JP3319845B2 - Input disconnection detection circuit, communication device, and input disconnection detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to communication devices, and more particularly to an input disconnection detection circuit for monitoring loss of input data in a communication device. 2. Description of the Related Art In various communication systems such as a mobile telephone system, an input disconnection detection circuit that monitors incoming input data, detects a state in which the input data is not received, and generates an alarm is used. For example, in a system with limited line resources such as a digital mobile phone system, it is necessary to prevent unnecessary line connection by cutting the line when input data no longer comes in, and to use resources effectively. Further, even in other large-capacity data communication systems in which line resources are strictly limited, it is essential to provide an input disconnection detection circuit because such loss of input data may lead to line failure. Particularly, in a wireless communication system using wireless data transmission, the line condition is easily affected by the environment, and therefore, a highly reliable input disconnection detection circuit is required.

[0002]

2. Description of the Related Art FIGS. 9A and 9B are block diagrams showing a configuration of a receiving side of a conventional radio transmission system having an input disconnection detecting circuit. Referring to the schematic diagram of FIG. 9A, the illustrated device has a configuration for performing baseband detection of an input wireless signal received by an antenna, amplified by a high-frequency amplifier RF, and then converted to an intermediate frequency IF. The baseband signal is output after passing through the switching circuit SW.

FIG. 9B shows the configuration of a baseband detector in more detail. Referring to the block diagram of FIG. 9B, the input data signal of the intermediate frequency IF supplied to the input terminal 11 is mixed with the local signal from the local oscillator 13 in the mixer 12, and the first signal having the phases orthogonal to each other. Quadrature baseband signal (horizontally polarized signal) and the second
Are formed, and these are LPF 13a and LPF 13b, respectively.
After that, the signal is supplied to the A / D converter 14b and converted into a digital signal. The digital baseband signals obtained by the A / D converters 14a and 14b pass through a transversal filter 15 and then are supplied to a processor 16 where the transmission data is demodulated. At that time, the filter 15 and the processor 16 constitute a demodulator 17. The data demodulated by the demodulator 17 is supplied with a similar demodulated data and supplied to a switching circuit 18 for selecting one demodulated data, and the data selected by the switching circuit 18 is output through an interface 19.

In the receiving apparatus having the configuration shown in FIG. 9B, there is provided an input disconnection detection circuit 20 for branching and inputting the intermediate frequency signal IF entering the input terminal 11, and the input disconnection detection circuit 2
0 detects the disappearance of the input RF signal by detecting the level of the intermediate frequency signal. Alternatively, the input disconnection detection circuit 20
May detect the level of the baseband signal output from the filter 13a or 13b. When the detection level falls below a predetermined value, the circuit 20 generates an alarm indicating the detection of an input disconnection and supplies the alarm to the processor 16.

[0005]

Referring to FIG. 10,
Circuit 20 is input an intermediate frequency signal or the rectifier 20 ₁ supplied baseband signal, the rectifier 20 LPF 20 ₂ for cutting a high frequency component from the output of _1, whereas in fed the output of the LPF 20 _2, the reference voltage on the other hand V _REF
Is supplied with, standards LPF 20 ₂ output level voltage V
The more a comparator 20 ₃ for generating an alarm output ALM when drops _REF below. That is, input disconnection detection circuit 20 of FIG. 10 performs an analog operation. Such an analog operation in the circuit for detecting the level of an input signal, high-frequency amplifier and intermediate frequency amplifier used in the amplification of the input signal, or easily threshold operation of the comparator 20 ₃ by the circuit parameters of the detection circuit is affected, Accordingly The setting of the reference voltage V _REF needs to be periodically calibrated, which is inconvenient. Further, the analog circuit as shown in FIG. 10 requires a relatively large area, and this has been a factor that hinders miniaturization especially in mobile wireless devices such as mobile phones.

Accordingly, it is a general object of the present invention to provide a new and useful input disconnection detection circuit which solves the above problems. A more specific object of the present invention is to provide an input disconnection detection circuit used in a digital data transmission device and detecting an input disconnection based on a combination of logical values in incoming digital data.

[0007]

According to the present invention, there is provided a demodulation means for demodulating an input signal to form a demodulated digital signal in the form of multi-bit data. A higher-order bit is extracted to form single-bit polarity data representing the polarity of the input signal, and bits other than the most significant bit of the demodulated digital signal are extracted to represent the amplitude of the input signal. Multi-valued Q including signal processing means 16 for forming amplitude data
In the AM communication device, in a detection circuit that detects an input interruption of an input signal, the most significant bit of the demodulated digital signal and the next bit of the most significant bit of the demodulated digital signal are separately separated into first and second bits, respectively. Supplied as a bit D ₁ and a second bit D ₂ , monitor for the appearance of a state in which the first bit and the second bit have different combinations of logic values, and if so, indicate that Bit pattern detecting means 1 for outputting a representative output signal
And an alarm generating means 2 for monitoring the output signal of the bit pattern for a predetermined time and generating an alarm when the output signal continues for the predetermined time. Or receiving means 12, 13, 13a, 13 for receiving an analog modulated signal.
b; demodulating means 14a and 14b for detecting an analog modulated signal received by the receiving means and forming a demodulated digital signal in the form of multi-bit data; and extracting the most significant bit of the demodulated digital signal and Signal processing for forming polarity data consisting of a single bit representing the polarity of an input signal, extracting bits other than the most significant bit of the demodulated digital signal, and forming amplitude data representing the amplitude of the input signal In the communication apparatus provided with the means 15, 16, and 17, the most significant bit of the demodulated digital signal and the bits of the demodulated digital signal other than the most significant bit are separately separated into first bits D _1. And a second bit D ₂ , wherein the first bit and the second bit have different logic value combinations. Bit pattern detecting means 1 for monitoring the occurrence of an error and outputting an output signal representing the occurrence of the error
And a communication device comprising: an alarm generating means 2 for monitoring an output signal of the bit pattern for a predetermined time and generating an alarm when the output signal is continuous for the predetermined time. Monitoring a single-bit data representing a polarity and multi-bit data representing an amplitude and monitoring a predetermined combination of logical values of upper predetermined bits among the single-bit data and the multi-bit data; And generating an alarm when the predetermined combination has continued for a predetermined period of time.

[0008]

FIGS. 11A and 11B show an example of a digital signal demodulated from an ordinary multilevel QAM modulated signal and A / D converted. Such multi-level QAM modulation is generally used in the wireless communication systems shown in FIGS. 9A and 9B. In the receiving device of FIG. 9, A / D converters 14a and 14b
Output an output signal as shown in FIGS.

[0009] Referring to FIG. 11 (A), A / D converter outputs a bit D _1, D _2, D ₃ multi-bit data composed of ..., the most significant bit D ₁ of the them A /
The polarity of the analog signal supplied to the D converter and the other bits D ₂ and D ₃ indicate the amplitude of the analog signal. Of the digital demodulated signals output from the A / D converters 14a and 14b, the content indicated by the bits D ₂ and D ₃ changes according to the content of the polarity bit D ₁ , and the processing device 16 responds to the content of the bit D ₁ To invert the logical values of the bits D ₂ and D ₃ . For example, when the polarity bit D ₁ is 1, if the values of the bits D ₂ and D ₃ are both 1, the maximum amplitude is indicated, while if the bits D ₂ and D ₃ are both 0, the minimum amplitude is indicated. . On the other hand, when the polarity bit D ₁ is 0, if the values of the bits D ₂ and D ₃ are both 1, it indicates the minimum amplitude, and if both of them are 0, it indicates the maximum amplitude.

[0010] By the way, when the transmission signal does not come in in such multi-level QAM modulation transmission, that is, when the input disconnection state occurs in the radio communication system of FIGS. 9A and 9B, the demodulated signal is transmitted. Converges to 0, so that if the value of the demodulated polarity bit D ₁ is 1, the value of the most significant amplitude bit D ₂ is 0, and if the value of the polarity bit D ₁ is 0, the most significant amplitude is D _1. the value of the bit D ₂ is situation occurs becomes 1. .

FIG. 1 is a diagram showing the principle of the present invention described above. In the drawing, D ₁ and D ₂ are the uppermost and two following digital signals demodulated from the quadrature phase signal component Q or I. Represents a bit. In the figure, the hatched area indicates that the first bit D ₁ is 1 and the second bit D ₂ is 0,
A state in which the bit D ₁ is 0 and the second bit D ₂ is 1 continuously appears temporally, and the present invention detects an input disconnection state in such a case. The state shown by the diagonal lines corresponds to the exclusive OR (EOR) of the first bit D ₁ and the second bit D ₂ , and therefore, the present invention provides the first bit D ₁
If the exclusive OR operation of the second bit D ₂ sequentially performed on the incoming digital signal, detects the input shutdown the results by monitoring a predetermined period. At that time, if the above condition is broken even once during the monitoring period, it is determined that there is incoming data,
Therefore, it is possible to avoid the problem of a malfunction in which the input is determined to be lost even though data is erroneously received.

FIG. 2 shows a schematic configuration of such an input disconnection detection circuit. Referring to FIG. 2, input data D ₁ and D ₂ are sequentially supplied to an EOR operation circuit 1, and the circuit 1 outputs a logical output signal representing a result of the EOR operation. The logic output signal of the circuit 1 is supplied to the decision circuit 2, and the decision circuit 2 detects that the logic value 1 continues for a predetermined period in the logic output signal from the EOR operation circuit 1, and outputs an alarm ALM.

According to the present invention, by detecting a state in which the combination of the first logical value and the second logical value is continuous in the polarity bit D ₁ and the most significant bit D ₂ of the amplitude bit, the input signal of the input signal is detected. Irrespective of the analog level, it is possible to detect the input disconnection state based on the content of the input signal, and it is possible to perform stable and highly reliable input disconnection detection.
Further, according to the present invention, since the input disconnection detection circuit can be configured by a digital circuit, the input disconnection detection circuit and the digital demodulation circuit can be integrally configured by an LSI, and the size of the device can be reduced. Will be possible. Further, in the present invention, the input disconnection detection circuit has a digital configuration, so that adjustment such as calibration is not required.

[0014]

FIG. 3 shows a data demodulation circuit having an input disconnection detection circuit according to a first embodiment of the present invention. In FIG. 3, the illustrated circuit corresponds to the circuit of FIG. 9B and is used in the wireless transmission system of FIG. 9A. In the figure, the same parts as those described above are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 3, in the present embodiment, one quadrature phase signal component, for example, multi-bit data corresponding to the signal component I output from the A / D converter 14a is supplied to the demodulator 17. At the same time, it is supplied to an input disconnection detection circuit 30 whose configuration is shown in detail in FIG. Or A /
After the multi-bit data output from the D converter 14a passes through the transversal filter 15, the input disconnection detection circuit 3
The circuit 30 may be configured to supply 0.

FIG. 4 shows the configuration of the input disconnection detection circuit 30.
Referring to FIG. 4, it has a schematic configuration corresponding to the configuration described in FIG. 2, and includes an exclusive OR circuit 1 and a determination circuit 2. The circuit 1 is supplied with the most significant bit constituting the multi-bit digital output signal from the A / D converter 14a and the two consecutive bits D ₁ and D ₂ successively from the A / D converter 14a, and obtains an exclusive OR thereof. consists _1, the arithmetic unit 30 ₁ supplies the operation result to the determination circuit 2.
At that time, the arithmetic unit 30 _1-bit D _1, D ₂ is (1,
0), (1, 0),... And outputs a logical signal “1” only when it changes.

On the other hand, the decision circuit 2 includes an oscillator 30_FourBy
First flip-flop 30 to be set_TwoIncluding
Lip flop 30_TwoThe clock input terminal CK of
EOR operator 30₁Are provided. Further
The high level bias voltage is applied to the flip-flop 30_Two
Is supplied to the D input terminal. Oscillator 30_FourIs the incoming bit
Operates at a frequency substantially lower than the stream bit rate
A predetermined number of bits D₁, D_TwoIs the EOR operator 30₁
Every time it arrives at the flip-flop 30 ₁Lise
Cut. Therefore, the flip-flop 30_TwoNo lycee
EOR operator 30 between reset and next reset₁of
If the output is all ones continuously, the flip-flop 30
_TwoThe output signal output to the Q output terminal of the
Will be retained. On the other hand, the operation unit 30₁Output once
Also transitions to 0, the state of the Q output terminal changes to the data input terminal D
The state transits to the high level state in accordance with the state.

The output data outputted from the Q output terminal of flip-flop 30 _2, oscillator 30 ₄ is supplied to from the D input terminal of flip-flop 30 ₃ receiving clock is latched until the next clock. That is,
Flip-flop 30 ₃ latches the output of flip-flop 30 ₂ to the Q output terminal, and outputs as an alarm signal after logically inverted by the inverter 30 _5. In other words, only when the EOR operator 30 ₁ continuously outputs the output signal “1” while the input is disconnected, the inverter 30 ₅
Goes high and is signaled to processor 16. Otherwise, the output of the inverter 30 ₅ is held low. At that time, the oscillation frequency of the oscillator 30 ₄ determines the monitoring period for monitoring the input shutdown state.

FIG. 5 shows the operation timing of the circuit of FIG.
It is a timing chart. In the figure, waveforms A to E correspond to those in FIG.
It shows the signal waveform that appears at the corresponding node in the circuit.
You. Referring to FIG. 5, as shown by waveform B, waveform E
Oscillator 30 shown_FourAt the rising edge of the output signal pulse
Top flop 30_TwoAre periodically reset. This state
State, for example, period T₁Incoming signal as in
Bit D corresponding to ₁, D_TwoChanges over time
In the case of the rising edge of the waveform A
Flip-flop 30_TwoIs high as shown by waveform B.
Set on the bell. Period T as in the example shown₁End of
If waveform B is set to high level,
T_TwoAt the beginning of the flip-flop 30_TwoOutput
The signal C goes high in response to the rising edge of the clock signal E.
And the output signal D of the circuit 30
Is set to low level.

On the other hand, as in the period T _2, the combination of the input bits D ₁ and D ₂ is (1, 1) over the entire period.
If it does not change at (0) or (0,1), the signal waveform A does not change from the low level state. Therefore, the output signal waveform of the flip-flop 30 ₂ is reset to the beginning period T ₂ B is not to be set to a high level, the period T
Maintain the low level state for the entire period of ₂ . For this reason, at the beginning of the period T _3, flip-flop 30 ₃
Latches the low level state as shown in waveform C. As a result, the circuit 30 is as shown by the waveform D, and trigger an alarm in the period T _3. That is, the circuit 30 when the input for one period of the clock signal oscillator 30 ₄ outputs no, to form an output signal representing the input interruption.

Further, when the input again as shown in the next period T ₃ in the waveform A is detected, an alarm is released. FIG. 6 illustrates the principle of another embodiment of the present invention. FIG.
In not only the most significant bit D ₂ of the amplitude bits are detected more accurate input interruption even with the next bit D _3.

Referring to FIG. 6, in the present embodiment,
If the polarity bit D ₁ is 1, the amplitude bits D ₂ , D ₃
If both are 0, it is determined that the input has been interrupted. When the polarity bit D ₁ is 0, the amplitude bits D ₂ , D ₃
When both are 1, it is determined that the input has been interrupted. Such a determination is made by a logical operation using D ₁ , D ₂ , D ₃ instead of the exclusive OR operation of bits D ₁ , D ₂ D ₁ · / D ₂ · / D ₃ + / D ₁ · D ₂ · D ₃ can be achieved by the execution. According to the present embodiment,
As can be seen from FIG. 6, more accurate input disconnection detection becomes possible.

FIG. 7 shows a configuration of a logic circuit 1 'for performing such a logical operation. Referring to FIG. 7, A circuit 1 'is supplied to the input data bits D ₁ to the first input terminal
It includes ND gate 40 _1, the AND gate 40 ₁ has a second and a third input terminal supplied logically inverted signal of the input data bit D _2, D ₃ from the inverter 40 _4, 40 _5, respectively. Similarly, the input data D
The _first logic inversion signal is supplied from the inverter 40 ₃ to the first input terminal, the AND having second and third input terminals supplied with input data bit D ₂ and D ₃ directly
Gate 40 ₂ is provided, the output of gate 40 ₁ and 40 ₂ after passing through the OR gate 40 _6, are supplied to the determination circuit 2 described the configuration in FIG. 4 above.

FIG. 8 shows still another embodiment of the present invention.
In FIG. 8, the same reference numerals are given to the parts described above,
The description is omitted. In this embodiment, in each of the quadrature phase signal components Q and I, the input disconnection state is independently detected by the input disconnection detection circuit 30 and the input disconnection detection circuit 50 having the same configuration, and the alarm output from each circuit is output. The signal is supplied to the processor 16 via the AND gate 51. In the embodiment of FIG. 8, the detection of the input disconnection can be executed independently for the Q component and the I component, so that a highly reliable input disconnection detection operation can be realized.

The present invention is not limited to the above embodiment, and various modifications and changes can be made within the gist of the present invention.

[0026]

According to the present invention, a state in which a combination of a first logical value and a second logical value appears in a most significant bit of a polarity bit and an amplitude bit for a predetermined time in a multilevel QAM signal is detected. Thus, it is possible to detect an input disconnection state based on the content of the input signal, regardless of the analog level of the input signal, and it is possible to perform stable and reliable input disconnection detection. According to the present invention,
Since the input disconnection detection circuit can be configured by a digital circuit, the input disconnection detection circuit and the digital demodulation circuit are
It is possible to configure the device with SI, and it is possible to reduce the size of the device. Further, in the present invention, the input disconnection detection circuit has a digital configuration, so that adjustment such as calibration is not required.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a schematic configuration of an input disconnection detection circuit according to the present invention.

FIG. 3 is a diagram showing an example of a wireless transmission system using an input disconnection detection circuit according to one embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of an input disconnection detection circuit used in the system of FIG. 3;

FIG. 5 is a timing chart illustrating the operation of the circuit of FIG. 4;

FIG. 6 is a diagram illustrating the principle of another embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of an input disconnection detection circuit according to the embodiment of FIG. 6;

FIG. 8 is a diagram showing a configuration of a wireless transmission system using an input disconnection detection circuit according to still another embodiment of the present invention.

9A is a diagram illustrating a schematic configuration of a conventional wireless transmission system, and FIG. 9B is a diagram illustrating an example of a multilevel QAM wireless transmission system using a conventional input disconnection detection circuit.

FIG. 10 is a diagram showing a configuration of a conventional input disconnection detection circuit.

FIGS. 11A and 11B are diagrams showing a configuration of a digital demodulated signal obtained in the wireless transmission system shown in FIGS. 9A and 9B.

[Explanation of symbols]

_1, 30 ₁ EOR operation circuit 2 Judgment circuit 11 Input terminal 12 Mixer 13 Local oscillator 13a, 13b LPF 14a, 14b A / D converter 15 Transversal filter 16 Processor 17 Demodulator 18 Switching circuit 19 Interface 20, 30, 50 Input off detection circuit 30 _2, 30 ₃ flip-flop 30 ₄ oscillator 30 _5, 40 _3, 40 _4, 40 ₅ inverter 40 ₆ OR gates 40 _1, 40 _2, 51 the AND gate

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Koshiro Akinaga Nippon Telegraph and Telephone Corporation, 1-6-1, Uchisaiwai-cho, Chiyoda-ku, Tokyo (56) References JP-A-5-336182 (JP, A) JP-A Sho 61-194952 (JP, A) JP-A-54-55358 (JP, A) JP-A-54-80061 (JP, A) Jiko 5-11593 (JP, Y2) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (9)

(57) [Claims] A demodulation means (14a, 14a) for demodulating an input signal and forming a demodulated digital signal in the form of multi-bit data.
b); extracting the most significant bit of the demodulated digital signal to form polarity data of a single bit representing the polarity of the input signal, and forming polarity data of the demodulated digital signal other than the most significant bit. An input disconnection detection circuit for detecting input disconnection of an input signal, wherein the input disconnection detection circuit is used in a multi-level QAM communication device having signal processing means (16) for extracting bits and forming amplitude data representing the amplitude of the input signal; The most significant bit of the demodulated digital signal and the next bit after the most significant bit of the demodulated digital signal are separately supplied as a _first bit (D ₁ ) and a second bit (D ₂ ), respectively. , The first bit and the second bit
Bit pattern detection means (1) for monitoring the appearance of a state in which the bits have different combinations of logical values, and outputting an output signal when the state appears;
An input disconnection detection circuit, comprising: an alarm generation means (2) for monitoring an output signal of the bit pattern for a predetermined time and generating an alarm when the output signal continues for the predetermined time. 2. The method according to claim 1, wherein said bit pattern detection means comprises:
2. The input disconnection detecting circuit according to claim 1, wherein the output signal is formed by detecting a case where the logical values of the first and second bits (D ₁ , D ₂ ) are different from each other. 3. The bit pattern detection means (1) is supplied with the first and second bits (D ₁ , D ₂ ),
3. An exclusive OR operation circuit (30 ₁ ) for obtaining an exclusive OR based on the logical values of the first and second logical bits and outputting the result as the output signal. 2. The input disconnection detection circuit according to 1. 4. The method according to claim 1, wherein the bit pattern detecting means includes:
Bit D of 1₁And the second bit D_TwoBesides the above
Of the second digital signal D _TwoThe next
Bit D of 3_ThreeAre further supplied, and the logical operation D₁・ / D
_Two・ / D_Three+ / D₁・ D_Two・ D_ThreeLogic circuit to perform
The input disconnection according to claim 1, wherein (1 ').
Detection circuit. 5. The alarm generating means is supplied with an oscillator (30 ₄ ) oscillating at a predetermined frequency, and a frequency signal of the predetermined frequency generated by the oscillator, and is periodically reset at the predetermined frequency. Detection circuit (30 ₂ , 3
0 ₃ ), the detection circuit is supplied with the output signal from the bit pattern detection means, and the output signal is different from the first bit in logic value and the second bit in logic value. holding the first state to indicate continuously the state, according to claim 1, characterized in that the output signal is formed of a latch circuit (30 ₂₎ for holding a second state when the changes Input disconnection detection circuit. 6. Receiving means (12, 13, 13a, 13b) for receiving an analog modulated signal; demodulation for detecting an analog modulated signal received by said receiving means to form a demodulated digital signal in the form of multi-bit data. Means (14a, 14
b); extracting the most significant bit of the demodulated digital signal to form polarity data of a single bit representing the polarity of the input signal, and forming polarity data of the demodulated digital signal other than the most significant bit. A communication apparatus comprising: signal processing means (15, 16, 17) for extracting bits to form amplitude data representing the amplitude of the input signal, wherein the signal processing means includes: a most significant bit of the demodulated digital signal; Are supplied separately as a first bit (D ₁ ) and a second bit (D ₂ ), respectively, except for the most significant bit, and the first bit and the second bit are different from each other. Bit pattern detection means (1) for monitoring the appearance of a state having a combination of logical values, and outputting an output signal indicating the appearance when the state appears
And an alarm generating means (2) for monitoring an output signal of the bit pattern for a predetermined time and generating an alarm when the output signal continues for the predetermined time. 7. A quadrature detector (12, 13) for separating a first quadrature signal component (Q) and a second quadrature signal component (I) whose phases are orthogonal to each other from a received modulation signal.
The demodulation means (14a, 14b) forms the demodulated digital signal for each of the first quadrature signal component and the second quadrature signal component, and the bit pattern detection means (1,20) And the alarm generating means (2, 2
The communication device according to claim 6, wherein 0) is provided corresponding to one of the first and second orthogonal signal components. 8. The receiving means includes quadrature detection means for separating a first orthogonal signal component (Q) and a second orthogonal signal component (I) whose phases are orthogonal to each other from a received modulation signal, and the demodulation means (14a, 14b) forms the logical bit stream for each of the first quadrature signal component and the second quadrature signal component, and the bit pattern detecting means and the alarm generating means are configured to control the first and the second signal components. First and second input disconnection detection circuits (30, 50) are provided corresponding to the second orthogonal signal components, respectively, and the first and second input disconnection detection circuits are independent of each other. 7. The communication device according to claim 6, wherein input disconnection is detected. 9. A single bit data representing a polarity and a multi-bit data representing an amplitude are supplied, and a predetermined combination appears for a combination of logical values of upper predetermined bits of the single-bit data and the multi-bit data. And a step of generating an alarm when the predetermined combination has continued for a predetermined time.