JP3317847B2 - Charge pump circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge pump circuit provided with a differential amplifier having a transistor configuration on an input side and amplifying and outputting a high-frequency input signal following a signal frequency, and more particularly to mobile communication by satellite communication. The present invention relates to a charge pump circuit that can operate in a wide output dynamic range at an ultra-high frequency, a low voltage, and a low power consumption.

[0002]

2. Description of the Related Art Conventionally, this kind of charge pump circuit has
As shown in FIG. 3, two npn transistors Q10
1 and Q102, and a pnp transistor Q103 which connects this output to the base and amplifies it.

If this connection is explained in detail, first, np
The n-transistor Q101 has the base connected to the input terminal Ti101, the collector connected to the power supply Vcc, and the emitter connected to the ground via the constant current source I10. The npn transistor Q102 has the base connected to the input terminal Ti102, the collector connected to the power supply Vcc via the resistor R101, and the emitter connected to the ground via the constant current source I10.

Accordingly, one of the constant current sources I10 is connected in duplicate to the emitters of the transistors Q101 and Q102, and is output by the resistor R101. As described above and shown, the transistors Q101 and Q102 form a differential circuit having a constant current source I10, and the resistor R101 is a load resistor. The output of this differential circuit is the connection between resistor R101 and transistor Q102.

A pnp transistor Q103 has a base connected to the collector of the transistor Q102 and a resistor R101,
The output terminal To100 is connected to the collector, and the resistor R10 is connected to the emitter.
2 are connected to each other via a power supply Vcc.

Therefore, the output of the differential circuit is input to the base of the pnp transistor Q103 as an input signal of the common emitter circuit formed by the pnp transistor Q103 and the resistor R102. Also, input terminals Ti101, Ti10
2 In each case, pulses with phases opposite to each other
Transistors Q101 and Q102 constituting a differential amplifier perform a switching operation by this pulse.

Next, the operation function will be described with reference to FIG.

Now, a low level potential V is applied to the input terminal Ti101.
When the high-level potential VOH2 is input to the input terminal OL1 and the input terminal Ti102, if the constant current source I10 flows the current i0, the collector current ic1 becomes "0 (zero)" in the transistor Q101, while the transistor Q102 outputs The collector current ic2 becomes "i0".

On the other hand, the output voltage of the differential circuit, that is, the voltage at the connection between the resistor R101 and the transistor Q102 is "Vcc-r1 * ic2" with respect to the voltage Vcc of the voltage V101 and the resistance r1 of the resistor R101. , The collector current ic3 of the pnp transistor Q103 is expressed by the following equations 1 and 2 with respect to the base-emitter voltage VBE3 of the pnp transistor Q103 and the resistance value r2 of the resistor R102.

Ic3 = (r1 × ic2−VBE3) / r2 (1) = (r1 × i0−VBE3) / r2 (2) The voltage value VBE3 is substantially constant due to the transistor manufacturing process, and is approximately 0.8V. It is.

The maximum output voltage value VOH3 of the output terminal To100 is obtained by the following equations 3 and 4 with respect to the collector-emitter saturation voltage VCE (SAT) 3 of the pnp transistor Q103.

VOH3 = Vcc− (ic3 × r2 + VCE (SAT) 3) (3) = Vcc− (r1 × ic2−VBE3) −VCE (SAT) 3 (4) where the saturation voltage value VCE (SAT) 3 Is substantially determined by the manufacturing process of the transistor and is about 0.2 to 0.3 V.

Next, when the high-level potential VOH1 is input to the input terminal Ti101 and the low-level potential VOL2 is input to the input terminal Ti102, the collector current ic1 of the transistor Q101 becomes "i0" with respect to the current i0 of the constant current source I10.
In the transistor Q102, the collector current ic2 becomes "0 (zero)".

Therefore, from the above equation (1), the output terminal To100
Is the following assuming that the current value ic2 is "0" and the voltage value VBE3 is "0".

Ic3 = (r1 × ic2-VBE3) / r2 = 0 Therefore, the collector current ic3 of the pnp transistor Q103
Does not flow.

At this time, the emitter current ie1 of the transistor Q101 is expressed by the following equation 5, and the inflow current it1 of the input terminal Ti101 is expressed by the following equation 6.

Ie1 = (VOH1−VBE1) / r2 (5) it1 = ie1−ic1 = (VOH1−VBE1) / r2−i0 (6) The upper limit frequency that can be operated in this circuit is the cut-off frequency ft of the npn transistor. Is higher than the cut-off frequency ft of the pnp transistor, and is determined by the frequency value f of the cut-off frequency ω- _3dB (= 2πf) of the common emitter circuit formed by the pnp transistor Q103 and the resistor R102, and is expressed by the following equation 7.

[0018] Here, "β0" is a common emitter current amplification factor (hFE),
"Ic" is the collector current, "VT" is the emitter-base voltage, which is a constant value of about 26 mV at room temperature.
“Cπ” is a base-emitter capacitance.

As described above, in the integrated circuit, the operation of the pnp transistor by the common emitter circuit generally has poor frequency characteristics, has a low upper limit frequency, and has a disadvantage that the gain in a high frequency band is reduced. In addition, the charge pump circuit has a problem that a signal having a high frequency and a short pulse width cannot be output, so that the frequency accuracy is lowered and the emitter ground current amplification factor (hFE) is weak.

A technique for solving this problem is described in, for example, Japanese Patent Application Laid-Open No. 3-29571. In this circuit, a common base pnp transistor that does not deteriorate the frequency characteristics in a high frequency band is used.

This circuit has a circuit for inputting a signal to an input electrode of at least one of a pair of npn transistors forming a differential pair of the differential amplifier, and is connected to an output voltage of the transistor as a load of the differential amplifier. And a constant current source for commonly supplying a current flowing to the output electrode and a current flowing to the common base transistor.

Next, the circuit described in this publication will be described with reference to FIG.

As shown in FIG. 4, in this circuit, two npn transistors Q201 and Q202 are provided on the input side, and three pnp transistors Q203 to Q205 are provided on the output side.
Is used.

The npn transistor Q201 has the base connected to the input terminal Ti201, the collector connected to the emitter of the pnp transistor Q203 and the collector of the pnp transistor Q204, and the emitter connected to ground via the resistor R201. The npn transistor Q202 has the base connected to the input terminal Ti202, the collector connected to the power supply V201, and the emitter connected via the resistor R202 to the npn transistor Q202.
The emitter of the n-transistor Q201 and the resistor R201 are connected.

Therefore, the ground level via the resistor R201 is np
It is connected to the emitter of the n-transistor Q201 and the emitter of the npn transistor Q202 via the resistor R202.

The pnp transistor Q203 has the base connected to the power supply V201, the collector connected to the output terminal To200, and the emitter connected to the collectors of the npn transistor Q201 and the pnp transistor Q204. The pnp transistor Q204 has a pnp
Connected to the base of transistor Q205 and np
The collector of the n-transistor Q201 and the emitter of the pnp transistor Q203 are connected to each other, and the power supply V201 is connected to the emitter via a resistor R203. pn
The p-transistor Q205 has a base connected to the base of the pnp transistor Q204, a collector connected to the ground via a constant current source I20, and an emitter connected to a power supply V20 via a resistor R204.
1, each connected.

In this connection circuit, the two npn transistors Q201 and Q202 form a differential circuit, and the output of this differential circuit sends out a signal as the collector current ic1 of the npn transistor Q201.
204 is the active load. The two pnp transistors Q204 and Q205 form a current mirror circuit. The saturation currents (IS: values determined by the manufacturing process and the emitter area of the transistors) of the pnp transistors Q204 and Q205 are the same, and the resistors R203 and R204 respectively. Are equal, the current value i0 of the constant current source I20 is
The collector current ic4 of the pnp transistor Q204 with respect to
Becomes a constant value of the current value i0 together with the collector current ic5 of the pnp transistor Q205.

That is, the pnp transistors Q204 and Q204
205 Each collector current is the current value i of the differential circuit output
The current value i0 is always constant irrespective of c1.

Next, the operation function will be described with reference to FIG.

When the low-level potential VOL1 is input to the input terminal Ti201 and the high-level potential VOH2 is input to the input terminal Ti202, the differential circuit functions as a switch, and the collector current ic1 of the npn transistor Q201 becomes "0". Therefore, all the collector current ic4 of the pnp transistor Q204 flows into the emitter of the pnp transistor Q203, and if the base current iB3 of the pnp transistor Q203 is ignored, the collector current ic3 of the pnp transistor Q203, which becomes the output terminal current, becomes equal to the pnp transistor Q203.
The current value i0 is equal to the collector current ic4 of 204.

In this case, the maximum value VOH3 of the output voltage of the output terminal To200 is equal to the collector-emitter saturation voltage VCE (SA) of the same pnp transistors Q203 and Q204.
T), and when the voltage V202 is the voltage value Vref,
Becomes

VOH3 = Vref−VCE (SAT) (8) Here, since the voltage value Vref can be set arbitrarily, pnp
The transistors Q203 and Q204 are designed so that the respective collector-emitter voltages VCE3 and VCE4 are higher than the collector-emitter saturation voltage VCE (SAT). If the resistances r3 and r4 of the resistors R203 and R204 are set to "0" in design, the following equation (9) is obtained.

VOH3 = Vcc−r3 × ic4−VBE4−2VCE (SAT) = Vcc−VBE4−2VCE (SAT) (9) On the other hand, the collector current ic2 flowing through the npn transistor Q202 depends on the voltage VOH2 of the input terminal Ti202. . Here, the collector current i.sub.c of the npn transistor Q201 in the cut-off state with respect to the collector current i.sub.c = 0 and the base-emitter voltage V.sub.BE2 of the npn transistor Q202 is represented by i.
c2 is obtained by the following equation (10).

Ic2 = (VOH2−VBE2) / (r2 + r1) (10) Next, the case where the high level potential VOH1 is input to the input terminal Ti201 and the low level potential VOL2 is input to the input terminal Ti202 will be described.

In this state, the cut-off npn transistor Q202 has a collector current ic2 = 0, and the collector current ic4 = i0 always flowing through the pnp transistor Q204.
Flows as the collector current ic1 of the npn transistor Q201. Emitter current ie1 of npn transistor Q201
Depends on the input level potential VOH1 of the input terminal Ti201 and is obtained by the following equation (11).

Ie1 = (VOH1−VBE1) / r1 (11) In this state, the base current ib1 of the npn transistor Q201 is expressed by the following equation (12).

Ib1 = ie1-ic1 = (VOH1-VBE1) / r1-i0 (12) That is, the npn transistor Q201 has the base current i
b1 depends on the input level potential VOH1 and is saturated. Therefore, the collector-emitter voltage VCE1 of the npn transistor Q201 becomes the saturation voltage VCE (SAT) (approximately 0.3
V).

In this state, the collector current ic4 of the pnp transistor Q204 is all drawn as the collector current ic1 of the npn transistor Q201.
The collector current ic3 of the p transistor Q203 becomes "0", and there is no output current from the output terminal To200.

The operating frequency in this circuit is determined by the pnp transistor Q203 whose base is grounded, and is obtained by the following equation 13 based on the above equation 7.

[0040]

[0041]

Among the above-mentioned conventional charge pump circuits, the circuit shown in FIG. 3 has a low operating frequency as described above, and has a high frequency and a pulse width as a charge pump circuit. There is a problem that a short signal cannot be output, the frequency accuracy is reduced, and the device is susceptible to variations in the common emitter current amplification factor (hFE).

In the circuit disclosed in the official gazette for solving this problem, a pnp transistor with a common base is used, which does not deteriorate the frequency characteristics in a high frequency band.
In this circuit configuration, the output dynamic range is narrow and P
When used in an LL (Phase-Locked Loop) circuit, there is a problem that the lock range is narrowed.

The reason for this is that since a pnp transistor is used in series as a load, the saturation voltage between the collector and the emitter of the transistor overlaps by two.

An object of the present invention is to provide a charge pump circuit which can be used in mobile communication by satellite communication or the like and which can operate at a very high frequency, low voltage, and low power consumption with a wide output dynamic range.

[0045]

The charge pump circuit according to the present invention has a base as a first means.
A first npn transistor whose collector is connected to a first constant voltage source via a load resistor, whose emitter is grounded via a constant current source, and whose base is the first input terminal. Is connected to a second input terminal to which a signal having an opposite phase relationship to the signal supplied to the first constant voltage source is connected to the connection point between the first constant voltage source and the load resistance, and the emitter is connected to the first input terminal. wherein the of the npn transistor and a second npn transistor being connected to a connection point between the constant current source, a base connected to a second constant voltage source for supplying the first voltage lower than the constant-voltage source, Collector is output terminal
And a pnp transistor having an emitter connected to a connection point between the collector of the first npn transistor and the load resistor.

In the above means, the output transistor p
On the one hand, the np transistor can be operated at a common base, so that the upper limit frequency can be increased. On the other hand, by driving only with a resistive load, the maximum output voltage can be set without restriction on the saturation voltage of the transistor.

Further, as another specific means of the charge pump circuit according to the present invention, a gate is connected to a first input terminal, a drain is connected to a first constant voltage source via a load resistor, A source is connected to a first field-effect transistor grounded via a constant current source, and a gate is connected to a second input terminal to which a signal having a reverse phase relationship to a signal applied to the first input terminal is applied. And the drain is the first
A second field effect transistor connected to a connection point between the constant voltage source and the load resistor, and a source connected to a connection point between the first field effect transistor and the constant current source;
A gate is connected to a second constant voltage source that supplies a lower voltage than the first constant power supply, a drain is connected only to the output terminal, and a source is a drain of the first field effect transistor, the load resistance, And a third field-effect transistor connected to the connection point.

[0048]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. In the charge pump circuit shown in FIG. 1, two npn transistors Q01 and Q02 forming a differential amplifier having a low current source I0 having a constant current i0 on the input side, and an output of the differential amplifier are connected to a load resistor R01. Is provided as one output transistor.

The difference from the prior art is that the output transistor p
This means that the np transistor Q03 operates with the base grounded and is driven by the output of only the load resistor R01 of the differential amplifier on the input side.

First, the details of the connection will be described with reference to FIG.

The npn transistor Q01 has the base connected to the input terminal Ti1, the collector connected to the constant voltage source V01 via the load resistor R01, and the emitter connected to the ground via the constant current source I0. npn transistor Q02
Has a base connected to an input terminal Ti2, a collector connected directly to a constant voltage source V01, and an emitter connected to the earth via a constant current source I0. Accordingly, one end of the constant current source I0 is connected to the emitter of each of the npn transistors Q01 and Q02.

The pnp transistor Q03 has a base connected to the constant voltage source V02, a collector connected to the output terminal To0, and an emitter connected to the constant voltage source V01 via the load resistor R01. Therefore, one end of the load resistor R01 has p
The emitter of np transistor Q03 and the collector of npn transistor Q01 are connected.

Next, main operation functions will be described with reference to FIG.

A negative-phase pulse is input to each of the input terminals Ti1 and Ti2, and each of the npn transistors Q01 and Q02 constituting the differential amplifier operates as a switch.

First, the low level potential V is applied to the input terminal Ti1.
OL1, when the high level potential VOH2 is input to the input terminal Ti2, the collector current ic1 of the npn transistor Q01
Becomes "0" (zero), while the npn transistor Q02
Is the current i0 of the constant current source I0.

The output current of the output terminal To0 in this state is the collector current ic3 of the pnp transistor Q03, the voltage Vcc of the constant voltage source V01 and the voltage VREF of the constant voltage source V02.
, The base-emitter voltage VBE3 of the pnp transistor Q03, and the resistance r1 of the load resistor R01, the following equation 14 holds.

Ic3 = (Vcc−Vref−VBE3) / r1 (14) When the current value ic3 = 125 μA, the voltage value Vcc = 3V, and the voltage value VBE3 = 0.8V, which are adopted in the normal design, are substituted. The voltage value Vref and the resistance value r1 are given by the following equation 1.
5 is adjusted.

125 (μA) = (3-Vref-0.8) (V) / r1 (MΩ) (15) Normally, the voltage value Vref is a value of 2.1 V obtained by the following equation 16 in consideration of the output dynamic range. Set.

Vref = Vcc−100 (mV) −VBE = 3−0.1−0.8 = 2.1 (V) (16) The maximum output voltage VOH3 of the output terminal To0 is expressed by the following equation (17). When the voltage value Vref is approximately 2.1 V, p
Since the collector-emitter saturation voltage VCE (SAT) 3 of np transistor Q03 is approximately 0.3V, the maximum output voltage VOH3 is calculated to be 2.6V.

VOH3 = Vref + VBE-VCE (SAT) 3 (17) = 2.1 + 0.8-0.3 = 2.6 (V) On the other hand, a high level potential VOH1 is applied to the input terminal Ti1, and a low level is applied to the input terminal Ti2. When the potential VOL2 is input, n
Collector current ic1 of pn transistor Q01 is constant current source I
0, while the collector current ic2 of the npn transistor Q02 becomes "0" (zero).

In this state, since the current i0 flows through the load resistor R01, the voltage (i0.times.r1) generated in the load resistor R01.
), The collector current ic of the pnp transistor Q03
3 is cut to “0”.

On the other hand, the inflow current iTi from each of the input terminals Ti1 and Ti2 is given by the following equation 18 regardless of the input amplitude.

ITi = i0 / hFE (18) The upper limit frequency of the operation is determined by the following equation 19 based on the above equation 7 of the pnp transistor Q03 whose base is grounded.

[0065] In the above description, the transistor is described as a bipolar transistor only. However, the present invention can be applied to other transistors, for example, a MOS (metal oxide semiconductor) FET or a GaAs (gallium arsenide) FET using a field effect transistor (FET).

FIG. 2 is a circuit diagram showing an embodiment of a charge pump circuit according to the present invention constituted by FETs.
In the charge pump circuit shown in FIG. 2, two field effect transistors Q11 and Q12 forming a differential amplifier having a low current source I0 of a constant current i0 on the input side, and the output of the differential amplifier is connected to a load resistor R11. Is provided as one output transistor, and a constant voltage source V11 is connected to the differential circuit, and a constant voltage source V12 is connected to the gate of the field effect transistor Q13.

The connection and operation functions are the same as those described with reference to FIG. 1. In this embodiment, the npn transistor or the pnp transistor is replaced with a field effect transistor, and the base, collector and emitter are replaced with gate, drain and source, respectively. Become.

[0068]

As described above, according to the present invention, two transistors having a constant current source on the input side and constituting a differential amplifier, and an output transistor for obtaining the output of the differential amplifier from a load resistor are provided. A constant voltage source is supplied and connected to the differential circuit, and a predetermined constant voltage source is connected to the base or gate of the output transistor.

With this configuration, the pnp transistor, which has a low operating frequency due to the circuit configuration and cannot output a signal with a high frequency and a short pulse width, has a circuit configuration based on the grounded base, and has a high frequency band. The characteristics can be improved. Further, with this configuration, the frequency accuracy is increased, the resistance to the variation of the grounded emitter current amplification factor (hFE) is strong, and the comparison frequency can be increased. Therefore, the lock-up time for the PLL circuit can be reduced.

Further, since the output of the differential amplifier is obtained only from the load resistance, other complicated conditions are eliminated, the dynamic range of the output can be designed wide, and the lock range can be expanded when used in a PLL circuit. be able to.

As a result, it is possible to obtain a charge pump circuit that can operate in a wide output dynamic range at ultra-high frequency, low voltage, and low power consumption, which is used in mobile communication by satellite communication or the like.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a functional block diagram showing another embodiment of the present invention.

FIG. 3 is a functional block diagram showing an example of the related art.

FIG. 4 is a functional block diagram showing another example of the related art.

[Explanation of symbols]

 I0 Constant current source Q01-Q03, Q11-Q13 Transistor R01, R11 Load resistance Ti1, Ti2 Input terminal To0 output terminal V01, V02, V11, V12 Constant voltage source

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-6-338787 (JP, A) JP-A-53-23063 (JP, A) JP-A-5-121971 (JP, A) 47233 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03F 3/45 H03F 3/343

Claims (4)

(57) [Claims] A base connected to a first input terminal, a collector connected to a first constant voltage source via a load resistor,
A base connected to a first npn transistor whose emitter is grounded via a constant current source, and a base connected to a second input terminal to which a signal having a phase opposite to that of a signal applied to the first input terminal is applied; A second npn transistor having a collector connected to a connection point between the first constant voltage source and the load resistor, an emitter connected to a connection point between the first npn transistor and the constant current source, and a base; There is connected to the second constant voltage source for supplying the first voltage lower than the constant-voltage source, a collector connected only to the output terminal, an emitter and a collector of said first npn transistor and said load resistor And a pnp transistor connected to a connection point of the charge pump circuit. 2. The voltage value Vref of a second constant voltage source according to claim 1, wherein the voltage value Vref of the first constant voltage source is changed from the voltage value Vcc of the first constant voltage source to a voltage value V base -emitter of the pnp transistor.
A charge pump circuit, which is set to a value obtained by subtracting a product of BE, a resistance value rl of the load resistor, and a collector current value ic3 of the pnp transistor. 3. The product according to claim 2, wherein the product of the resistance rl of the load resistor and the collector current ic3 of the pnp transistor is 100 in consideration of an output dynamic range.
A charge pump circuit set to millivolt (mV). A gate connected to the first input terminal; a drain connected to the first constant voltage source via a load resistor;
A source is connected to a first field-effect transistor grounded via a constant current source, and a gate is connected to a second input terminal to which a signal having a reverse phase relationship to a signal applied to the first input terminal is applied. A second field effect transistor having a drain connected to a connection point between the first constant voltage source and the load resistor, and a source connected to a connection point between the first field effect transistor and the constant current source And the gate is the first
Is connected to the voltage lower than the constant-voltage source to a second constant voltage source for supplying a drain connected only to the output terminal, a connection point between the source and the drain and the load resistance of the first field effect transistor And a third field-effect transistor connected to the charge pump circuit.