JP3317720B2 - High-speed pull-in adaptive control demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulator for receiving a PSK modulated wave of a digital portable / car phone, and more particularly to an adaptive carrier synchronization (ACT).
The present invention relates to an adaptive control type demodulator (hereinafter, referred to as an ACT demodulator) having a (rrier Tracking) type synchronous detector.

Since terminals such as mobile phones are required to be small and operate continuously for a long time, it is indispensable to reduce the size of a battery occupying a large part of the terminal, that is, to operate the circuit with low power consumption. Therefore, the reception operation is performed intermittently during the standby operation of the telephone, and the intermittent operation for suppressing the power consumption is performed. In intermittent operation, the ratio of the time that the receiver is operating and the time that it is stopped determines the average power consumption of the receiver. Therefore, it is desirable that this ON / OFF ratio be as small as possible. Therefore, the demodulator is required to have a short time (rise time) from the start of the demodulation operation until a normal demodulation result is obtained. The present invention provides an ACT demodulator with a reduced rise time.

[0003]

2. Description of the Related Art Conventionally, as a QPSK demodulation method for mobile communication, an ACT type demodulator having good anti-fading characteristics has been proposed (Ref. 1). The ACT demodulator is
It has an ACT type synchronous detector that performs detection by controlling the phase of the reproduced carrier used for the synchronous detector so as to adaptively follow the phase of the carrier detected one symbol before. In this ACT demodulator, data cannot be reproduced because correct carrier tracking is not performed until symbol clock synchronization is established. On the other hand, the symbol clock information output from the ACT demodulator to the bit synchronization circuit BTR when the carrier tracking is not performed is not valid. For this reason, conventionally, both carrier tracking and BTR pull-in proceed while affecting each other to be in a steady state, thereby establishing synchronization.

In pulling in two loops of carrier tracking and symbol clock synchronization, ACT
, The time constant of carrier tracking is much smaller than that of BTR, so that the pull-in time of BTR is dominant in most cases. In mobile communication, a filter having a large time constant is used for the BTR in order to prevent the jitter of the reproduced symbol clock from increasing due to noise, fading, and the like, thereby preventing the demodulation characteristics from deteriorating. For this reason, the pull-in time of the BTR usually requires several hundred to several thousand symbols. However, in the intermittent operation of the receiver of the car telephone system which is currently considered for application,
It is desirable that the pull-in time is less than one hundred symbols.
For this reason, it is necessary to devise the BTR in some way to perform high-speed pull-in. As one method of speeding up the BTR pull-in, speeding up by an initial phase preset has been proposed (Reference Document 2). This is at the data change point of the first received signal received after the operation of the receiver starts, and the BTR
This is a method of forcibly presetting the reproduction phase of the data and for bringing in the data at a high speed.

Reference 1: Shigeki Saito, Haruo Yamamoto, Yasushi Yamao: "All-digital ACT synchronous detection circuit", IEICE Technical Report, RCS 89-64 (1989). Reference 2: Koji Ohno, Hiroshi Koyama, Fumiyuki Adachi: "Initial state reset type clock recovery (IPR-CR)", 1989
IEICE Autumn National Convention B-54
3.

[0006]

In the conventional ACT demodulator, the carrier tracking cannot be performed in a state where the symbol clock synchronization is not established, so that the initial phase used for the preset cannot be extracted. In other words, since the output is detected by the free-running carrier, the phase difference between the transmission and reception carriers is superimposed, and the zero cross point of the demodulated signal input to the BTR does not match the change point of the transmission data. Therefore, there is a problem that the conventional high-speed pull-in BTR cannot be applied.

An object of the present invention is to provide means for enabling high-speed pull-in of an ACT demodulator.

[0008]

According to the present invention, a kind of baseband delay detector is constructed by using a measured phase value obtained by direct phase quantization used in ACT demodulation, and the output of this delay detector is used. The BTR is initially loaded.

FIG. 1 is a principle diagram of the ACT demodulator according to the present invention shown in claim 1 of the claims. In FIG. 1, reference numeral 1 denotes an ACT type synchronous detector that performs carrier tracking (hereinafter, referred to as ACT), 2 denotes a bit synchronization circuit (hereinafter, referred to as BTR) that performs clock recovery, and 3 denotes a baseband added according to the present invention. It is a differential detector.

The baseband delay detector 3 includes a direct phase quantization circuit 4 for quantizing with a clock n times the IF frequency of the demodulator input, a delay circuit 5 for delaying the phase value of the quantization result by one symbol time, It comprises a subtractor 6 for subtracting the phase value one symbol before and the current phase value, and a computing unit 7 for adding n / 8 to the output of the subtractor 6 or subtracting n / 8 from the subtraction result.

In QPSK transmission used for mobile communication, it is difficult to recover the absolute phase of a carrier on the receiving side, so that differential coding is usually performed on the transmitting side. Thereby, the transmission data corresponds to the phase transition of the modulated wave. Therefore, the relationship between the phase difference between the previous symbol and the current symbol (this phase difference is obtained by subtraction on the receiving side) and the transmission code is as shown in Table 1.

[0012]

[Table 1]

By performing an operation of ± n / 8 on the result of the subtraction, a shift of ± π / 4 occurs, and the correspondence is as shown in the right column of Table 1. Now, when n is selected as n = 2 ^k (k ≧ 2), the most significant bit of each of the calculation results of ± n / 8 becomes a reproduction code as it is, and the calculation result is the same as the in-phase / quadrature output of the differential detection. Has become. In the present invention, an initial phase preset is performed on the BTR 2 using the data change point of the operation result, thereby realizing high-speed pull-in of the ACT demodulator.

Next, FIG. 2 is a principle diagram of the ACT demodulator according to the present invention shown in claim 2 of the claims. In FIG. 2, 1 ACT and 3 baseband differential detectors are the same as those in FIG. 1, but 2a is a low inertia BTR having a small time constant and 2b is a high inertia BT having a large time constant.
R. The high inertia BTR2b is the BTR2 of FIG.
Corresponding to

BTR used in conventional ACT demodulation
Has a large time constant (high inertia BTR) in order to reduce clock jitter, and the pull-in time is long. In the initial phase preset method according to the first aspect of the present invention, it is considered that the filter time constant of the BTR is instantaneously set to zero, and the only effect of the transmission path with noise is to preset the correct phase with a certain probability. In other words, there is always a probability of presetting to the wrong phase, and if the preset fails, it takes a considerable amount of time to pull in the optimal phase using the high inertia BTR. This significantly degrades the rise characteristics of the demodulator. The second object of the present invention is to reduce this deterioration. The part of the baseband differential detector 3 is the same as that of the first aspect. The low inertia BTR 2 a is a simple BTR in which the frequency division ratio of the DPLL is reduced and the function of the filter is removed, and the clock jitter in a steady state is large, but high-speed pull-in is possible. At the start of the operation of the demodulator, first, the output of the baseband differential detector 3 is used to reduce the low inertia B
TR2a is pulled in. At this time, low inertia BTR
The initial phase preset method can also be used for 2a. When the low inertia BTR 2a is pulled in, the high inertia BTR 2b used for ACT demodulation is preset.

The above-described additional circuits for high-speed pull-in such as the baseband delay detector 3 and the low-inertia BTR 2a can stop the operation when the demodulator reaches a steady state. It does not increase current consumption.

[0017]

In the configuration shown in FIG. 1, by performing the delay detection operation in the baseband delay detector 3, correct symbol clock information can be extracted even using the measured phase value of the free-running carrier. In other words, it can be considered that the phase difference between the transmitting and receiving carriers hardly changes in about the symbol time, so that the component of this phase difference is removed by the subtraction operation. Therefore, the data change point of the delay detection calculation result is BT
It has a correct clock component regardless of the symbol synchronization of R2 and the state of carrier tracking of ACT1. Therefore, by performing initial pull-in of the BTR 2 using this edge, high-speed pull-in becomes possible. When symbol synchronization is established, the ACT demodulator completes carrier tracking in the next one symbol time, and a correct demodulation operation can be performed. Thereby, high-speed pull-in of the ACT demodulator can be realized.

In the configuration shown in FIG. 2, at the start of the demodulation operation, a low inertia BTR 2a is used to pull the phase to a certain level at a high speed. The high inertia BTR 2b is preset by the obtained phase. This two-stage preset enables high-speed pull-in without deteriorating the low clock jitter characteristics and stability required during the ACT demodulation operation. Further, it is also possible to reduce the drawback of the initial phase preset method, that is, the deterioration of the pull-in characteristic when the preset fails.

[0019]

FIG. 3 shows an embodiment of the baseband differential detector 3 in the principle diagram of FIG. This embodiment is an example of a case where direct phase quantization is performed using a clock 32 times the IF frequency.

In FIG. 3, reference numeral 8 denotes a frequency F _k = 32 × f
_A 5-bit phase measurement counter that counts with the master clock of _IF , 9 is a 5-bit D-FF that latches the counter value at the rising edge of the received signal,
10 a shift register for delaying one symbol time the output of the _{D-FF (f IF / f} S stages × 5 bits, f _S transmission symbol rate), 11 a preceding symbol phase value B from the current phase value A A 5-bit subtractor for subtraction, 12 is a subtraction result A
, Or subtracting 4 from the subtraction result A. The output of the circuit of this embodiment is sent to the BTR 2 shown in FIG. 1, and an initial phase preset is performed.

Next, FIG. 4 shows an embodiment of the low inertia BTR 2a in the principle diagram of FIG. The low inertia BTR of this embodiment is an example in which the frequency division ratio is 16. The frequency divider of the high inertia BTR used for demodulation is reset using the rising or falling edge of the reproduced clock of the low inertia BTR.

In FIG. 4, reference numeral 13 denotes a BTR input.
The received signal detection output of the baseband delay detector of FIG. 3 is input. Reference numeral 14 denotes a BTR master clock, which uses a clock 16 times the transmission symbol rate f _S. 1
Reference numeral 5 denotes an initial phase preset signal, which is set to "L" level to perform an initial phase preset operation when the ACT demodulator rises. 16 is a BTR switching signal,
Set to “H” level while operating as a low inertia BTR, and after starting the ACT demodulator, set a high inertia BT.
It is set to “L” level to function as R.

Reference numeral 17 denotes a preset signal, which is used as a signal for presetting the frequency divider in the next high inertia BTR. The circuit 18 is a rising edge detection circuit for the BTR input.
The TR input is read, and its rise is detected. 19
Is a circuit for dividing the BTR master clock by a half, and generates two complementary outputs which are inverted every clock. 2
Reference numeral 0 denotes a 1/2 frequency dividing circuit of the detection output of the rise detection circuit 18, which generates two complementary outputs that are inverted for each detection output. Reference numeral 21 denotes a phase comparator which compares the phases of the signals from the 1/2 frequency dividers 19 and 20 to detect a phase difference. Reference numeral 22 denotes a 1/8 frequency dividing counter, BT
Generating a f _S in synchronism with one cycle delay in the rise of the R input. Reference numeral 23 denotes an asynchronous reset signal generation circuit for the frequency dividing counter 22.
An asynchronous reset signal synchronized with the master clock is output, and the frequency division counter 22 is reset. Reference numeral 24 denotes a latch for forming a feedback loop of f _S , which outputs a signal for driving the frequency division counter 22 when the rising output signal of the BTR input exists when the carry output f _S of the frequency division counter 22 is at “H” level. Occurs. An OR gate 25 couples a phase difference detection signal from the phase comparator 21 and an output signal of the latch 24 to an input of the frequency division counter 22. 26 is a pulse width extending circuit, and 27 is a BTR switching control circuit.

[0024]

According to the present invention, the ACT demodulator can be pulled in at a high speed. Also, a low inertia BTR for establishing synchronization at high speed and a high inertia BTR for performing demodulation operation.
By using the BTR, it is possible to suppress the increase in the pull-in time and realize a BTR having a sufficiently low clock jitter characteristic even in a transmission line on which noise is superimposed.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention having a baseband differential detector.

FIG. 2 is a principle diagram of the present invention having a high inertia BTR and a low inertia BTR.

FIG. 3 is a configuration diagram of an embodiment of a baseband differential detector.

FIG. 4 is a configuration diagram of an embodiment of a low inertia BTR.

[Explanation of symbols]

 Reference Signs List 1 ACT synchronous detector (ACT) 2 Bit synchronous circuit (BTR) 3 Baseband delay detector 2a Low inertia BTR 2b High inertia BTR

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Eisuke Fukuda 1015 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Ken Takano 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited ( 72) Inventor Isao Shimizu Nippon Telegraph and Telephone Corporation, 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo (56) References JP-A-5-103030 (JP, A) JP-A-5-63748 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 27/00 H04L 7/00

Claims (2)

(57) [Claims] 1. A delay unit for delaying a phase measurement value obtained by direct phase quantization by one symbol time, a subtracter for subtracting a value before and after a delay, and adding a constant value to a subtraction result or a subtraction result A high-speed adaptive control demodulator, comprising: a delay detector constituted by an arithmetic unit for subtracting a constant value from the delay detector, and performing an initial pull-in by an output of the delay detector. 2. A delay unit for delaying a phase measurement value obtained by direct phase quantization by one symbol time, a subtracter for subtracting a value before and after a delay, and adding a constant value to a subtraction result or a subtraction result. A low-inertia bit synchronization circuit having a small time constant for performing an initial pull-in operation by an output of the delay detector, and a constant time required for the initial pull-in. A high-speed adaptive control demodulator comprising a high inertia bit synchronization circuit having a large time constant operating in synchronization with an output of a low inertia bit synchronization circuit, and performing a high-speed acquisition of the high inertia bit synchronization circuit.