JP3316755B2 - Test sequence generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (LS)
This relates to test sequence generation I).

[0002]

2. Description of the Related Art A scan design method is a typical example of a conventional design method for testability. The scan design method is to replace a flip-flop (FF) in a logic-designed integrated circuit with a scan FF that can be directly controlled (scan-in) and observed (scan-out) directly from the outside, and the scan FF is used as an external input / output. This makes it easier to generate test sequences by handling it (1990, Computer Science Press (Computer S
cience Press), “Digital Systems Tesingand
Testable DESIGN ”, Chapter 9 Design For Testability).

The scan design includes a full scan design in which all FFs in the circuit are replaced with scan FFs and a partial scan design in which some FFs in the circuit are replaced with scan FFs. For information on how to identify FFs to be scanned in partial scan design, see “An Exact Al
gorithm for Selecting Partial Scan Flipflop '' (1994
Year, DAC (design automation conference), pp81-pp86) and its references.

[0004] Also, regarding the generation of a test sequence of a sequential circuit, the compression of the test sequence is described in “Dynamic Test Compaction for
Synchronous Sequential Circuits using Static Comp
actiono Technique '' (1996, FTCS (Fault Tolerant Comp
uting Symposium), pp53-pp61) and their references.

[0005]

In a conventional partial scan design, a method of identifying an FF to be scanned is as follows.
Not necessarily sufficiently high fault detection efficiency (for example, 95% or more)
There is a problem that cannot be guaranteed.

Further, the conventional method of compressing a test sequence of a sequential circuit has a problem that the compression ratio is not always sufficiently high.

[0007] In view of the above problems, an object of the present invention is to provide a test sequence generation method capable of obtaining higher compression efficiency than in the past.

[0008]

Means for Solving the Problems In order to solve the above-mentioned problem, a solution taken by the invention of claim 1 is a test sequence generating method for generating a test sequence for a test after manufacturing an integrated circuit. A buffer length setting process for setting a length of a buffer for storing a test sequence, and the accumulation while sequentially compressing and storing the test sequence for each fault in a buffer having the buffer length set in the buffer length setting process. A test sequence compression process for generating a test sequence for the circuit, wherein the buffer length setting process determines whether or not a loop exists in the integrated circuit. Is set as the buffer length, while if not present, the order depth of the integrated circuit is set to 1
Is set as the buffer length.

According to a second aspect of the present invention, there is provided a test sequence generating method for generating a test sequence for a test after manufacturing an integrated circuit, wherein a length of a buffer for storing the test sequence is set. A buffer length setting process to be set and a test sequence compression process for generating a test sequence for the integrated circuit while sequentially compressing and storing the test sequence for each failure in a buffer having the buffer length set in the buffer length setting process. The buffer length setting process includes providing one buffer having the buffer length. The test sequence compression process includes a first process for generating a test sequence for one fault, and a first process for generating a test sequence. If the test sequence generated in step (1) can be compressed and stored in the already provided buffer, the test sequence is compressed and stored in the buffer. If not, a new buffer is stored. A second process of providing a new buffer and storing the new buffer in the new buffer. In the second process, when the number of buffers exceeds a predetermined number, the test sequence stored in the buffer having the smallest don't care number is used. A third process of performing a failure simulation and deleting the buffer; and repeatedly performing the first to third processes for each failure.

According to a third aspect of the present invention, there is provided a test sequence generating method for generating a test sequence for a test after manufacturing an integrated circuit, wherein a length of a buffer for storing the test sequence is set. A buffer length setting process to be set and a test sequence compression process for generating a test sequence for the integrated circuit while sequentially compressing and storing the test sequence for each failure in a buffer having the buffer length set in the buffer length setting process. The buffer length setting process includes providing a predetermined number of buffers having the buffer length, and the test sequence compression process includes a first process of generating a test sequence for one fault and a first process of generating a test sequence for one fault. A process of compressing and storing the generated test sequence over one of the predetermined number of buffers or between consecutive buffers is performed, and this compression storing process is not performed. In the second process for performing a failure simulation using the test sequence, and in the second process, when the non-don't care rate in the predetermined number of buffers exceeds a predetermined value, Performing a failure simulation using the test sequence stored in the buffer, and initializing all data in the predetermined number of buffers to "don't care".
To the third process are repeatedly performed for each failure.

[0011]

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a flowchart showing a flow of processing in a test sequence generation method according to a first embodiment of the present invention. The test sequence generation method according to the present embodiment is to generate a test sequence while sequentially compressing and storing test sequences generated for each fault in a given integrated circuit in a buffer.

In FIG. 1, SG1 is a step for determining whether or not a loop exists in the circuit. If a loop exists, the procedure proceeds to step SG2, and if no loop exists, the procedure proceeds to step SG3. In step SG2, a value specified in advance is set as a buffer length,
One buffer of this buffer length is provided, and all data is initialized to don't care. In step SG3, a value obtained by adding 1 to the order depth of the circuit is set as the buffer length, one buffer having this buffer length is provided, and all the data is initialized to don't care.

After setting the buffer length in steps SG2 and SG3, the maximum number of buffers is specified in step SG4.

SG5 is a step of determining whether or not a test sequence has been generated for all undetected faults in the circuit. If a test sequence has been generated for all undetected faults, the process proceeds to step SG6. If there is an undetected fault for which a test sequence has not been generated yet, the process proceeds to step SG7. In step SG6, a failure simulation is executed using all the test sequences stored in the buffer group.

SG7 is a step of selecting one fault as a target fault from undetected faults for which a test sequence has not yet been generated, and SG8 is a step of generating a test sequence for the target fault selected in step SG7.

SG9 is a step for determining whether or not the length of the test sequence generated in step SG8 is longer than the buffer length set in step SG2 or SG3. If it is long, proceed to step SG10; otherwise, proceed to step SG11. If there is no loop in the circuit, the buffer length is set to (order depth + 1) in step SG3, so that the length of the test sequence does not become longer than the buffer length. In step SG10, a failure simulation is performed on the generated test sequence. Step SG1
In step 1, the generated test sequence is compressed and stored in a buffer. Details of step SG11 will be described later.

SG12 is a step for determining whether or not the number of buffers has exceeded the maximum number of buffers specified in step SG4 as a result of the compression and storage in step SG11.
If the number of buffers is larger than the maximum number of buffers, the process proceeds to step SG13; otherwise, the process proceeds to step SG13.
Go back to G5. In step SG13, a failure simulation is performed using the test sequence stored in the buffer having the smallest number of don't cares, and this buffer is deleted.

FIG. 2 is a flowchart showing details of the processing of step SG11 in the test sequence generation method according to the present embodiment shown in FIG. In FIG. 2, SG11a
Is a step of determining whether or not compression storage has been attempted for all buffers for the test sequence generated in step SG8. If all buffers have been tried to be compressed and stored, the process proceeds to step SG11g. If there is a buffer that has not yet been compressed and stored, the process proceeds to step SG11b.

SG11b is a step of selecting one buffer that has not yet tried compression storage. SG11c
Is a step of judging whether or not compression storage has been tried for all the start positions in the buffer selected in step SG11b. When compression storage has been tried for all start positions, the process returns to step SG11a, and when there is a start position for which compression storage has not yet been tried, the process proceeds to step SG11d. In step SG11d, a start position at which compression storage is attempted is selected. For one buffer, (buffer length−test sequence length + 1) start positions can be selected.

SG11e is a step for determining whether or not the test sequence generated in step SG8 is to be compressed and stored in the buffer selected in step SG11b from the start position selected in step SG11d. In this step SG11e, the logical value “0” of the test sequence is
The logical value “0” or don't care in the buffer can be compressed, but the logical value “1” cannot be compressed. The logical value “1” of the test sequence can be compressed as the logical value “1” in the buffer or don't care. It is determined whether or not the test sequence can be compressed and stored based on a compression rule that it is possible but cannot be compressed with the logical value “0”.

When it is determined in step SG11e that the test sequence can be compressed and stored, the test sequence is compressed and stored in the buffer based on the compression rule in step SG11f.

SG11g is a process for adding a new buffer and storing the test sequence in the new buffer when the test sequence could not be compressed and stored in any buffer. SG11h is a process of sorting the buffers in descending order of the number of don't cares.

The test sequence generation method according to the present embodiment shown in FIGS. 1 and 2 will be described with reference to FIGS. Here, there is no loop in the target circuit, and the order depth of the circuit is 2. It is also assumed that the target circuit has faults a, b, c, and d as undetected faults. 3 to 6 , X1 to X3 are external inputs, A and B are buffers, 0 of data in the buffers is a logical value "0", 1 is a logical value "1", and X is don't care. .

In step SG1, since no loop exists in the target circuit, the process proceeds to step SG3.
3 which is a value obtained by adding 1 to the order depth is set as the buffer length. Then, as shown in FIG. 3A, a buffer A having a buffer length of 3 is generated, and all the data is initialized to don't care. At step SG4, 2 is designated as the maximum number of buffers.

Next, a test sequence is generated in step SG8 for the fault a selected in step SG7,
In step SG11, the test sequence of the fault a is compressed and stored in the buffer A. In this case, the buffer length and the fault a
Since the length of the test sequence is the same, only 0 is possible as the start position, and all the data in the buffer A is initialized to "don't care", so that the data can be compressed based on the compression rule already described. As a result, FIG.
As shown in (b), the test sequence of the fault a is compressed and stored in the buffer A.

Next, for a fault b selected in step SG7, a test sequence is generated in step SG8.
As shown in FIG. 4A, the test sequence of the failure b is compressed and stored in the buffer A. In this case, the buffer length and the failure b
Since the length of the test sequence is equal, only 0 is possible as the start position. As a result of trying compression storage based on the compression rule already described, compression is impossible.
As shown in (b), a new buffer B is added to store the test sequence of the fault b. Since the don't care number of the buffer A is 4 and the don't care number of the buffer B is 5, the buffers are sorted in the order of the buffers B and A.

Next, for a fault c selected in step SG7, a test sequence is generated in step SG8.
As shown in FIG. 5A, the test sequence of the fault c is compressed and stored in the buffers A and B. In this case, since the length of the test sequence of the fault c is 2, the possible starting position is 0.
And 1 only. As a result of attempting compression storage based on the compression rule described above, buffer B was not able to be stored when the start position was 0 or 1. Buffer A could not be stored when the start position was 0, but could be stored when the start position was 1. From this result, as shown in FIG. 5B, the test sequence of the fault c is compressed and stored in the buffer A with the start position set to 1. Since the number of don't cares in buffer A is 1 and the number of don't cares in buffer B is 5, buffers B and A are sorted in this order.

Next, for a fault d selected in step SG7, a test sequence is generated in step SG8.
As shown in FIG. 6, the test sequence of this failure d is compressed and stored in buffers A and B. In this case, the buffer length and the failure d
Since the length of the test sequence is equal, only 0 is possible as the start position. As a result of the trial of the compression storage based on the compression rule described above, it is impossible to store the data in both the buffer B and the buffer A. In the buffer C. Since the number of don't cares in buffer A is 1, the number of don't cares in buffer B is 5, and the number of don't cares in buffer C is 3, the buffers are sorted in the order of buffers B, C, and A.

Since the number of buffers has exceeded the maximum number of buffers 2 (step SG12), of the buffers A, B and C,
A fault simulation is executed by randomly entering a logical value “0” or “1” in the test sequence stored in the buffer A with the smallest number of don't cares, instead of the don't cares. Then, the buffer A is deleted, and the buffer C storing the test sequence of the failure d is set as the buffer A (step S
G13).

Since there are no undetected faults that have not generated a test sequence (step SG5), the buffer A,
A logical value “0” or “1” is randomly entered in the test sequence stored in B instead of the don't care, and a fault simulation is executed (step SG6).

As described above, in test sequence generation, compression is dynamically performed using a buffer, so that a short test sequence can be generated.

(Second Embodiment) FIG. 7 is a flowchart showing a flow of processing in a test sequence generation method according to a second embodiment of the present invention. The test sequence generation method according to the present embodiment generates a test sequence while sequentially compressing and storing test sequences generated for each fault in a given circuit in a buffer. However, the algorithm for compressing and storing in the buffer is different from that of the first embodiment.

In FIG. 7, SH1 is a step for determining whether or not a loop exists in the circuit. If a loop exists, the process proceeds to step SH2, and if no loop exists, the process proceeds to step SH3. In step SH2, a value L specified in advance is set as a buffer length, and N buffers (N is a positive integer) having a buffer length L are provided, and all data is initialized to don't care. In step SH3, a value obtained by adding 1 to the order depth of the circuit is set as the buffer length, and N buffers of this buffer length are provided to initialize all data to don't care.

In step SH4, it is determined whether or not the ratio of non-don't care data among the data in the N buffers, that is, the non-don't care rate , exceeds an upper limit value P specified in advance. When the non-don't care rate exceeds the upper limit value P, the process proceeds to step SH5, in which a logical value "0" or "1" is inserted in place of the don't care of the buffer data, and a failure simulation is performed. Update data to don't care. Non
If the don't care rate does not exceed the upper limit P, the process proceeds to step SH7.

At step SH7, it is determined whether or not a test sequence has been generated for all faults. If a test sequence has been generated for all faults, the process proceeds to step SH8, where a logical value " The fault simulation is executed by inserting “0” or “1”.

SH9 is a step of selecting one fault as a target fault from undetected faults for which a test sequence has not yet been generated, and SH10 is a step of generating a test sequence for the target fault selected in step SH9.

In step SH11, the length of the test sequence generated in step SH10 is set to step SH2 or step SH3.
Is a step of determining whether or not the length of the test sequence is longer than the buffer length. If the length of the test sequence is longer than the buffer length, the process proceeds to step SH12; otherwise, the process proceeds to step SH13. If there is no loop in the circuit, the buffer length is (order depth +
Since it is set to 1), the length of the test sequence does not become longer than the buffer length. In step SH12, a failure simulation is performed using the generated test sequence. In step SH13, the generated test sequence is compressed and stored in N buffers. Details of step SH13 will be described later. It is determined in step SH14 whether or not compression storage was possible. If compression and storage were successful, the process returns to step SH4. If compression and storage was not possible, a failure simulation was performed in this test sequence in step SH12.
Return to H4.

FIG. 8 is a flowchart showing the details of the processing in step SH13 in the test sequence generation method according to the present embodiment shown in FIG. In FIG. 8, SH 13a is a step of initializing start position i to 0, SH 13b to SH 13b.
H13e is a step of determining whether or not the test sequence can be compressed and stored in the N buffers while incrementing the start position i, compressing and storing the data if possible, and terminating the processing otherwise.

The test sequence generation method according to the present embodiment shown in FIGS. 7 and 8 will be described with reference to FIGS. Here, there is no loop in the target circuit, and the order depth of the circuit is 2. Further, the number N of buffers is 2, and the upper limit value P of the non-don't care rate is 60.
%. It is also assumed that the target circuit has faults a, b, c, and d as undetected faults. 9 to 12 , X1 to X3 indicate external inputs, 0 in the data in the buffer indicates a logical value "0", 1 indicates a logical value "1", and X indicates don't care. The processing is performed by regarding the N buffers as one buffer.

In step SH1, since there is no loop in the target circuit, the process proceeds to step SH3.
3 which is a value obtained by adding 1 to the order depth is set as the buffer length. Then, as shown in FIG. 9A, two buffers having a buffer length of 3 are generated, and
And all data is initialized to don't care.

[0042] Non-don't-care index in step SH4 that determines whether or not exceeded the upper limit value P, where the non Dontoke
Since the rate is 0%, the process proceeds to step SH7.

Next, for a fault a selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault a is compressed and stored in a buffer. As shown in FIG. 9A, the data can be stored when the start position is 0, so that the data is stored as shown in FIG. 9B. The non-don't care rate is 5/18, less than 60%.

Next, for the fault b selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault b is compressed and stored in a buffer. As shown in FIG.
When the start position is 1, the data can be compressed and stored.
Store as shown in. Non-don't care rate is 6 at 8/18
Less than 0%.

Next, for the fault c selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault c is compressed and stored in a buffer. As shown in FIG.
Since the compressed storage is possible when the start position is 4, FIG.
Store as shown in. The non-don't care rate is 12/18, which is greater than 60%. Therefore, a failure simulation is performed in step SH5, and all the buffer data is updated to "don't care" in step SH6.

Next, for a fault d selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault d is compressed and stored in a buffer. As shown in FIG.
When the start position is 0, the data can be compressed and stored.
The test sequence of the fault d is stored as shown in FIG. Non-dontone
The a ratio is 6/18, which is smaller than 60%.

As described above, according to the present embodiment, whether or not further compression storage is possible is determined based on the non-don't care rate of the buffer, so that dynamic compression of the test sequence can be efficiently realized. In addition, by regarding a plurality of buffers as one buffer, it becomes possible to compress and store a test sequence across a plurality of buffers.
The compression ratio can be further increased.

[0048]

As described above, according to the test sequence generation method of the present invention, a test sequence is generated for a given integrated circuit while sequentially compressing and storing the test sequence generated for each fault in a buffer. Therefore, the compression ratio of the test sequence can be made sufficiently high.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing flow in a test sequence generation method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing details of a process of step SG11 in FIG. 1;

FIGS. 3A and 3B are diagrams for explaining a test sequence generation method according to the first embodiment of the present invention.

FIGS. 4A and 4B are diagrams for explaining a test sequence generation method according to the first embodiment of the present invention.

FIGS. 5A and 5B are diagrams illustrating a test sequence generation method according to the first embodiment of the present invention.

FIG. 6 is a diagram for explaining a test sequence generation method according to the first embodiment of the present invention.

FIG. 7 is a flowchart showing a flow of processing in a test sequence generation method according to a second embodiment of the present invention.

FIG. 8 is a flowchart showing details of the processing in step SH13 of FIG. 7;

FIGS. 9A and 9B are diagrams for explaining a test sequence generation method according to the second embodiment of the present invention.

FIGS. 10A and 10B are diagrams illustrating a test sequence generation method according to a second embodiment of the present invention.

FIGS. 11A and 11B are diagrams illustrating a test sequence generation method according to a second embodiment of the present invention.

FIGS. 12A and 12B are diagrams for explaining a test sequence generation method according to a second embodiment of the present invention.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/3183 G06F 17/50

Claims (3)

(57) [Claims] An inspection system for inspecting an integrated circuit after manufacturing.
A test sequence generation method for generating a sequence, comprising: a buffer for setting a length of a buffer for storing a test sequence.
In the buffer length setting process, the buffer length setting process and the inspection sequence for each failure are performed.
Compressed and stored in the buffer with the buffer length set in
A test for generating a test sequence for the integrated circuit
And a sequence compression process, wherein the buffer length setting process determines whether or not a loop exists in the integrated circuit, and when it is determined that a loop exists, sets a predetermined value as a buffer length, If not, a value obtained by adding 1 to the order depth of the integrated circuit is set as a buffer length. 2. An inspection system for inspection after manufacturing an integrated circuit.
A test sequence generation method for generating a sequence, comprising: a buffer for setting a length of a buffer for storing a test sequence.
In the buffer length setting process, the buffer length setting process and the inspection sequence for each failure are performed.
Compressed and stored in the buffer with the buffer length set in
A test for generating a test sequence for the integrated circuit
A sequence compression process, wherein the buffer length setting process includes providing one buffer having the buffer length. The test sequence compression process includes: a first process of generating a test sequence for one failure; When the test sequence generated in the first process can be compressed and stored in the buffer already provided, the test sequence is compressed and stored in the buffer. Otherwise, a new buffer is provided and the new buffer is provided. In the second processing for storing, and in the second processing, when the number of buffers exceeds a predetermined number, a failure simulation is performed using the test sequence stored in the buffer with the smallest number of don't cares, and this buffer is A third process for deleting, wherein the first to third processes are repeatedly performed for each fault. Method. 3. An inspection system for inspection after manufacturing an integrated circuit.
A test sequence generation method for generating a sequence, comprising: a buffer for setting a length of a buffer for storing a test sequence.
In the buffer length setting process, the buffer length setting process and the inspection sequence for each failure are performed.
Compressed and stored in the buffer with the buffer length set in
A test for generating a test sequence for the integrated circuit
A sequence compression process, wherein the buffer length setting process is to provide a predetermined number of buffers having the buffer length, the test sequence compression process is a first process of generating a test sequence for one fault, A process for compressing and storing the test sequence generated in the first process over one of the predetermined number of buffers or between consecutive buffers is performed. A second process of performing a failure simulation using a sequence, and in the second process, when a non-don't care rate in the predetermined number of buffers exceeds a predetermined value, a test sequence stored in the predetermined number of buffers. And a third process of performing a failure simulation by using the first and third data, and initializing all data in the predetermined number of buffers to don't care. Test sequence generation method characterized by processing, is performed repeatedly for each fault.