JP3267928B2 - Testability design method and semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an integrated circuit (LS)
It relates to the design for ease of inspection of I).

[0002]

2. Description of the Related Art A scan design method is a typical example of a conventional design method for testability. The scan design method is to replace a flip-flop (FF) in a logic-designed integrated circuit with a scan FF that can be directly controlled (scan-in) and observed (scan-out) directly from the outside, and the scan FF is used as an external input / output. This makes it easier to generate test sequences by handling it (1990, Computer Science Press (Computer S
cience Press), “Digital Systems Tesingand
Testable DESIGN ”, Chapter 9 Design For Testability).

The scan design includes a full scan design in which all FFs in the circuit are replaced with scan FFs and a partial scan design in which some FFs in the circuit are replaced with scan FFs. For information on how to identify FFs to be scanned in partial scan design, see “An Exact Al
gorithm for Selecting Partial Scan Flipflop '' (1994
Year, DAC (design automation conference), pp81-pp86) and its references.

[0004] Also, regarding the generation of a test sequence of a sequential circuit, the compression of the test sequence is described in “Dynamic Test Compaction for
Synchronous Sequential Circuits using Static Comp
actiono Technique '' (1996, FTCS (Fault Tolerant Comp
uting Symposium), pp53-pp61) and their references.

[0005]

In a conventional partial scan design, a method of identifying an FF to be scanned is as follows.
Not necessarily sufficiently high fault detection efficiency (for example, 95% or more)
There is a problem that cannot be guaranteed.

Further, the conventional method of compressing a test sequence of a sequential circuit has a problem that the compression ratio is not always sufficiently high.

[0007] In view of the above problems, it is an object of the present invention to provide a design method for facilitating inspection that can guarantee high fault detection efficiency when identifying an FF to be scanned .

[0008]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is to provide an integrated circuit designed at a gate level so that inspection after manufacturing becomes easy. As a testability design method for making a design change, among the flip-flops of the integrated circuit, the integrated circuit has an n-fold alignment structure (where n is an integer, and the fault detection efficiency and scan performance).
As will be determined) based on the emission rate, which determines the flip-flop to be scanned of a full scan processing for provisionally determining all of the flip-flops of the integrated circuit, as for scanning of, For each flip-flop tentatively determined to be scanned in the full scan processing, it is determined whether or not the integrated circuit has an n-fold alignment structure when it is assumed that the flip-flop is not scanned, and n In the case of a double-aligned structure, the flip-flop is temporarily determined not to be scanned. On the other hand, in the case of an n-fold aligned structure, the flip-flop is not scanned. Performing the full scan process and the non-scanning selection process. Of a provisional decision flip-flops as the one in which is determined as a flip-flop to be scanned of.

According to a second aspect of the present invention, the non-scanning selection process in the testability designing method of the first aspect recognizes a flip-flop having a self-loop structure among the flip-flops of the integrated circuit. For flip-flops recognized as having a loop structure, the process of determining whether or not the logic circuit has an n-fold alignment structure assuming that the flip-flop is not to be scanned is omitted, and provisional determination is to be performed for scanning. Shall be maintained.

According to the third aspect of the present invention, the first aspect is provided.
The design method for facilitating the inspection of the integrated circuit according to claim 1, further comprising: determining a reachable external output and a pseudo external output with respect to the flip-flop of the integrated circuit; and a flip-flop belonging to a path from the flip-flop to the reachable external output and the pseudo external output. Is determined as a reachable flip-flop, and the non-scanning selection processing determines whether or not the integrated circuit has an n-fold alignment structure on the assumption that one flip-flop is not scanned. In doing so, the reachable external output and pseudo external output obtained in the preprocessing for the one flip-flop, and
Time frame expansion is performed on a pseudo external output which is a data input of one of the reachable flip-flops obtained by the pre-processing for the one flip-flop which is temporarily determined to be scanned.

Further, in the invention of claim 4, according to the first aspect,
The design method for testability of the present invention is characterized in that, for the integrated circuit, a flip-flop, an external input, and an external output represent a connection relationship that can be reached only through a combinational circuit with each other.
It is assumed that a preprocessing for creating a relation graph is provided, and a flip-flop to be scanned is determined based on the FF relation graph created in the preprocessing.

[0012] Further, according to a fifth aspect of the present invention, there is provided an integrated circuit designed by RTL, wherein the integrated circuit is designed as an inspection facilitating design method for making a design change so that inspection after manufacturing is facilitated. All registers of the circuit are tentatively determined to be scanned, and full-scan processing is performed.For each register tentatively determined to be scanned in the full-scan processing, the registers are assumed not to be scanned. The integrated circuit has an n-fold alignment structure (where n is an integer and is based on the fault detection efficiency and scan rate).
It is determined whether or not the register is n-ordered, and if the register is not n-ordered, the register is provisionally determined not to be scanned. A non-scanning selection process that maintains a tentative decision that the scan is to be performed, as a result of executing the full scan process and the non-scanning selection process,
A register provisionally determined to be scanned is determined as a register to be scanned.

According to a sixth aspect of the present invention, an integrated circuit designed at a gate level and composed of a plurality of blocks is designed to have a design change so as to facilitate inspection after manufacturing. As a testability design method to be performed, in each block of the integrated circuit, an output unit FF that is an FF that can be reached from the block output to the input side only through the combinational circuit, or only the combinational circuit from the block input to the output side is used. A first process of determining an input unit FF that is an FF that can be reached through the process as an FF to be scanned, and in each of the blocks, the block has an n-fold alignment structure (n is
Integer, determined based on fault detection efficiency and scan rate.
2) to determine flip-flops to be scanned.

According to a seventh aspect of the present invention, there is provided an integrated circuit designed at a gate level, which is designed as a test simplification design method for making a design change so that a test after manufacturing is facilitated. Without recognizing the / flip-flop as a flip-flop having a self-loop structure, the integrated circuit has an n-fold alignment structure (where n is an integer and
(Determined on the basis of the fault detection efficiency and the scan ratio) to determine the flip-flop to be scanned from the flip-flops constituting the integrated circuit.
Of the integrated circuit for which the flip-flop to be scanned has been determined in the first test facilitation processing, so that the inspection of the load / hold type flip-flop is facilitated. And a second inspection facilitation process for determining

According to the invention of claim 8, in the second test simplification process in the test simplification design method of the seventh invention, the flip-flop to be scanned in the first test simplification process is determined. For the integrated circuit, a time frame is developed based on the justification of the state of the load / hold type flip-flop, and the flip-flop to be scanned is determined from the time frame development.

According to the ninth aspect of the present invention, the seventh aspect is provided.
The second test facilitating process in the test facilitating design method of the first aspect includes loading / unloading the integrated circuit for which the flip-flop to be scanned has been determined in the first test facilitating process, which is not determined to be scanned. A flip-flop that can be reached from a load / hold selection input of a hold-type flip-flop through only a combinational circuit,
It shall be determined as a scan.

Further, in the invention of claim 10, the testability design method of claim 9 is characterized in that, in the load / hold type flip-flop of the integrated circuit, A process for obtaining a load mode ratio indicating a ratio of the status justified; if the load mode ratio exceeds a predetermined value, the second
Of the flip-flop to be scanned in the inspection simplification processing of the above is used.
It is assumed that the determination result of the flip-flop to be scanned in the inspection facilitation process is not used.

Further, in the invention of claim 11, in the testability design method according to claim 10, when the load mode ratio does not exceed a predetermined value, scanning is performed in the first testability processing. For the integrated circuit for which the flip-flop has been determined, time frame expansion is performed based on the state justification of the load / hold type flip-flop,
From this time frame development, a third inspection facilitation process for determining a flip-flop to be scanned is to be executed.

In the twelfth aspect of the present invention, in the testability designing method of the seventh aspect, a state can be justified without assigning a value to its own output among flip-flops having a self-loop structure. Something is extended Pure Road /
A preprocessing for recognizing the flip-flop as a hold flip-flop, wherein the first and second inspection facilitation processes respectively include a flip-flop recognized as an extended pure load / hold flip-flop in the preprocessing;
It is assumed that the flip-flop to be scanned is determined by regarding it as a load / hold type flip-flop.

According to a thirteenth aspect of the present invention, a design change is performed on an integrated circuit which is designed at a gate level and includes a plurality of blocks so that inspection after manufacturing is facilitated. As a testability design method to be performed, in each block of the integrated circuit, an output unit FF that is an FF that can be reached from the block output to the input side only through the combinational circuit, or only the combinational circuit from the block input to the output side is used. A first process of determining an input unit FF that is an FF that can be reached through as a FF to be scanned, and in each of the blocks, without recognizing a load / hold type flip-flop as a flip-flop having a self-loop structure , The block has an n-fold alignment structure (n is an integer,
The second process of determining flip-flops to be scanned and the respective flip-flops to be scanned in the second process are determined so as to be determined based on the failure detection efficiency and the scan ratio. And a third process of deciding a flip-flop to be scanned so that the load / hold type flip-flop can be easily inspected for the block.

According to a fourteenth aspect of the present invention, there is provided a design for facilitating the inspection of an integrated circuit designed at a gate level, which determines a flip-flop to be scanned so as to facilitate an inspection after manufacturing. As a method, when the data input of the flip-flop to be scanned is regarded as a pseudo external output and the data output is regarded as a pseudo external input, a gate is provided in each path from the external input or pseudo external input to the external output or pseudo external output. The flip-flop to be scanned is determined so that the number of stages is n or less (n is 0 or a natural number).

According to another aspect of the present invention, there is provided an easy-to-test design for determining a flip-flop to be scanned so that an integrated circuit designed at a gate level can be easily tested after manufacturing. As a method, the structure of the logic circuit is an n-fold aligned structure (where n is an integer and
Rate and scan rate) .
A first process for determining a flip-flop to be scanned, and regarding the logic circuit, a data input of the flip-flop to be scanned determined in the first process is regarded as a pseudo external output, and a data output is regarded as a pseudo external input. Assuming, time frame expansion of each external output and pseudo external output is performed, and the number of test sequence generation influence flip-flops which is the number of flip-flops in this expanded time frame, or the number of test sequence generation influence gates which is the number of gates A second process for determining the number.
, A plurality of values including at least 1 are set, the first and second processes are respectively performed for each set value of the n, and the number of test sequence generation influence flips or the test sequence determined by the second process is set. The value of n is determined based on the number of generation influence gates.

[0023]

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a flowchart showing a flow of processing in a testability design method according to a first embodiment of the present invention. In FIG. 1, SA1 is a step as a full scan process in which all flip-flops (FFs) of the target integrated circuit are temporarily determined to be scanned, and SA2 to SA2.
In step SA8, for each flip-flop temporarily determined to be scanned in step SA1, when it is assumed that the flip-flop is not scanned, it is determined whether or not the integrated circuit has an n-fold alignment structure (SA).
7) In the case of an n-fold alignment structure, this is a step as non-scanning flip-flop selection processing in which the flip-flop is temporarily determined not to be scanned. In step SA9, steps SA1 to SA8
Is executed, the flip-flop temporarily determined to be scanned is determined as the flip-flop to be scanned.

The n-fold alignment structure means that in an arbitrary pair of FF and external output in a circuit, a path between the paired FF and external output has n or less order depths. ,
Circuit structure. Here, n is an integer not less than 1 and not more than the order depth of the circuit. A circuit having an n-fold alignment structure has a feature that when a time frame is expanded for a certain external output, at most n identical FFs exist. For example, when n = 1, that is, the single alignment structure has a feature that when a time frame is expanded for a certain external output, there is only one identical FF. In the present embodiment, the FF to be scanned is determined so that the integrated circuit has an n-fold alignment structure. At this time, the input of the FF to be scanned is regarded as a pseudo external output, and the output of the FF to be scanned is regarded as a pseudo external input.

SA2 is an FF having a self-loop structure.
When the FF selected in step SA4 is recognized as having a self-loop structure in step SA2, the process returns to step SA3 (SA5). That is, for the FFs recognized as having the self-loop structure, the execution of step SA7 is omitted while the FFs are provisionally determined to be scanned.

The design method for testability according to the present embodiment shown in FIG. 1 will be described with reference to FIGS. Here, it is assumed that n in the n-fold alignment structure is 1, and it is determined in step SA7 whether the circuit has a single-alignment structure.

FIG. 2 is a diagram showing an integrated circuit (sequential circuit) to be subjected to the testability designing method according to the present embodiment.
In FIG. 2, A to E are combinational circuits, and r1 to r4 are F
F, PI1, and PI2 are external inputs, and PO1 and PO2 are external outputs. Arrows indicate the connection relationships between the components. It is assumed that all the clocks of the FFs r1 to r4 are connected to the same clock input, and the description thereof is omitted in FIG.

It should be noted that the FF temporarily determined to be scanned is
, The data input is regarded as a pseudo external output, and the output is regarded as a pseudo external input. The pseudo external output is represented as PPOi (i is a character corresponding to the sign of the FF), and the pseudo external input is represented as PPIi (i is a character corresponding to the sign of the FF). For example, when FFr1 is provisionally determined to be scanned, the data input is regarded as a pseudo external output PPO1, and the output is regarded as a pseudo external input PPI1.

First, in step SA1, it is provisionally determined that all FFs r1 to r4 in the sequential circuit shown in FIG. 2 are to be scanned. Next, in step SA2, the circuit structure of the sequential circuit shown in FIG. 2 is analyzed, and it is recognized that only FFr3 has a self-loop structure.

Hereinafter, steps SA4 to SA8 are executed for each of the FFs r1 to r4.

First, at step SA4, FFr1 is selected. Since FFr1 does not have a self-loop structure,
At step SA6, it is tentatively determined that non-scanning is performed, and at step SA7, it is determined whether or not the circuit has a single alignment structure.

FIG. 3 is a diagram showing time frame development when FFr1 is non-scanned. First step SA
Step SA for the external output PO1 selected in Step 7b
At 7c, time frame development is performed (FIG. 3A). Since there is no FF in the developed time frame, the process returns from step SA7d to step SA7a, and then selects the external output PO2 to perform time frame development (FIG. 3).
(B)). Since there is no FF in the developed time frame, the flow returns to step SA7a again, and then the pseudo external output PPO2 (data input of the FFr2 provisionally determined to be scanned) is subjected to time frame development (FIG. 3 ( c)). FFr1 is 1 in the expanded time frame
Since there is only one, the process returns to step SA7a again,
Next, the pseudo external output PPO3 (data input of the FFr3 provisionally determined to be scanned) is selected and time frame development is performed (FIG. 3D). Since there is only one FFr1 in the developed time frame, step S
Returning to A7a, next, the pseudo external output PPO4 (data input of the FFr4 temporarily determined to be scanned) is selected and time frame development is performed (FIG. 3E). Since no FF exists in the developed time frame, the flow returns to step SA7a again. Since time frame development has been completed for all external outputs and pseudo external outputs, the process returns to step SA3, and the next FF is selected in step SA4.

Next, in step SA4, FFr2 is selected. Since FFr2 does not have a self-loop structure,
At step SA6, it is tentatively determined that non-scanning is performed, and at step SA7, it is determined whether or not the circuit has a single alignment structure.

FIG. 4 is a diagram showing a time frame development when FFr2 is not scanned. First step SA
Step SA for the external output PO1 selected in Step 7b
At 7c, time frame development is performed (FIG. 4A). Since only one FFr1 and one FFr2 exist in the expanded time frame, step SA7d
Then, the process returns to step SA7a, where the external output PO2 is selected and time frame development is performed (FIG. 4B). Since there is no FF in the developed time frame, the flow returns to step SA7a again, and then the pseudo external output PPO3 is selected to perform the time frame development (FIG. 4C). Since there is only one FFr1 in the developed time frame, the process returns to step SA7a again, and then selects the pseudo external output PPO4 to perform time frame development (FIG. 4).
(D)). Since only one FFr1 and one FFr2 exist in the expanded time frame, the flow returns to step SA7a again. Since time frame expansion has been completed for all external outputs and pseudo external outputs,
Returning to step SA3, the next FF is selected in step SA4.

Next, in step SA4, FFr3 is selected. However, since FFr3 is recognized as having a self-loop structure in step SA2, execution of step SA7 is omitted and steps SA5 to S5 are performed.
Returning to A3, the next FF is selected in step SA4.

Next, in step SA4, FFr4 is selected. Since FFr4 does not have a self-loop structure,
At step SA6, it is tentatively determined that non-scanning is performed, and at step SA7, it is determined whether or not the circuit has a single alignment structure.

FIG. 5 is a diagram showing time frame development when FFr4 is non-scanned. Step SA7b
Step SA7c for the external output PO1 selected in step
Perform time frame development with. Since two FFr1s and two FFr2s exist in the expanded time frame, the circuit is not of a single alignment structure. Therefore, the process proceeds from step SA7d to step SA8, and FFr4 is provisionally determined to be scanned.

Since the processing of steps SA4 to SA8 has been completed for all the FFs r1 to r4, the FFs r3 and r4, which have been temporarily determined to be scanned, are determined as FFs to be scanned (SA9), and the processing is terminated. .

FIG. 6 is a diagram showing the result of executing the testability design method according to the present embodiment on the integrated circuit of FIG. In FIG. 6, FFs r3 and r4 determined to be scanned are replaced with scan FFs. SI is a scan-in external input, SO is a scan-out external output, SE is a scan enable external input, and a scan FFr4
Via the scan input DT and output Q of the scan FFr3 and the scan input DT and output Q of the scan FFr3 to the scan-out external output SO.

As described above, according to the design method for testability according to the present embodiment, the FF to be scanned is determined so that the integrated circuit has the n-fold alignment structure.
, A high fault detection efficiency can be guaranteed.

The algorithm described in the present embodiment can be easily applied to a testability design method for an integrated circuit designed by RTL. That is,
Full scan processing in which all registers of the integrated circuit designed by RTL are provisionally determined to be scanned,
For each register provisionally determined to be scanned in the full scan processing, it is determined whether or not the integrated circuit has an n-fold alignment structure by assuming that the register is not to be scanned. In the case of a column structure, a non-scanning selection process of tentatively determining that the register is not to be scanned may be executed, and the register temporarily determined to be scanned may be determined as a register to be scanned.

Second Embodiment FIG. 7 shows a load / hold type FF (hereinafter referred to as “L / H type F”).
F "). As shown in FIG. 7A, the L / H FF switches between a load mode and a hold mode according to a load / hold signal input to a load / hold selection input LH. In the load mode, data is loaded from the D input, while in the hold mode, the currently held data is held as it is. By using the L / H FF, the number of clock signal lines can be reduced and the power consumption of the circuit can be reduced. The L / H type FF can be described by a combination of a selector and a DFF as shown in FIG. The selector uses the load / hold signal as a selection signal, selects and outputs one of the external input and the output of the DFF,
Takes the selection output of the selector as input. That is, L / H
The type FF has a self-loop structure.

The design method for facilitating inspection according to this embodiment is as follows.
L / H type FF having a self-loop structure as shown in FIG.
Is recognized as having no self-loop structure, and a partial scan is performed based on the “state justification”.

FIG. 8 is a flowchart showing the flow of processing in the testability design method according to the second embodiment of the present invention. In FIG. 8, SB1 is a step of determining an FF to be scanned so that a circuit to be designed for testability has an n-fold alignment structure. This step SB1
Is the same process as the testability design method according to the first embodiment, except that the L / H FF is recognized as not having a self-loop structure, and then the F / F to be scanned is used.
The difference from the first embodiment is that F is determined.

SB2 to SB4 are steps for performing a partial scan based on the justification of the state of the L / H FF. In step SB3, one of the unprocessed external output or pseudo external output is selected, and in step SB4, the time frame expansion of the external output or pseudo external output selected in step SB3 is performed based on the L / H type FF state justification. To determine an FF to be scanned. When steps SB3 and SB4 have been executed for all the external outputs and the pseudo external outputs, the design for testability according to the present embodiment ends (SB2).

FIG. 9 is a flowchart showing details of step SB4 of the design method for testability according to the present embodiment shown in FIG. In step SB4, an FF to be scanned is determined so that a test sequence can be generated in a predetermined number of time frames. In FIG. 9, SB4
a is a step of setting 1 as an initial value of a time frame number i to be searched and setting a designated time frame number t indicating an upper limit of the number of time frames to be processed; S
B4b is a step of determining whether or not the processing has been completed for the number of time frames corresponding to the designated time frame number t. If the processing has been completed, the process proceeds to step SB4m, whereas if not completed, the process proceeds to step SB4c. move on. SB4c is a step of searching the input side for one time frame from the external output or pseudo external output or the data input of the FF existing in the previous time frame. SB
4d is a step for determining whether or not FF exists in the current time frame searched in step SB4c;
If FF exists, the process proceeds to step SB4e, and if FF does not exist, the process ends. SB4e is a step of counting the number of FFs in the current time frame.
4f indicates that the time frame number i is the designated time frame number t
This is a step of determining whether or not the L / H type FF exists in the current time frame. If the time frame number i is different from the designated time frame number t and the current time frame has an L / H-type FF, the process proceeds to step SB4g; otherwise, the process proceeds to step SB4.
After that, the process returns to step SB4b. SB4g performs a state justification of the L / H-type FF of the current time frame;
SB4h is a step of determining whether or not the state justification of the L / H-type FF has succeeded. If the state justification of all the L / H-type FFs has succeeded, the process proceeds to Step SB4i. Proceed to SB4j. SB4i determines the search direction in the next time frame for the L / H-type FF for which the state justification has succeeded, SB4j
Is a step for determining that all L / H FFs in the current time frame are to be scanned when the state justification of the L / H FFs fails. SB4k is a step SB4j based on the number of FFs in the current time frame. This is a step of reducing the number of L / H-type FFs determined to be scanned in. In addition, SB4m is a step of determining all FFs present in the time frame in which the number of FFs counted in steps SB4d and SB4k is the minimum as those to be scanned.

The testability design method according to the present embodiment shown in FIGS. 8 and 9 will be described with reference to FIGS.

FIG. 10 is a diagram showing a sequential circuit to be subjected to the testability designing method according to the present embodiment. In FIG. 10, A to I are combinational circuits, r1 to r7 are FFs, PI1
PI4 indicates an external input, and PO1 and PO2 indicate external outputs. r3, r4, r6, r7 are L / H type F
F. Further, each arrow represents a connection relationship between the above-described components. It is assumed that all the clocks of the FFs r1 to r7 are connected to the same clock input, and the description thereof is omitted in FIG.

First, in step SB1, an FF to be scanned is determined for the circuit shown in FIG. 10 so that this circuit has an n-fold alignment structure. FIG. 11 is a diagram showing a result of determining an FF to be scanned so that the circuit of FIG. 10 has a double alignment structure. As shown in FIG. 11, here, only FFr5 is determined to be scanned. However, in step SB1, the L / H type FFr3,
Since r4, r6, and r7 are recognized as having no self-loop structure, none of them are determined to be scanned as shown in FIG.

Next, in steps SB2 to SB4, a partial scan is performed on the circuit of FIG. 11 based on the L / H type FF state justification. For the external output or pseudo external output selected in step SB3, step SB
4 according to the flowchart shown in FIG.
Scanning is performed based on the justification of the state of the H-type FF. However, in step SB4, the L / H type FF is regarded as a circuit including a combination of a selector and a DFF as shown in FIG. 7B. In this case, the load mode is set when the S input of the selector is "0", and the hold mode is set when the S input is "1". Here, it is assumed that the designated time frame number t is set to 3 in step SB4a.

First, at step SB3, the external output PO1 is selected, and step SB4 is executed.

FIG. 12 is a diagram showing the processing in step SB4 for the external output PO1. First, as shown in FIG. 12A, the input side is searched from the external output PO1, and the L / H
The type FFs r4 and r6 are reached (SB4c). The number of FFs in this time frame 1 is 2 (SB4e). Here, the time frame number i is 1, which is different from the specified number of time frames 3, and since the current time frame has L / H type FFs r4 and r6 (SB4f), the state of the L / H type FFs r4 and r6 is valid. (SB4g). FF
As a result of simultaneous state justification of the logical values “0” of the D inputs of r4 and r6, the state justification succeeds and the L / H type FFr
4 is determined to be the hold mode, and the L / H type FFr6 is determined to be the load mode. As the search direction in the next time frame, the input side of the hold mode is set for the L / H type FFr4, and the input side of the load mode is set for the L / H type FFr6 (SB4i).

Next, as shown in FIG. 12B, the input side of the hold mode of the L / H type FFr4 and the L / H type FFr4
The input side of the load mode of r6 is searched, and FFs r1 to r4
(SB4c). The number of FFs in this time frame 2 is 4 (SB4e). Here, the time frame number i is 2, which is different from the designated time frame number 3, and the current time frame has L / H type FFs r3, r4
(SB4f), the L / H type FFr3, r4
The logic value “0” of the D input is simultaneously state justified (S
B4g). Here, it is assumed that the state justification has failed. At this time, the L / H type r3, r4 is determined as the FF to be scanned (SB4j), and the F / F in the current time frame 2 is determined.
Reduce F number from 4 to 2.

Next, as shown in FIG.
Although the input side of 1, r2 is searched, the processing does not reach the FF and reaches the external inputs PI2 and PI3, so that the processing of step SB4 for the external output PO1 ends (SB4).
d). As a result, the L / H-type FFs r3 and r4 are determined to be scanned.

Next, in step SB3, the external output PO2 is selected, and step SB4 is executed.

FIG. 13 is a diagram showing the processing in step SB4 for the external output PO2. First, as shown in FIG. 13A, the input side is searched from the external output PO2, and L / H
The type FFr7 is reached (SB4c). The number of FFs in this time frame 1 is 1 (SB4e). here,
The time frame number i is 1, which is different from the designated time frame number 3, and the current time frame has L / H type FFr
7 (SB4f), the L / H-type FFr7 is justified (SB4g). Here, as a result of performing the logical “0” state justification, the state justification succeeds, and L / H
It is assumed that the type FFr7 is determined to be in the load mode. As the search direction in the next time frame, L / H type FFr
7 is set as the input side of the load mode (SB4
i).

Next, as shown in FIG. 13 (b), the input side of the load mode of the L / H type FFr7 is searched and reaches the FFr6 (SB4c). The number of FFs in this time frame 2 is 1 (SB4e). Here, since the time frame number i is 2, which is different from the designated time frame number, and the current time frame has the L / H type FFr6 (SB4f), the state of the L / H type FFr6 is justified (SB4g). ). As a result of performing the logical “0” state justification,
It is assumed that the state justification is successful and the L / H type FFr6 is determined to be in the load mode. The input side of the load mode is set for the L / H type FFr6 as the search direction in the next time frame (SB4i).

Next, as shown in FIG. 13 (c), the input side of the load mode of the L / H type FFr6 is searched and reaches the FFr2 (SB4c). The number of FFs in this time frame 3 is 1 (SB4e). Here, since the time frame number i is 3 and matches the designated time frame number t (SB4f), the time frame development is terminated (SB4f).
4b), FFs existing in the time frame having the smallest number of FFs are determined to be scanned (SB4)
m). Now, as shown in FIG.
Since the F numbers are all 1 and equal, it is determined here that FFr7 existing in the time frame 1 is to be scanned.

Next, at step SB3, the pseudo external output PPO
5 (data input of FFr5 determined to be scanned in step SB1) is selected, and step SB4
Execute

FIG. 14 is a diagram showing the processing in step SB4 for the pseudo external output PPO5. First, FIG.
As shown in (a), the input side is searched from the pseudo external output PPO5 and reaches the FFr2 (SB4c). The number of FFs in this time frame 1 is 1 (SB4e).
Since no L / H FF exists in this time frame (SB4f), the next time frame is developed.
As shown in FIG. 14 (b), when the input side of FFr2 is searched, the input has reached the external input PI3 without reaching the FF, so that the processing of step SB4 for the pseudo external output PPO5 is terminated (SB4d).

Next, at step SB3, the pseudo external output PPO
3 (Step S for external output PO1 shown in FIG. 12)
(Data input of DFF constituting L / H-type FFr3 determined to be scanned by the process of B4)
Is selected, and step SB4 is executed.

FIG. 15 is a diagram showing the processing in step SB4 for the pseudo external output PPO3. First, FIG.
As shown in (a), the input side is searched from the pseudo external output PPO3 and reaches the FFs r1 and r2 (SB4c). The number of FFs in this time frame 1 is 2 (SB4
e). Further, since there is no L / H type FF in this time frame 1 (SB4f), a search for the next time frame is performed. As shown in FIG. 15B, when the input side of the FFs r1 and r2 is searched, the external input PI
2, since it has reached PI3, the process of step SB4 for the pseudo external output PPO3 ends (SB4d).

Next, at step SB3, the pseudo external output PPO
4 (Step S for external output PO1 shown in FIG. 12)
(Data input of DFF constituting L / H-type FFr4 determined to be scanned by the process of B4)
Is selected, and step SB4 is executed.

FIG. 16 is a diagram showing the processing in step SB4 for the pseudo external output PPO4. First, FIG.
As shown in (a), the input side is searched from the pseudo external output PPO4 and reaches the FFs r1 and r2 (SB4c). The number of FFs in this time frame 1 is 2 (SB4
e). Further, since there is no L / H type FF in this time frame 1 (SB4f), a search for the next time frame is performed. Next, as shown in FIG.
When the input side of No. 2 was searched, it reached the external inputs PI2 and PI3 without reaching the FF.
Ends the processing of step SB4 for (SB4
d).

Next, at step SB3, the pseudo external output PPO
7 (Step S for external output PO2 shown in FIG. 13)
(Data input of DFF constituting L / H-type FFr7 determined to be scanned by the processing of B4)
Is selected, and step SB4 is executed.

FIG. 17 is a diagram showing the processing in step SB4 for the pseudo external output PPO7. First, FIG.
As shown in (a), the input side is searched from the pseudo external output PPO7 and reaches the FFr6 (SB4c). The number of FFs in this time frame 1 is 1 (SB4e).
The time frame number i is 1 which is different from the designated number of time frames, and the current time frame has L / H type FFr6
Exists (SB4f), the state of the L / H-type FFr6 is justified (SB4g). As a result of performing the logical “0” state justification, the state justification succeeds, and the L / H type FFr6
Is determined to be in the load mode. As the search direction in the next time frame, the input side of the load mode is set for the L / H type FFr6.

Next, as shown in FIG. 17 (b), the input side of the load mode of the L / H type FFr6 is searched, and FFr1,
r2 is reached (SB4c). The number of FFs in this time frame 2 is 2 (SB4e). Since the time frame 2 does not include the L / H type FF (SB4
f) Search for the next time frame.

Next, as shown in FIG.
When the input side of 1, r2 was searched, it reached the external inputs PI2 and PI3 without reaching the FF.
The process at step SB4 for PO7 is ended.

Since the processing of step SB4 has been completed for all external outputs and pseudo external outputs (SB2),
The design for testability according to the present embodiment ends. As a result, FFr5 determined to be scanned in step SB1 and L / H type FFr3, r4, r7 determined to be scanned in step SB4.
Are determined as FFs to be scanned.

As described above, the L / H type FF is not recognized as having a self-loop structure, and in addition to the process of determining the FF to be scanned so that the integrated circuit has an n-fold alignment structure, An integration including a large number of L / H FFs is performed by performing a process of determining FFs to be scanned so that a test sequence can be generated in a predetermined number of time frames based on the state justification of the L / H FFs. When a FF to be scanned is identified for a circuit, a high failure detection efficiency can be guaranteed at a relatively low scan ratio.

In this case, the state is justified by assigning a logical value “0” to a plurality of L / H-type FFs. This is because when a value is assigned to a plurality of L / H-type FFs at the same time,
The purpose is to know whether each L / H FF is justified in load mode or hold mode. Therefore, the logical value assigned in state justification is not limited to “0”, and another logical value may be assigned.

(Third Embodiment) FIG. 18 is a flowchart showing a flow of processing in a testability design method according to a third embodiment of the present invention.
In FIG. 18, SC1 is a step of determining an FF to be scanned so that the target circuit has an n-fold alignment structure, and is the same process as step SB1 of the second embodiment. That is, after recognizing that the L / H FF does not have the self-loop structure, the FF to be scanned is determined so that the circuit has the n-fold alignment structure.
As a result of step SC1, the L / H-type FF that is not determined to be scanned is referred to as a pure L / H-type FF here.

SC2 is a step for determining whether or not steps SC3 and SC4 have been executed for all the pure L / H-type FFs. When steps SC3 and SC4 are completed for all the pure L / H-type FFs, the processing is terminated. SC3 is a step of selecting one of the unprocessed pure L / H-type FFs. SC4 is a step of searching for the input side of the pure L / H-type FF selected in step SC3 from the load / hold selection input and combining them. This is a step of determining an FF that can be reached only through the circuit as an FF to be scanned.

The testability design method according to the present embodiment shown in FIG. 18 will be described with reference to FIG.

FIG. 19 is a diagram showing a sequential circuit to be subjected to the testability designing method according to the present embodiment. In FIG. 19, FF1 to FF8 are L / H type FFs, FF9 to FF1
5 is a normal FF that is not an L / H type, A to D are combinational circuits,
PI1 to PI8 are external inputs, and PO is an external output. Note that the combinational circuit C is a one-hot decoder (only one of the outputs has a different value from the other outputs).

First, in step SC1, an FF to be scanned is determined for the circuit shown in FIG. 19 so that this circuit has an n-fold alignment structure. Here, n = 1, that is, the circuit shown in FIG. 19 has a single alignment structure.
The FF to be scanned is determined. At this time, L / H type F
Since F1 to F8 are recognized as not having a self-loop structure, only FF15 is determined to be scanned.

Next, in steps SC2 to SC4, L
FFs that can be reached from the load / hold selection inputs of the / H-type FF1 to FF8 through only the combinational circuit are FF9 to FF8.
Since it is F12, FF9 to FF12 are determined as FFs to be scanned.

As a result, for the L / H type FFs 1 to 8,
In each case, the load / hold signal can be set arbitrarily through the scan path. For this reason, since most faults can be detected in the load mode, test sequence generation is facilitated. Also, depending on the circuit configuration, the scan rate can be reduced as compared with the case where all the L / H FFs have a self-loop structure and are scanned.

(Fourth Embodiment) A fourth embodiment of the present invention relates to a testability design method according to the third embodiment, in which the validity of an L / H FF
The determination is made based on the load mode ratio indicating the ratio of the ones whose status is justified in the load mode.

FIG. 20 is a flowchart showing the flow of processing in the testability design method according to the fourth embodiment of the present invention. In FIG. 20, SD1 is a step of determining an FF to be scanned by the design for testability according to the third embodiment, and SD2 is a threshold value P of the load mode ratio.
And initializing the values M and L for obtaining the load mode ratio. SD3 and SD4 are time frames using the L / H type FF state justification for each external output and each pseudo external output. This is a step of calculating the total number M of L / H-type FFs appearing in the time frame, and the total number L of L / H-type FFs whose state is justified in the load mode. In step SD5, it is determined whether or not the load mode ratio, that is, the value of (L / M) is larger than the threshold value P. If it is larger, it is determined that the design for facilitating inspection in step SD1 is effective, and this result is obtained. On the other hand, if not, it is determined that the design for testability in step SD1 is not effective, and in step SD6,
For example, a testability design based on the state justification of the L / H FF according to the second embodiment is executed.

FIG. 21 is a flowchart showing details of step SD4 of the testability designing method according to the present embodiment shown in FIG. In FIG. 21, SD4a is a step of developing a time frame for one time with respect to the external output selected in step SD3 or the input of the FF of the previous time frame. However, L /
As to the input of the H-type FF, as a result of the state justification, when the state is justified in the load mode, the load mode input and the select input are expanded, and when the state is justified in the hold mode, the hold mode input and the select are expanded. Expand for input. If there is an FF in the current time frame in step SD4b, step SD
Proceed to step 4c, and if not, end step SD4.

In step SD4c, the number of L / H-type FFs in the current time frame is set to m, and
If m = 0 in D4d, the process returns to step SD4a. In step SD4e, the state of all the L / H FFs existing in the current time frame is justified. If the state justification is successful, in step SD4g, the number of L / H-type FFs whose state is justified in the load mode is set to 1
On the other hand, if the state justification fails, 1 is set to 0 in step SD4h (step SD4h).
4f). In step SD4i, the value of m is added to the value of the total number M of L / H-type FFs appearing in the time frame, and the value of l is added to the value of total number L of L / H-type FFs whose state is justified in the load mode. Add.

The calculation of the load mode ratio will be specifically described with reference to the circuits shown in FIGS. Here, the threshold value P of the load mode ratio is set to 80%.

In the circuit shown in FIG.
1, FF9 to FF1 as in the third embodiment.
2 and FF 15 are determined as FFs to be scanned. FF1 which is an L / H type FF appearing in the time frame when the time frame is developed for the external output PO
Since FF9 to FF12 are scan FFs, all of the FF8 to FF8 can be justified in the load mode.
Further, when the pseudo external output PPO15 (input of the FF15 determined to be scanned) is time-frame expanded, the F / F type FF that appears in the timeframe is displayed.
Since F1 to FF8 are scan FFs in FF9 to FF12, all of them can be justified in the load mode. Therefore, the load mode ratio in this case is L / M
= 16/16 to 100%. That is, since the load mode ratio is larger than the threshold value P, the step SD
The result of the design for easy inspection 1 is adopted.

In FIG. 22, FF1 to FF4 are L
/ H type FF, FF5 and FF6 are normal L / H type F
F, A to D are combinational circuits, PI1 to PI6 are external inputs,
PO is an external output. Note that the combinational circuit C represents one hot decoder.

In the circuit shown in FIG.
1, the FFs FF5 and FF6, which can be reached from the load / hold selection inputs of the L / H FFs FF1 to FF4 through only the combinational circuit, are scanned.
Is determined as A time frame is developed for the external output PO, and the state is justified for FF1 to FF4, which are L / H FFs appearing in the time frame. As a result,
Since the combinational circuit C is a one-hot decoder, for example, F
F1 is justified in the load mode, and other FFs
2 to FF4 are justified in the hold mode. In this case, the load mode ratio is changed from L / M = 1/4 to 25%. In other words, since the load mode ratio is smaller than the threshold value P, the result of the design for testability in step SD1 is not used, and another design for testability, for example, L / A testability design based on the state justification of the H-type FF is executed.

(Fifth Embodiment) In a fifth embodiment of the present invention, before executing the testability designing method according to the second or third embodiment, a target circuit is Pre-processing. Specifically, among the FFs having a self-loop structure other than the L / H-type FF, those that can be state-justified without assigning a value to their own output are recognized as extended pure L / H-type FFs. The preprocessing is performed, and the FF recognized as the extended pure L / H-type FF is regarded as the L / H-type FF.
The testability design method according to the embodiment is executed. This makes it possible to reduce the scan rate for a circuit including many L / H FFs having a normal self-loop structure other than the L / H FFs.

A method of recognizing the extended pure L / H type FF will be described.

FIGS. 23 and 24 are diagrams showing FFs having a self-loop structure, and are diagrams for explaining a method of recognizing extended pure L / H type FFs.

In FIG. 23, as shown in FIG.
When the state justification of the logical value "0" is performed on the D input of F1a, "0" may be set on the input which does not constitute the loop of the AND gate 1b, and as shown in FIG. ,
When the state of the logical value "1" is justified at the D input of the FF 1a, "1" may be set to the input which does not constitute the loop of the AND gate 1b and the OR gate 1c.
That is, the state of the FF 1a can be justified without assigning a value to the Q output. In such a case,
The FF 1a is recognized as an extended pure L / H type FF.

In FIG. 24, as shown in FIG. 24 (a), when the state of the logical value "0" is justified at the D input of the FF 2a, the input of the AND gate 2b which does not constitute the loop is input to the other input. Although it is sufficient to set “0”, as shown in (b), when the state of the logical value “1” is justified at the D input of the FF 1a, the one that does not constitute the loop of the AND gate 1b The input must be set to "1" and the output of the NOT gate 2c must be set to "1". Therefore, "0" must be assigned to the Q output of the FF 2a. In such a case, the FF 2a recognizes that it is not an extended pure L / H type FF.

Further, a hold signal line is defined for an FF recognized as an extended pure L / H FF. When the state of the logical value “0” is justified, a loop is searched from the D input to the input side, the first signal line having no value set is defined as a 0 hold signal line, and the logical value “1” is defined. When the state justification is performed, a loop is searched from the D input to the input side, and the first signal line having no value set is defined as a 1-hold signal line. Then, of the 0 hold signal line and the 1 hold signal line, the signal line farther from the D input is defined as a hold signal line of the extended pure L / H FF.
For example, in the case of FIG. 23, the 0 hold signal line is a signal line 1d connecting the output of the OR gate 1c and the input of the AND gate 1b, and the 1 hold signal line is connected to the Q output of the FF 1a and the O output.
Since the signal line 1e connects the input of the R gate 1c,
D of the hold signal lines 1d and 1e
The one far from the input, that is, one hold signal line 1e is defined as a hold signal line of the extended pure L / H type FF 1a.

The reason why the hold signal line is defined is to make a finite number of time frames when expanding the time frames. FIGS. 25A and 25B are diagrams showing the time frame expansion of the circuit shown in FIG. 23. FIG. 25A shows a normal time frame expansion, and FIG. 25B shows a time frame expansion using a hold signal line. As shown in FIG.
In normal time frame development, when there is a loop in the circuit, time frame development is repeated indefinitely. Therefore, in order to make the number of time frames finite, after all,
An FF having a self-loop structure must be scanned. On the other hand, as shown in FIG. 25B, in the time frame expansion using the hold signal line, when the state of the extended pure L / HFF can be justified in the load mode, in the next time frame, the hold signal line Does not appear, this FF itself does not appear. Therefore, the number of time frames becomes finite, and the FF to be scanned can be determined.

FIG. 26 is a diagram showing a sequential circuit to be subjected to the testability designing method according to the present embodiment. In FIG. 26, FF1 to FF4 are FFs having a self-loop structure,
FF5 to FF11 are FFs having no self-loop structure,
PI1 to PI3 are external inputs, PO is an external output, and A and B are combinational circuits.

For the sequential circuit shown in FIG. 26, first, it is determined by preprocessing according to the present embodiment whether or not FF1 to FF4 having a self-loop structure are extended pure L / H type FFs.

As shown in FIG. 27A, FF1 is
Since the value “0” must be assigned to the Q output when the state of the logical value “0” is justified for the input, it is determined that the input is not the extended pure L / HFF. FIG. 27 (b),
As shown in (c), the FF2 receives a logical value “0” at the D input.
It is not necessary to assign a value to the Q output both when the status justification is performed and when the logic value "1" is justified, so it is determined that the output is the extended pure L / HFF, and the 0 hold signal line 3a And the 0 hold signal line 3a farther from the D input among the 1 hold signal lines 3b is defined as the hold signal line of the FF2.

As shown in FIGS. 28A and 28B,
The FF3 does not need to assign a value to the Q output when the state of the logical value “0” is justified for the D input or when the state of the logical value “1” is justified, so the extended pure L / HF
J is determined to be F, and the 0 hold signal line 4a farthest from the D input of the 0 hold signal line 4a and the 1 hold signal line 4b is defined as the hold signal line of the FF3. Further, as shown in FIGS. 28 (c) and (d), FF4
Does not need to assign a value to the Q output both when the state of the logical value “0” is justified for the D input and when the state of the logical value “1” is justified. It is determined that there is, and of the 0 hold signal line 5a and the 1 hold signal line 5b, the 0 hold signal line 5a farther from the D input is defined as the hold signal line of the FF3.

Next, the testability design method according to the second embodiment as shown in FIG. 8 is executed on the circuit of FIG. However, step SB1 is executed after recognizing that the FF2 to FF4 recognized as the extended pure L / H type FF in the preprocessing do not have the self-loop structure.

First, in step SB1, an FF to be scanned is determined so that the circuit has a single alignment structure. In this case, FF1 which has a self-loop structure and is not recognized as the extended pure L / H FF in the preprocessing is determined to be scanned.

Next, step SB4 for the external output PO
Execute Here, the designated time frame number t is set to 3.

FIG. 29 is a diagram showing the result of time frame expansion (time T) for one time for the external output PO. As shown in FIG. 29A, FF2 to FF recognized as extended pure L / HFF are included in this time frame.
Since there are four, the number of FFs is three. D of FF2 to FF4
As a result of assigning a logical value “0” to the input and justifying the state, as shown in FIG. 29B, the FF2 and FF3 do not need to assign a logical value to their own outputs, so the state is justified in the load mode. Since the FF 4 needs to assign a logical value “0” to its own Q output, the FF 4 determines that the state has been justified in the hold mode.

FIG. 30 is a diagram showing the result of time frame development (time T-1) for the next one time based on the result of FIG. As shown in FIG. 30A, the FF4 recognized as the extended pure L / HFF is included in this time frame.
And FF7 to FF11 having no self-loop structure, the number of FFs is 6. As a result of assigning a logical value “0” to the D input of FF4 and performing state justification, FIG.
As shown in (b), since the FF 4 does not need to assign a logical value to its own Q output, it is determined that the state is justified in the load mode.

FIG. 31 is a diagram showing the result of time frame development (time T-2) for the next one time based on the result of FIG. As shown in FIG. 31, the number of FFs is 2 because there are FF10 and FF11 that do not have a self-loop structure in this time frame. Since development was performed for three time frames, the time T-2 at which the number of FFs was the smallest was calculated.
FF10, FF1 which are FFs belonging to the time frame of
1 is determined to be scanned.

As described above, according to the present embodiment, all FFs having a self-loop structure have been scanned in order to guarantee high fault detection efficiency. Pure L / H type F
Since the FF recognized as F is regarded as an L / H type FF and the testability design method according to the second embodiment is executed,
With respect to a circuit including many FFs having a self-loop structure other than the H-type FF, it is possible to reduce the scan ratio while maintaining high fault detection efficiency. In addition, extended pure L / H
Inspection design for circuits that recognize type FF is the second
The present invention is not limited to the design for testability according to the third embodiment. For example, the design method for testability according to the third embodiment may be used.

(Sixth Embodiment) In a sixth embodiment of the present invention, as a pre-process of the design for testability according to the first embodiment, a flip-flop, an external input, and an external Of the output,
An FF relation graph representing a connection relation that can be reached via only the combinational circuit is created. By performing time frame expansion for determining an FF to be scanned using this FF relationship graph, the amount of calculation required for time frame expansion can be significantly reduced.

In this embodiment, as preprocessing of the design for testability according to the first embodiment, a reachable external output and a pseudo-external output are obtained for the FF of the integrated circuit, and the FF is reachable from the FF. The FFs belonging to the paths to the external output and the pseudo external output are obtained as reachable FFs. The reachable external output and pseudo-external output of each FF and the data on the reachable FF are referred to as reachable data herein. When determining whether an integrated circuit has an n-fold alignment structure assuming that one FF is not scanned, an external output capable of reaching the one FF is referred to by referring to the reachable data. And pseudo external output,
Further, by performing time frame expansion only on the pseudo external output which is the data input of the FFs which can be reached to this one FF and provisionally determined to be scanned, the amount of calculation required for time frame expansion is greatly increased. Can be reduced.

FIG. 32 is an FF relation graph created for the sequential circuit shown in FIG. In FIG. 32, r1 to r
4 is FF, PI1 and PI2 are external inputs, PO1 and PO2
Is an external output. The FF relation graph of (a) is a direct representation of the sequential circuit of FIG. 2. However, since FFr3 has a self-loop structure and is determined to be scanned, the FF relation graph is as shown in (b). FFr3 is deleted from the graph, and the input of FFr3 is replaced with the pseudo external output PP.
The output may be replaced with a pseudo external output PPI3 at O3.

FIG. 33 shows reachable data created based on the FF relation graph shown in FIG. 32 (b). The reachable data in FIG. 33 indicates that, for FFr1, for example, reachable external outputs and pseudo external outputs are PO1 and PPO3, and reachable FFs are r2 and r4.

The testability design method according to the first embodiment shown in FIG. 1 is executed based on the FF relation graph shown in FIG. 32B and the reachable data shown in FIG. Here, in step SA7, it is determined whether or not the circuit has a single alignment structure. That is, when the FF selected in step SA4 is non-scanned and the circuit does not have a single alignment structure, in step SA8, the selected FF is provisionally determined to be scanned.

First, in step SA1, FIG.
All FFr1, FFr1, in the FF relation graph shown in FIG.
It is temporarily determined that r2 and r4 are to be scanned. The scanned FFri is regarded as a pseudo external output PPOi and a pseudo external input PPIi.

FIG. 34 is a diagram showing time frame development when FFr1 is made non-scanning. According to the reachable data shown in FIG. 33, since the external output and the pseudo external output that can reach the FFr1 are only PO1 and PPO3, first, time frame expansion is performed on the external output PO1 and the pseudo external output PPO3 ((a), (b) )). According to the reachable data shown in FIG. 33, FFs that can reach FFr1 are r2 and r4.
4 is tentatively determined to be scanned, so FF
Data input of r2, r4, ie, pseudo external output PPO
2, time frame expansion is performed for PPO4 ((c), (d)). Time frames are not expanded for external outputs or pseudo external outputs other than PO1, PPO2 to PPO4. As shown in FIG. 34, no two or more identical FFs appear in each expanded time frame, so that this circuit has a single alignment structure. Therefore, FFr1 is provisionally determined to be non-scanned.

FIG. 35 is a diagram showing time frame development when FFr2 is made non-scan. According to the reachable data shown in FIG. 33, the only external output that can reach FFr2 is PO1, so that time frame expansion is first performed on the external output PO1 ((a)). According to the reachable data shown in FIG. 33, the FF that can reach FFr2 is r4
Since FFr4 is provisionally determined to be scanned at this stage, time frame expansion is performed on the data input of FFr4, that is, the pseudo external output PPO4 ((b)). Time frames are not expanded for external outputs or pseudo external outputs other than PO1 and PPO4.
As shown in FIG. 35, since the same FF does not appear more than once in each developed time frame, this circuit has a single alignment structure. Therefore, FFr2 is provisionally determined to be non-scanned.

FIG. 36 is a diagram showing a time frame development when FFr4 is non-scanned. According to the reachable data shown in FIG. 33, the only external output that can reach FFr4 is PO1, so that time frame expansion is performed for the external output PO1. In the expanded time frame,
Since two FFs r1 and r2 appear, this circuit does not have a single alignment structure. Therefore, FFr4 is provisionally determined to be scanned.

As a result of the above processing, FFr3, r4
Has been provisionally determined to be a scan,
Fr3 and r4 are determined as FFs to be scanned.

As described above, according to the present embodiment, instead of performing time frame expansion on a sequential circuit including nine gates, time frame expansion may be performed on an FF relation graph including three gates. Further, by using reachable data, the number of times of time frame development can be reduced from 10 to 7. Therefore,
The amount of calculation required for time frame expansion can be significantly reduced.

In the case of the design for testability other than the first embodiment, the amount of calculation is greatly reduced by creating an FF relation graph and determining a flip-flop to be scanned based on the FF relation graph. can do.

(Seventh Embodiment) A seventh embodiment of the present invention relates to a design method for facilitating inspection of a logic circuit which is an integrated circuit designed at a gate level. Is regarded as a pseudo external output and the data output is regarded as a pseudo external input, the number of gate stages is n or less (n is 0) in each path from the external input or pseudo external input to the external output or pseudo external output. Or a natural number).

The design method for testability according to the present embodiment will be described with reference to FIG. FIG. 37 is a diagram showing a logic circuit targeted by the testability designing method according to the present embodiment. In FIG. 37, FF1 to FF7 are flip-flops, PI1 and PI2 are external inputs, and PO is an external output. Here, in each path from the external input or pseudo external input to the external output or pseudo external output, the FF to be scanned is determined for the circuit shown in FIG. 37 so that the number of gate stages is 6 or less.

In the circuit shown in FIG. 37, FF1 → FF5 →
Loop 1 of FF6 → FF1 (10 gate stages) and FF
There is a loop 2 of 2 → FF5 → FF2 (the number of gate stages 2). Here, first, a loop 1 having a larger number of gate stages
Is determined so as to break.

Assuming that FF1 among the FFs constituting the loop 1 has been scanned, the maximum number of gate stages in each path is 10, F in the path from FF1 to FF1.
Infinity on the path from F1 to the external output PO, 4 on the path from the external input PI1 to FF1, 8 on the path from the external input PI2 to FF1, infinity on the path from the external input PI1 to the external output PO, external input The path from PI2 to the external output PO is infinite. Similarly, FF5
Is assumed to be a scan, the maximum number of gate stages in each path is 10 in the path from FF5 to FF5,
The value is 8 for the path from the external input PI1 to the FF5, 4 for the path from the FF5 to the external output PO, 2 for the path from the external input PI2 to the FF5, and 9 for the path from the external input PI2 to the external output PO. Further, assuming that the FF6 is scanned, the maximum number of gate stages in each path is 10 in the path from FF6 to FF6, and the external input P
10 on the path from I1 to FF6, 2 on the path from FF6 to external output PO, infinity on the path from external input PI2 to FF6, and from external input PI1 to external output PO
Infinity on the path to the external input PI2 to the external output P
The path to O is infinite.

As described above, FF1,
Of the FF5 and FF6, the paths in which the maximum number of gate stages is infinite remain even if the FF1 and FF6 are scanned,
When the FF 5 is scanned, there is no path in which the maximum number of gate stages is infinite. Therefore, here, FF5 is first determined as the FF to be scanned.

When FF5 is scanned, the path where the maximum number of gate stages exceeds 6 is FF5 → FF6 → FF1 → F
F5 (maximum number of gate stages 10), PI1 → FF1 → FF5
(Maximum number of gate stages 8), PI2 → FF3 → FF7 → PO
(Maximum number of gate stages 9), PI2 → FF2 → FF7 → PO
(Maximum number of gate stages: 7). Assuming that the FFs included in these paths are scanned one by one, a path in which the maximum number of gate stages exceeds 6 is obtained.

Assuming that FF6 is to be scanned,
The route where the maximum number of gate stages exceeds 6 is F6 → FF1 → F
F5 (maximum number of gate stages 8), PI1 → FF1 → FF5
(Maximum number of gate stages 8), PI2 → FF3 → FF7 → PO
(Maximum number of gate stages 9), PI2 → FF2 → FF7 → PO
(Maximum number of gate stages: 7). Assuming that FF1 is to be scanned, there are two paths in which the maximum number of gate stages exceeds 6: PI2 → FF3 → FF7 → PO (maximum number of gate stages 9) and PI2 → FF2 → FF7 → PO (maximum number of gate stages 7). is there. Assuming that FF3 is to be scanned, the path where the maximum number of gate stages exceeds 6 is FF5 → F
F6 → FF1 → FF5 (maximum number of gate stages 10), PI1
→ FF1 → FF5 (maximum number of gate stages 8), PI2 → FF
2 → FF7 → PO (maximum number of gate stages: 7).
Assuming that FF2 is scanned, the path in which the maximum number of gate stages exceeds 6 is FF5 → FF6 → FF1 → FF
5 (maximum number of gate stages 10), PI1 → FF1 → FF5
(Maximum number of gate stages 8), PI2 → FF3 → FF7 → PO
(Maximum number of gate stages: 9). Assuming that the FF7 is scanned, the paths whose maximum number of gate stages exceeds 6 include FF5 → FF6 → FF1 → FF5 (maximum number of gate stages 10), PI1 → FF1 → FF5 (maximum number of gate stages 8), PI2 → FF3 → FF7. → PO (maximum number of gate stages: 9).

As a result, the number of paths whose maximum number of gate stages exceeds 6 becomes the smallest when FF1 is scanned, so that FF1 is determined to be FF for scanning.

Further, when the FF2 or FF3 is scanned, there is no path in which the maximum number of gate stages exceeds 6, so here, it is determined that the FF2 is to be scanned.

FIG. 38 is a diagram showing an execution result of the testability designing method according to the present embodiment for the circuit shown in FIG. As shown in FIG. 38, FF1, FF2, and FF5 are determined to be scanned. As a result, the circuit has a non-closed circuit structure, and the number of gate stages is six or less in each path from an external input or pseudo external input to an external output or pseudo external output. As a result, in the circuit after the scan path is inserted,
Inspection input generation becomes easy.

(Eighth Embodiment) FIG. 39 is a flowchart showing a flow of processing in a testability design method according to an eighth embodiment of the present invention.
The testability design method according to the present embodiment shown in FIG.
When determining an FF to be scanned so that the circuit has an n-fold alignment structure, the value of n is reduced while keeping the scan rate low, the time required for test sequence generation is short, and the fault detection efficiency is reduced. It is determined to be sufficiently high.

In the n-fold alignment structure, generally, as the value of n decreases, the scan rate increases, but the time required for test sequence generation tends to decrease and the fault detection efficiency tends to increase. . On the other hand, as the value of n increases, the scan rate decreases, but the test sequence generation time increases and the fault detection efficiency decreases. Therefore, the optimum value of n needs to be determined by a trade-off between the scan ratio and the test sequence generation time and the fault detection efficiency.

However, according to the experiment of the present inventor, n
When the value of is increased, the test sequence generation time tends to sharply increase from the time when n reaches a certain value,
Moreover, the value of n at which the test sequence generation time sharply increases is
It varied depending on the configuration of the circuit. For this reason, it was difficult to determine the optimal value of n.

As a result of further study by the inventors of the present application, regarding a circuit in which an FF to be scanned is determined by the design for testability, the data input of the FF to be scanned is regarded as a pseudo external output, and the data output is regarded as a pseudo external input. When the time frame expansion of each external output and each pseudo external output is performed, there is a high correlation between the number of flip-flops or gates in the expanded time frame, the test sequence generation time, and the fault detection efficiency. It turned out that there was. In the present specification, the number of flip-flops in an expanded time frame is referred to as a test sequence generation influence flip-flop number, and the number of gates in the expanded time frame is referred to as a test sequence generation influence gate number. In other words, it has been confirmed by the experiments of the present inventor that when the test sequence generation time rapidly increases, the number of test sequence generation influence flip-flops or the number of test sequence generation influence gates also rapidly increase.

The invention according to the present embodiment uses the number of test sequence generation influence flip-flops or the number of test sequence generation influence gates as an index for determining the value of n.

The testability design method according to this embodiment shown in FIG. 39 will be described with reference to FIGS.

FIG. 40 is an FF relation graph showing a circuit to be subjected to the testability designing method according to the present embodiment. In FIG. 40, A to L are FFs, PI1 to PI4 are external inputs, and PO is an external output.

It is assumed that 1.6 is set as threshold value P in step SE1. In step SE2, n is initialized to 1, and in step SE3, an FF to be scanned is determined so that the circuit indicated by the FF relation graph of FIG. 40 has a single-aligned structure.

FIG. 41 (a) shows an FF which scans the FF relation graph of FIG. 40 so as to have a single alignment structure.
It is a figure which shows the result of having been determined. As shown in FIG. 41A, FFs C, E, F, and L are determined as FFs to be scanned. In step SE4, FIG.
As shown in (b), C, which is an FF to be scanned,
E, F, and L data inputs are simulated external outputs PPOC, PP
OE, PPOF, PPOL, and data outputs as pseudo external inputs and PPIC, PPIE, PPIF, PPIL, and external output PO and pseudo external output PPOC,
Perform time frame expansion for PPOE, PPOF, and PPOL, and check sequence generation influence flip-flop number AI
Find F (1). AIF (1) becomes 12. Further, since the order depth of the circuit is 2, the process proceeds to step SE7, and the value of n is increased to 1 by adding 1.

Returning to step SE3, since n = 2, the FF to be scanned is determined so that the circuit shown by the FF relation graph of FIG. 40 has a double alignment structure. FIG.
FIG. 41 (a) is a diagram illustrating a result of determining an FF to be scanned so as to have a double alignment structure in the FF relationship graph of FIG. 40. As shown in FIG. 42 (a), FF C,
F and L are determined as FFs to be scanned. In step SE4, as shown in FIG. 42B, the data inputs of the FFs C, F, and L to be scanned are regarded as pseudo external outputs PPOC, PPOF, and PPOL, and the data outputs are output as pseudo external inputs and PPIC, PPIF. , PPIL
And the external output PO and the pseudo external output PPO
C, PPOF, and PPOL are subjected to time frame expansion, and the check sequence generation influence flip-flop number AIF
Find (2). AIF (2) becomes 15. In step SE5, AIF (2) / AIF (1) = 15 /
Since 12 = 1.2 <P = 1.6, the process proceeds to step SE6. Since the sequence depth of the circuit is 3, the process proceeds to step SE7.
Then, the value of n is set to 3 by adding 1.

Returning to step SE3, since n = 3, an FF to be scanned is determined so that the circuit shown by the FF relation graph of FIG. 40 has a triple alignment structure. FIG.
FIG. 41 (a) is a diagram illustrating a result of determining an FF to be scanned so as to have a triple alignment structure in the FF relation graph of FIG. 40. As shown in FIG. 43 (a), FF C,
L is determined as the FF to be scanned. In step SE4, as shown in FIG. 43B, the data inputs of C and L, which are FFs to be scanned, are regarded as pseudo external outputs PPOC and PPOL, and the data outputs are regarded as pseudo external inputs and PPIC and PPIL. The time frame expansion is performed on the external output PO and the pseudo external outputs PPOC and PPOL, and the number AIF (3) of the test sequence generation influence flip-flops is obtained. AIF (3) becomes 24. In step SE5, AIF (3) / AIF (1) =
Since 24/12 = 2.0> P = 1.6, step SE
Proceed to 8, and set the value of n to 2 by subtracting 1 and end the processing. That is, the double alignment structure is determined to be optimal.

(Ninth Embodiment) FIG. 44 shows an LSI composed of the same three blocks A.
FIG. When designing for testability of an LSI composed of a plurality of blocks, simply determining an FF to be scanned so as to make the test easier for each block does not necessarily mean that the LSI becomes testable. For example, when the connection between the blocks has a loop structure as in the LSI in FIG. 44, the LSI does not necessarily have the n-fold alignment structure even if each block A has the n-fold alignment structure. Absent.

Therefore, in the ninth embodiment of the present invention,
Before deciding FFs to be scanned for each block, FFs to be scanned for FFs that can reach the input side from the block output through only the combinational circuit in each block.
Pre-processing is determined. In this embodiment, an FF that can reach the input side from the block output through only the combinational circuit is referred to as an output unit FF.

FIG. 45 is a flowchart showing the flow of processing in the testability design method according to the present embodiment.
As shown in FIG. 45, as a pre-process, a step SF1 of deciding to scan the output unit FF in each block is executed. Then, as shown in (a),
Scanning based on the n-fold alignment structure as described in the first embodiment is executed for each block (Step S
As shown in F2) and (b), scanning is performed for each block based on the state justification of the L / H FF as described in the second embodiment (step SF3).

FIG. 46 is a diagram showing an example of the result of executing step SF1 for a certain circuit block. In FIG. 46, A to I are combinational circuits, and r1 to r7 are F
F, BPI1 to BPI4 are block inputs, BPO1, BPO
PO2 indicates a block output, respectively. When the input side is searched from the block output BPO1, the FFs that can be reached only through the combinational circuit are r4 and r6. When the input side is searched from the block output BPO2, the FFs that can be reached only through the combinational circuit are r4 and r6. r5 and r7. Therefore, as shown in FIG. 46, FFr4, r5, r6,
r7 is recognized as the output unit FF, and these are determined to be scanned. After that, step SF2 is executed as in the first embodiment.

FIG. 47 is a diagram showing another example of the result of executing step SF1 for a certain circuit block.
In FIG. 47, A to I are combinational circuits, r1, r2, r
5 is FF, r3, r4, r6, and r7 are L / H type FFs, B
PI1 to BPI4 are block inputs, BPO1, BPO2
Indicates a block output. Block output B
When the input side is searched from PO1, the FFs that can be reached only through the combinational circuit are r4 and r6. When the input side is searched from the block output BPO2, the FFs that can be reached only through the combinational circuit are r5 and r5. r7. Therefore, as shown in FIG. 47, FFr4, r5, r6, r7
Are recognized as the output unit FF, and these are determined to be scanned. After that, as in the second embodiment,
Step SF3 is executed.

As described above, according to the present embodiment, in each block of the LSI, the output unit FF that can be reached from the block output through only the combinational circuit is determined as the FF to be scanned, and then the first FF is set for each block. In addition, since the FF to be scanned is determined by the testability design method as described in the second embodiment, high failure detection efficiency can be guaranteed at the stage of determining the scan FF. In addition, the test input sequence generation complexity of the LSI can be simplified from the LSI circuit scale level to the block circuit scale level.

Note that, instead of the output unit FF, an FF that can reach from the block input to the output side only through the combinational circuit
May be determined as the FF to be scanned. However, in general, the input unit FF has a larger number than the output unit FF, and thus it is preferable to determine the output unit FF as the FF to be scanned.

(First Reference Example) FIG. 48 is a flowchart showing the flow of processing in the test sequence generation method according to the first reference example of the present invention. The test sequence generation method according to this reference example is to generate a test sequence while sequentially compressing and storing the test sequence generated for each fault in a given integrated circuit in a buffer.

In FIG. 48, SG1 is a step of determining whether or not a loop exists in the circuit. If a loop exists, the process proceeds to step SG2, and if no loop exists, the process proceeds to step SG3. Step SG2
Then, a value specified in advance is set as a buffer length, one buffer having this buffer length is provided, and all data is initialized to don't care. In step SG3, a value obtained by adding 1 to the order depth of the circuit is set as the buffer length, one buffer having this buffer length is provided, and all the data is initialized to don't care.

After setting the buffer length in steps SG2 and SG3, the maximum number of buffers is specified in step SG4.

SG5 is a step of determining whether or not a test sequence has been generated for all undetected faults in the circuit. If a test sequence has been generated for all undetected faults, the process proceeds to step SG6. If there is an undetected fault for which a test sequence has not been generated yet, the process proceeds to step SG7. In step SG6, a failure simulation is executed using all the test sequences stored in the buffer group.

SG7 is a step of selecting one fault as a target fault from undetected faults for which a test sequence has not yet been generated, and SG8 is a step of generating a test sequence for the target fault selected in step SG7.

SG9 is a step in which it is determined whether or not the length of the test sequence generated in step SG8 is longer than the buffer length set in step SG2 or SG3. If it is long, proceed to step SG10; otherwise, proceed to step SG11. If there is no loop in the circuit, the buffer length is set to (order depth + 1) in step SG3, so that the length of the test sequence does not become longer than the buffer length. In step SG10, a failure simulation is performed on the generated test sequence. Step SG1
In step 1, the generated test sequence is compressed and stored in a buffer. Details of step SG11 will be described later.

SG12 is a step in which it is determined whether or not the number of buffers has exceeded the maximum number of buffers specified in step SG4 as a result of the compression and storage in step SG11.
If the number of buffers is larger than the maximum number of buffers, the process proceeds to step SG13; otherwise, the process proceeds to step SG13.
Go back to G5. In step SG13, a failure simulation is performed using the test sequence stored in the buffer having the smallest number of don't cares, and this buffer is deleted.

FIG. 49 is a flowchart showing the details of the process of step SG11 in the test sequence generation method according to the present embodiment shown in FIG. In FIG. 49, SG11
The step a is a step of judging whether or not an attempt has been made to compress and store all the buffers for the test sequence generated in step SG8. If all buffers have been tried to be compressed and stored, the process proceeds to step SG11g. If there is a buffer that has not yet been compressed and stored, the process proceeds to step SG11b.

SG11b is a step of selecting one buffer for which compression storage has not been tried yet. SG11c
Is a step of judging whether or not compression storage has been tried for all the start positions in the buffer selected in step SG11b. When compression storage has been tried for all start positions, the process returns to step SG11a, and when there is a start position for which compression storage has not yet been tried, the process proceeds to step SG11d. In step SG11d, a start position at which compression storage is attempted is selected. For one buffer, (buffer length−test sequence length + 1) start positions can be selected.

SG11e is a step of judging whether or not the test sequence generated in step SG8 is compressed and stored in the buffer selected in step SG11b from the start position selected in step SG11d. In this step SG11e, the logical value “0” of the test sequence is
The logical value “0” or don't care in the buffer can be compressed, but the logical value “1” cannot be compressed. The logical value “1” of the test sequence can be compressed as the logical value “1” in the buffer or don't care. It is determined whether or not the test sequence can be compressed and stored based on a compression rule that it is possible but cannot be compressed with the logical value "1".

If it is determined in step SG11e that the test sequence can be compressed and stored, the test sequence is compressed and stored in the buffer based on the compression rule in step SG11f.

SG11g is a process for adding a new buffer and storing the test sequence in the new buffer when the test sequence could not be compressed and stored in any buffer. SG11h is a process of sorting the buffers in descending order of the number of don't cares.

The test sequence generation method according to the present embodiment shown in FIGS. 48 and 49 will be described with reference to FIGS. Here, there is no loop in the target circuit, and the order depth of the circuit is 2. Further, faults a, b, c, d are detected as undetected faults in the target circuit.
It is assumed that there is. 50 to 53, X1 to X3
Is an external input, A and B are buffers, data 0 in the buffer is a logical value "0", 1 is a logical value "1", and X is don't care.

In step SG1, since no loop exists in the target circuit, the flow advances to step SG3.
3 which is a value obtained by adding 1 to the order depth is set as the buffer length. Then, as shown in FIG. 50A, a buffer A having a buffer length of 3 is generated, and all the data is initialized to don't care. At step SG4, 2 is designated as the maximum number of buffers.

Next, for a fault a selected at step SG7, a test sequence is generated at step SG8.
In step SG11, the test sequence of the fault a is compressed and stored in the buffer A. In this case, the buffer length and the fault a
Since the length of the test sequence is the same, only 0 is possible as the start position, and all the data in the buffer A is initialized to "don't care", so that the data can be compressed based on the compression rule already described. As a result, FIG.
As shown in (b), the test sequence of the fault a is compressed and stored in the buffer A.

Next, for a fault b selected in step SG7, a test sequence is generated in step SG8.
As shown in FIG. 51A, the test sequence of the failure b is compressed and stored in the buffer A. In this case, since the buffer length is equal to the length of the test sequence of the fault b, only 0 is possible as the start position. As a result of trying compression storage based on the compression rule described above, compression is not possible. Therefore, as shown in FIG. 51B, a new buffer B is added to store the test sequence of the failure b. Since the don't care number of the buffer A is 4 and the don't care number of the buffer B is 5, the buffers are sorted in the order of the buffers B and A.

Next, for a fault c selected in step SG7, a test sequence is generated in step SG8.
As shown in FIG. 52A, the test sequence of the fault c is compressed and stored in the buffers A and B. In this case, since the length of the test sequence for the fault c is 2, only 0 and 1 are possible as start positions. As a result of attempting compression storage based on the compression rule described above, buffer B was not able to be stored when the start position was 0 or 1. Buffer A could not be stored when the start position was 0, but could be stored when the start position was 1. From this result, as shown in FIG. 52 (b), the test sequence of the fault c is compressed and stored in the buffer A with the start position set to 1.
Since the number of don't cares in buffer A is 1 and the number of don't cares in buffer B is 5, buffers B and A are sorted in this order.

Next, a test sequence is generated in step SG8 for the fault d selected in step SG7,
As shown in FIG. 53, the test sequence of this failure d is compressed and stored in buffers A and B. In this case, the buffer length and the failure d
Since the length of the test sequence is equal, only 0 is possible as the start position. As a result of the trial of the compression storage based on the compression rule described above, it is impossible to store the data in both the buffer B and the buffer A. In the buffer C. Since the number of don't cares in buffer A is 1, the number of don't cares in buffer B is 5, and the number of don't cares in buffer C is 3, the buffers are sorted in the order of buffers B, C, and A.

Since the number of buffers has exceeded the maximum number of buffers 2 (step SG12), of the buffers A, B, and C,
A fault simulation is executed by randomly entering a logical value “0” or “1” in the test sequence stored in the buffer A with the smallest number of don't cares, instead of the don't cares. Then, the buffer A is deleted, and the buffer C storing the test sequence of the failure d is set as the buffer A (step S
G13).

Since there are no undetected faults for which no test sequence has been generated (step SG5), the buffer A,
A logical value “0” or “1” is randomly entered in the test sequence stored in B instead of the don't care, and a fault simulation is executed (step SG6).

As described above, in test sequence generation, compression is dynamically performed using a buffer, so that a short test sequence can be generated.

(Second Reference Example) FIG. 54 is a flowchart showing a flow of processing in a test sequence generation method according to a second reference example of the present invention. The test sequence generation method according to the present reference example is to generate a test sequence while sequentially compressing and storing in a buffer a test sequence generated for each fault in a given circuit. However, the algorithm for compressing and storing in the buffer is different from that of the first reference example.

In FIG. 54, SH1 is a step for judging whether or not a loop exists in the circuit. If a loop exists, the procedure proceeds to step SH2. If no loop exists, the procedure proceeds to step SH3. Step SH2
Then, a value L specified in advance is set as the buffer length, N buffers (N is a positive integer) of the buffer length L are provided, and all the data is initialized to don't care. In step SH3, a value obtained by adding 1 to the order depth of the circuit is set as the buffer length, and N buffers of this buffer length are provided to initialize all data to don't care.

In step SH4, it is determined whether or not the ratio of don't care among the data in the N buffers, that is, the don't care ratio has exceeded a predetermined upper limit value P. If the don't care rate exceeds the upper limit value P, the process proceeds to step SH5, in which a logic value "0" or "1" is inserted instead of the don't care of the buffer data, and a failure simulation is performed. Is updated to don't care. If the don't care rate does not exceed the upper limit P, the process proceeds to step SH7.

In step SH7, it is determined whether or not the test sequence has been generated for all the faults. If the test sequence has been generated for all the faults, the process proceeds to step SH8, where the logical value " The fault simulation is executed by inserting “0” or “1”.

SH9 is a step of selecting one fault as a target fault from undetected faults for which a test sequence has not yet been generated, and SH10 is a step of generating a test sequence for the target fault selected in step SH9.

In step SH11, the length of the test sequence generated in step SH10 is changed to step SH2 or step SH3.
Is a step of determining whether or not the length of the test sequence is longer than the buffer length. If the length of the test sequence is longer than the buffer length, the process proceeds to step SH12; otherwise, the process proceeds to step SH13. If there is no loop in the circuit, the buffer length is (order depth +
Since it is set to 1), the length of the test sequence does not become longer than the buffer length. In step SH12, a failure simulation is performed using the generated test sequence. In step SH13, the generated test sequence is compressed and stored in N buffers. Details of step SH13 will be described later. It is determined in step SH14 whether or not compression storage was possible. If compression and storage were successful, the process returns to step SH4. If compression and storage was not possible, a failure simulation was performed in this test sequence in step SH12.
Return to H4.

FIG. 55 is a flowchart showing the details of the processing in step SH13 in the test sequence generation method according to the present embodiment shown in FIG. In FIG. 55, SH13
a is a step of initializing the start position i to 0, SH13b
SH13e is a step of judging whether or not the test sequence can be compressed and stored in the N buffers while incrementing the start position i. If possible, compress and store the test sequence; otherwise, end the process.

The test sequence generation method according to the present embodiment shown in FIGS. 54 and 55 will be described with reference to FIGS. Here, there is no loop in the target circuit, and the order depth of the circuit is 2. Further, the number N of buffers is 2, and the upper limit value P of the don't care rate is 6
0%. It is also assumed that the target circuit has faults a, b, c, and d as undetected faults. Figures 56 to 59
, X1 to X3 represent external inputs, 0 of data in the buffer represents a logical value "0", 1 represents a logical value "1", and X represents don't care. The processing is performed by regarding the N buffers as one buffer.

In step SH1, since no loop exists in the target circuit, the flow advances to step SH3.
3 which is a value obtained by adding 1 to the order depth is set as the buffer length. Then, as shown in FIG. 56 (a), two buffers with a buffer length of 3 are generated, this is regarded as one buffer with a buffer length of 6, and all the data is initialized to don't care.

In step SH4, the don't care rate is equal to the upper limit value P.
It is determined whether or not the value has exceeded the value. In this case, since the don't care rate is 0%, the process proceeds to step SH7.

Next, for a fault a selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault a is compressed and stored in a buffer. As shown in FIG.
Since the data can be stored when the start position is 0, the data is stored as shown in FIG. The don't care rate is 5/18, less than 60%.

Next, for a fault b selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault b is compressed and stored in a buffer. As shown in FIG.
When the start position is 1, the data can be compressed and stored.
Store as shown in. Don't care rate is 60 at 8/18
Less than%.

Next, for the fault c selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault c is compressed and stored in a buffer. As shown in FIG.
When the start position is 4, the data can be compressed and stored.
Store as shown in. Don't care rate is 6 at 12/18
Greater than 0%. Therefore, a failure simulation is performed in step SH5, and all the buffer data is updated to "don't care" in step SH6.

Next, for a fault d selected in step SH9, a test sequence is generated in step SH10, and in step SH13, the test sequence for this fault d is compressed and stored in a buffer. As shown in FIG.
When the start position is 0, the data can be compressed and stored.
The test sequence of the fault d is stored as shown in FIG. The don't care rate is 6/18, less than 60%.

As described above, according to the present embodiment, whether or not further compression storage is possible is determined based on the don't care rate of the buffer, so that dynamic compression of the test sequence can be efficiently realized. Further, by regarding the plurality of buffers as one buffer, the test sequence can be compressed and stored across the plurality of buffers, so that the compression ratio can be further increased.

[0182]

As described above, according to the testability designing method according to the present invention, the FF to be scanned is determined so that the integrated circuit has the n-fold alignment structure.
In identifying F, high fault detection efficiency can be guaranteed. In addition, when identifying an FF to be scanned with respect to an integrated circuit including a large number of L / H-type FFs, it is possible to guarantee high fault detection efficiency with a relatively low scan rate.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a flow of processing in a testability designing method according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an integrated circuit to be subjected to a testability design method according to the first embodiment of the present invention.

FIGS. 3 (a) to 3 (e) show F of the integrated circuit of FIG.
FIG. 7 is a diagram illustrating a time frame development when Fr1 is not scanned.

4 (a) to 4 (d) show F of the integrated circuit of FIG.
FIG. 11 is a diagram illustrating a time frame development when Fr2 is not scanned.

FIG. 5 is a diagram showing a time frame development when FFr4 is not scanned in the integrated circuit of FIG. 2;

FIG. 6 is a diagram showing a result of executing the testability designing method according to the first embodiment of the present invention on the integrated circuit of FIG. 2;

FIGS. 7A and 7B are diagrams showing L / H-type FFs.

FIG. 8 is a flowchart illustrating a flow of processing in a testability design method according to a second embodiment of the present invention.

FIG. 9 is a flowchart showing details of step SB4 in FIG. 8;

FIG. 10 is a diagram illustrating a sequential circuit to be subjected to a testability designing method according to a second embodiment of the present invention.

11 is a diagram showing a result of determining an FF to be scanned so that the circuit of FIG. 10 has a double alignment structure.

FIGS. 12A to 12C are diagrams showing the processing of step SB4 for the external output PO1 with respect to the circuit of FIG. 11;

FIGS. 13A to 13C are diagrams showing the processing of step SB4 for the external output PO2 with respect to the circuit of FIG. 11;

14 (a) and (b) are diagrams showing the processing of step SB4 for the pseudo external output PPO5 for the circuit of FIG. 11;

FIGS. 15A and 15B are diagrams showing the processing of step SB4 for the pseudo external output PPO3 for the circuit of FIG. 11;

FIGS. 16 (a) and (b) are diagrams showing the processing of step SB4 for the pseudo external output PPO4 for the circuit of FIG. 11;

FIGS. 17 (a) to (c) are diagrams showing the processing of step SB4 for the pseudo external output PPO7 for the circuit of FIG. 11;

FIG. 18 is a flowchart showing a flow of a process in a testability design method according to the third embodiment of the present invention.

FIGS. 19A and 19B are diagrams showing sequential circuits to be subjected to the testability designing method according to the third embodiment of the present invention.

FIG. 20 is a flowchart illustrating a flow of processing in a testability design method according to a fourth embodiment of the present invention.

FIG. 21 is a flowchart illustrating details of step SD4 in FIG. 20;

FIGS. 22A and 22B are diagrams illustrating a sequential circuit to be subjected to the testability designing method according to the fourth embodiment of the present invention.

23 (a) and (b) show F having a self-loop structure.
FIG. 6 is a diagram illustrating F, and is a diagram for describing a method of recognizing an extended pure L / H type FF.

24 (a) and (b) show F having a self-loop structure.
FIG. 6 is a diagram illustrating F, and is a diagram for describing a method of recognizing an extended pure L / H-type FF.

25A and 25B are diagrams showing a time frame development of the circuit shown in FIG. 23, where FIG.
(B) shows a time frame development using a hold signal line.

FIG. 26 is a diagram illustrating a sequential circuit to be subjected to the testability designing method according to the fourth embodiment of the present invention;

FIGS. 27 (a) to (c) show F in the circuit of FIG. 26;
FIG. 9 is a diagram illustrating a determination as to whether F1 and FF2 are extended pure L / H-type FFs.

FIGS. 28 (a) to (d) show F in the circuit of FIG. 26;
It is a figure which shows determination of whether F3 and FF4 are extended pure L / H type FFs.

FIGS. 29 (a) and (b) are diagrams showing the result of one-time time frame expansion of the external output PO1 with respect to the circuit of FIG. 26.

30 (a) and (b) show the following 1 based on the results of FIG.
It is a figure showing the result of having performed time frame expansion for time.

FIG. 31 is a diagram showing a result of performing time frame development for the next one time from the result of FIG. 30;

FIGS. 32A and 32B are FF relation graphs created for the sequential circuit shown in FIG. 2;

FIG. 33 shows reachable data created based on the FF relation graph shown in FIG. 32 (b).

34 (a) to (d) are diagrams showing time frame development when FFr1 is non-scanned in the FF relation graph shown in FIG. 32 (b).

FIGS. 35 (a) and (b) are diagrams showing time frame development when FFr2 is non-scanned in the FF relation graph shown in FIG. 32 (b).

FIG. 36 is a diagram showing a time frame development when FFr4 is not scanned with respect to the FF relation graph shown in FIG. 32 (b).

FIG. 37 is a diagram illustrating a logic circuit to be subjected to the testability designing method according to the seventh embodiment of the present invention;

FIG. 38 is a diagram showing an execution result of the testability designing method according to the seventh embodiment of the present invention for the circuit shown in FIG. 37;

FIG. 39 is a flowchart showing the flow of processing in the testability design method according to the eighth embodiment of the present invention.

FIG. 40 is an FF relation graph showing a circuit to be subjected to the testability designing method according to the eighth embodiment of the present invention.

FIG. 41 (a) shows the FF relation graph of FIG. 40.
FIG. 9B is a diagram illustrating a result of determining an FF to be scanned so as to have a single alignment structure, and FIG. 9B is a diagram illustrating a time frame development for the result of FIG.

FIG. 42A is a graph showing the FF relation graph of FIG.
FIG. 7B is a diagram illustrating a result of determining an FF to be scanned so as to have a double alignment structure, and FIG. 7B is a diagram illustrating a time frame development for the result of FIG.

FIG. 43 (a) shows the FF relation graph of FIG.
FIG. 7B is a diagram illustrating a result of determining an FF to be scanned so as to form a triple alignment structure, and FIG. 7B is a diagram illustrating a time frame development for the result of FIG.

FIG. 44 shows an LS composed of the same three blocks A
It is a schematic diagram showing I.

FIGS. 45 (a) and (b) are flowcharts showing the flow of processing in the testability design method according to the ninth embodiment of the present invention.

FIG. 46 is a diagram showing a result of executing step SF1 of FIG. 45 for a certain circuit block;

FIG. 47 is a diagram showing the result of executing step SF1 of FIG. 45 for a certain circuit block;

FIG. 48 is a flowchart showing a processing flow in a test sequence generation method according to the first reference example of the present invention.

FIG. 49 is a flowchart showing details of the process of step SG11 in FIG. 48.

FIGS. 50A and 50B are diagrams for explaining a test sequence generation method according to the first reference example of the present invention.

FIGS. 51A and 51B are diagrams for explaining a test sequence generation method according to the first reference example of the present invention.

FIGS. 52A and 52B are diagrams for explaining a test sequence generation method according to the first reference example of the present invention.

FIG. 53 is a diagram for explaining a test sequence generation method according to the first reference example of the present invention.

FIG. 54 is a flowchart showing a flow of processing in a test sequence generation method according to a second reference example of the present invention.

FIG. 55 is a flowchart showing details of the processing in step SH13 in FIG. 54.

FIGS. 56A and 56B are diagrams for explaining a test sequence generation method according to the second embodiment of the present invention; FIGS.

FIGS. 57 (a) and (b) are diagrams for explaining a test sequence generation method according to a second reference example of the present invention.

FIGS. 58 (a) and (b) are diagrams for explaining a test sequence generation method according to a second reference example of the present invention.

FIGS. 59 (a) and (b) are diagrams for explaining a test sequence generation method according to a second reference example of the present invention.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-72223 (JP, A) JP-A-61-222582 (JP, A) Transactions of the Institute of Electronics, Information and Communication Engineers, Vol. J 80-DI No. 2 PP. 155-163 (February 1997) (58) Fields investigated (Int. Cl. ⁷ , DB name) G01R 31/28 G01R 31/3183 G06F 11/22 360 G06F 17/50

Claims (15)

(57) [Claims] 1. An easy-to-test design method for changing a design of an integrated circuit designed at a gate level so that a test after manufacturing is easy. The flip-flop to be scanned is determined so that the circuit has an n-fold alignment structure (n is an integer and is determined based on the fault detection efficiency and the scan ratio). The full-scan process that tentatively determines that the flip-flop is to be scanned, and the respective flip-flops that are tentatively determined to be scanned in the full-scan process. It is determined whether or not the integrated circuit has the n-fold alignment structure. If the integrated circuit has the n-fold alignment structure, the flip-flop is scanned. A non-scanning selection process for maintaining a tentative decision that the flip-flop is to be scanned when the n-fold alignment structure is not obtained, while the full scan process and the non-scanning A testability design method wherein a flip-flop provisionally determined to be scanned as a result of executing the scanning selection process is determined as a flip-flop to be scanned. 2. The method for designing for testability according to claim 1, wherein the non-scanning selection process recognizes a flip-flop having a self-loop structure among the flip-flops of the integrated circuit and has a self-loop structure. For the flip-flop recognized as, the process of determining whether or not the logic circuit has the n-fold alignment structure when it is assumed that scanning is not performed is omitted, and a tentative decision that scanning is performed is maintained. A design method for facilitating inspection characterized by the following. 3. The design method for testability according to claim 1, wherein a reachable external output and a pseudo external output are obtained for the flip-flop of the integrated circuit, and the reachable external output and the pseudo external output are obtained from the flip-flop. The non-scanning selection processing is performed by assuming that a flip-flop belonging to a path to an external output is determined as a reachable flip-flop. When determining whether or not to have a column structure, the reachable external output and pseudo external output obtained in the pre-processing for the one flip-flop, and the reach obtained in the pre-processing for the one flip-flop Data input of tentatively determined possible flip-flops to be scanned A test design method for facilitating inspection, characterized in that a time frame is expanded for the pseudo external output. 4. The testability design method according to claim 1, wherein, for the integrated circuit, a FF relation graph representing a connection relation of a flip-flop, an external input, and an external output that can be reached only through a combinational circuit with each other. And a flip-flop to be scanned is determined based on the FF relation graph created in the preprocessing. 5. An easy-to-test design method for making a design change on an integrated circuit designed by RTL so as to facilitate a test after manufacture, wherein all registers of the integrated circuit are scanned. The integrated circuit has an n-fold aligned structure (n) when it is assumed that the register is not scanned for each register temporarily determined to be scanned in the full scan process. Is an integer, and is determined based on the fault detection efficiency and the scan ratio). When the register has an n-fold alignment structure, the register is temporarily determined not to be scanned. , A non-scanning selection process for maintaining a tentative decision that the register is to be scanned when it does not have an n-fold alignment structure, A design method for facilitating inspection, wherein a register provisionally determined to be scanned as a result of execution of the logical and non-scanning selection processing is determined as a register to be scanned. 6. An inspection-easy design method for making a design change on an integrated circuit designed at a gate level and configured from a plurality of blocks so that inspection after manufacturing is facilitated. In each block of the circuit, an output unit FF that can be reached from the block output to the input side only through the combinational circuit or an input unit that is an FF that can reach the block side from the block input to the output side only through the combinational circuit FF,
A first process for determining an FF to be scanned, and in each of the blocks, the block has an n-fold alignment structure (n is an integer and is determined based on the fault detection efficiency and the scan ratio). And a second process for determining a flip-flop to be scanned. 7. An easy-to-test design method for making a design change for an integrated circuit designed at a gate level so that a test after manufacturing is facilitated, wherein the load / hold type flip-flop has a self-loop structure. Flip-flops constituting the integrated circuit so that the integrated circuit has an n-fold alignment structure (n is an integer and is determined based on the fault detection efficiency and the scan ratio) without being recognized as a flip-flop having the flip-flop. A first test facilitation process for determining a flip-flop to be scanned from among the flip-flops, and a load / hold flip-flop for the integrated circuit in which the flip-flop to be scanned is determined in the first test facilitation process To determine the flip-flop to be scanned so that the inspection of the flip-flop becomes easy.
And a test facilitation process. 8. The testability design method according to claim 7, wherein the second testability processing is performed on the integrated circuit for which the flip-flop to be scanned is determined in the first testability processing. A time frame is developed based on the state justification of the load / hold type flip-flop, and from this time frame development,
A testability design method for determining a flip-flop to be scanned. 9. The testability design method according to claim 7, wherein the second testability processing is performed on the integrated circuit for which a flip-flop to be scanned is determined in the first testability processing. A load / hold type flip-flop which has not been determined to be scanned and which can be reached from a load / hold selection input through only a combinational circuit is determined to be scanned. Inspection design method. 10. The testability design method according to claim 9, wherein, as a result of the second testability processing, a ratio of the load / hold type flip-flop of the integrated circuit whose state is justified in the load mode. When the load mode rate exceeds a predetermined value, the determination result of the flip-flop to be scanned in the second inspection facilitation processing is used, but the load mode rate does not exceed the predetermined value. In some cases, the result of the second test facilitation processing does not use a result of determining a flip-flop to be scanned. 11. The testability design method according to claim 10, wherein the flip-flop to be scanned in the first testability processing is determined when the load mode ratio does not exceed a predetermined value. For the integrated circuit, a time frame is developed based on the justification of the state of the load / hold type flip-flop, and a third inspection facilitation process for determining a flip-flop to be scanned is executed based on the time frame expansion. Inspection design method. 12. The method for designing for testability according to claim 7, wherein, among flip-flops having a self-loop structure, those whose state can be justified without assigning a value to their own output are expanded pure load / A preprocessing for recognizing the flip-flop as a hold flip-flop; wherein the first and second inspection facilitation processes respectively load and hold the flip-flop recognized as the extended pure load / hold flip-flop in the preprocessing. A testability designing method characterized by determining flip-flops to be scanned by regarding the flip-flops as flip-flops. 13. An inspection-easy design method for making a design change on an integrated circuit designed at a gate level and composed of a plurality of blocks so that inspection after manufacture is facilitated. In each block of the circuit, an output unit FF that can be reached from the block output to the input side only through the combinational circuit or an input unit that is an FF that can reach the block side from the block input to the output side only through the combinational circuit FF,
A first process for determining an FF to be scanned; and in each of the blocks, the load / hold type flip-flop is not recognized as a flip-flop having a self-loop structure, and the block is an n-fold aligned structure (n is an integer). And a flip-flop to be scanned in the second process is determined so as to be determined based on the failure detection efficiency and the scan rate. And a third process of determining a flip-flop to be scanned so that the load / hold type flip-flop can be easily inspected for each block. 14. A testability design method for determining a flip-flop to be scanned for an integrated circuit designed at a gate level so as to facilitate inspection after manufacturing, comprising: When the input is regarded as a pseudo external output and the data output is regarded as a pseudo external input, the number of gate stages is n in each path from the external input or pseudo external input to the external output or pseudo external output.
A design method for facilitating inspection, wherein a flip-flop to be scanned is determined so that n is 0 or a natural number. 15. A testability design method for determining a flip-flop to be scanned so as to facilitate a test after manufacture of an integrated circuit designed at a gate level, wherein the structure of the integrated circuit is n. Multiple alignment structure (n is an integer;
A first process for determining a flip-flop to be scanned so as to be determined based on a failure detection efficiency and a scan ratio, and a flip-flop to be scanned for the integrated circuit determined in the first process. The data input of the flip-flop is regarded as a pseudo-external output, the data output is regarded as a pseudo-external input, and time-frame expansion of each external output and pseudo-external output is performed. A second process for determining the number of generation-influence flip-flops or the number of test-sequence generation-influenced gates, which is the number of gates; Perform the first and second processes, respectively, and determine the test sequence generation influence offset obtained by the second process. Flop number or based on test sequence generation influence gates, testability method characterized by determining the value of said n.