JP3316512B2 - Control circuit for CD-ROM drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a control circuit for a ROM drive, and more particularly to a main control circuit of a CD-ROM drive using a DRAM for providing a working memory space for executing a signal decoding operation. More specifically, the present invention provides a main control circuit for a CD-ROM drive, which can improve the performance of the entire system by using a DRAM working memory with reduced access frequency and can reduce the cost by realizing the whole system as a one-chip IC. About.

[0002]

2. Description of the Related Art Laser disk drives fall into the category of digital storage devices widely used in computer systems, especially microprocessor-based personal, home, and office computers. In the description herein, these laser-based digital storage devices are commonly referred to as optical disk drives, or simply drives as is common in the art.

[0003] Philip / Sony CD (Compact Disc) players are categorized as optical disc drives based on laser technology. CDs themselves have been transformed from their initial intended use as storage media for music to digital storage of information in various formats. A great deal of digital information can be recorded on the surface of a 12 cm diameter disc. Different applications have been developed based on different formats of these CD variants. For example, in addition to early music CDs, CD-RO
CD drives, known as M drives, are becoming widely used in the personal computer industry. The modular design of the CD-ROM drive fits in the expansion bay of a typical personal computer system, such as an IBM compatible machine, and helps to provide large amounts of data storage at low cost.

A CD-ROM disk medium widely used in the personal computer industry is a medium that can hold information of 650 MB or more and conforms to International Standard (ISO) -9660. In addition to searching for information contained on CD-ROM discs, current CD-ROM drives
Like a multimedia VCD, a music CD can be played. CD-ROM drives have become substantially the standard subsystem for personal computers.

C is widely used in personal computer systems.
Since the acceptance of D-ROM drives, there has been severe competition in the CD-ROM manufacturing business. The direct consequence of this business competition is manifested in a rapid increase in performance and a rapid decline in price. Advances in microprocessor technology, such as the recently developed DVD (Digital Video Disc) for the purpose of storing files and / or high-resolution image / video information, have led to larger and faster information storage and storage. It fulfills an increasing demand for search. For example, a music CD player may have its standard spindle speed of 100 to about 300 rpm.
m, the CD-ROM drive, while operating at
It has been developed to operate at 2X (twice the spindle speed), 4X, 6X, 8X, and even 10X or more.
For data retrieval purposes, this increased spindle speed substantially improves the data transfer rate of the drive.

A digital electronic control circuit used in a conventional CD-ROM drive includes an IC chip set separated into two chips. One of the two is
This is a read control IC, and the other is a signal decode IC. The read control IC is provided with a de-inter
It includes an internal SRAM with a memory space of about 2 Kbytes used as a data processing space for releasing operation. In contrast, the signal decoder controls the external DRAM to execute the active memory cache.

Since the two IC chips are physically separated, the internal RAM in the read control IC becomes indispensable. If the two can be incorporated into a one-chip IC, and the DRAM memory device is
If the C internal SRAM could be used instead, the access frequency to the DRAM would naturally be increased to an impractical level. This is because DRAMs are inherently slower in operation speed than SRAMs, which hinders the formation of such a one-chip design.

In order to explain the present invention, a conventional CD-R
The configuration of the electrical control circuit of the OM is roughly verified below. FIG. 1 is a block diagram showing a circuit configuration of a digital control electronic circuit of a conventional CD-ROM drive. As shown in the block diagram, the circuit includes a read access controller 120, a signal decoder 130, an RF (high frequency) amplifier 110, and a DRAM 140. These circuit elements are organized and connected by a wire network. A laser pickup head 103 and a disk spindle motor 102 are shown and are included in this drive. These are the optical and electrical mechanical components of the drive mechanism controlled by the read access controller 120.

In the prior art, the circuit elements of FIG. 1 can be implemented as separate IC chips. For example, before assembling into one control electric circuit, the DRAM 1
40 may be an independent memory IC chip. Similarly,
The RF amplifier 110 is an independent RF IC, and the read access controller 120 and the signal decoder 130 are physically independent of each other.

In the case of the circuit configuration of FIG. 1, a conventional CD-R connected to a host computer system such as a personal computer system accessing a CD-ROM.
The operation of the OM drive is as follows. The spindle motor 102 rotates the CD-ROM disk 101,
Also, the laser pickup head 103 is
Is searched for recorded data formed in the form of minute pits on the surface of the. The data picked up by head 103 is then relayed to RF amplifier 110 via connection 4. After amplification, the data portion is sent via connection 5 to a DSP (digital signal processor) 121 in the read access controller 120. The DSP 121 processes the received data, controls the disk spindle motor 102 via the connection line 7 based on the obtained data, and maintains the rotation speed at an appropriate value. On the other hand, the DSP 121 controls the laser pickup head 103 via the connection line 6,
The entire drive mechanism is fine-tuned to achieve sufficient beam focusing and proper head tracking.

For servo control, DS via connection line 5
In addition to being sent to P121, the RF signal also
It is sent to the demodulator 122 of the read access controller 120 to perform decoding of the FM (8 to 14 modulation coding) code. In the EFM demodulator 122, the digital signal is R
It is extracted from the F signal and demodulated according to the provisions of the IEC (International Electrotechnical Commission) 908 standard. The result of the EFM demodulation is a data signal arranged in byte units, which is sent to a CIRC (Cross-Interlib Reed-Solomon) decoder 123 for decoding Reed-Solomon codes.

[0012] The CIRC decoder 123 also performs error detection and correction (EDC) in accordance with the IEC 908 standard, similar to the deinterleave operation. To perform deinterleaving when receiving input data and to act as a data buffer, the CIRC decoder 123
It is necessary to have a circuit configuration that incorporates sufficient memory space for the operation throughout the entire operation process. This memory space is typically a 2K byte SRAM 124 as shown in the figure.

After error detection and deinterleaving,
The data is converted serially in a serial output unit 125 and then transmitted to the next processing circuit, namely the signal decoder 130, via connection 26.

The signal decoder 130 has an internal RSPC
(Reed-Solomon product-like code) Decoder 1
32 is used to perform error detection and correction in accordance with the provisions of the ISO / IEC 10149 standard. This is connection line 2
6 is performed by the RSPC decoder 132 performing an operation on the serial data received by the signal decoder 130 through the RPC 6. EDC generation unit 134 of signal decoder 130 then performs data error detection on the data block. If any errors are detected, a correction process is activated and corrected. After processing by the EDC generation unit 134, the data is stored in the CD-RO
It is relayed to the IDE or SCSI interface of the M drive and then transmitted to the bus 150 under the control of the interface unit 133. Thus, data can be received on the bus 150 by the host computer system.

In such a conventional CD-ROM drive, the read access controller 120 and the signal processor 13
One of the differences from 0 is that the signal processor 130 needs to use a cache memory for its operation. As the data access speed of the CD-ROM drive increases, the data cache system in the operation for decoding data becomes indispensable. However, the cache hit rate in the cache memory is directly related to the size of the cache memory. In other words, it is impossible to achieve a meaningful hit rate with a cache area that is too small. The result is that additional external memory, such as DRAM 140, is needed because 2K bytes of SRAM memory space is substantially too small to provide useful cache space for signal processor 130. In this case, the EDC generation unit 1
34, the RSPC unit 132 and the interface control unit 133 have an external DRA instead of their corresponding small internal SRAMs.
M140 is used as a work space. The read access controller 120 has its own small-capacity SRAM 124.

In FIG. 1, the read access controller 12
0 internal SRAM 124 and signal processor 130 external DR
Both AMs 140 experience a substantially proportional increase in access frequency as the CD-ROM spindle speed increases. Therefore, when designing the control electronics of the CD-ROM drive, the SRAM 124 and the DRAM 140
The maximum allowable access speed of both is CD-ROM
It is increased as the spindle speed of the drive is improved.

The following analysis calculates the frequency of access to the corresponding SRAM 124 and DRAM 140 by the read access controller 120 and signal decoder 130, respectively, when the CD-ROM drive is reading data from the disk surface. For convenience, the calculations are based on the assumption that the drive control electronics are SRAM 124 and DRA
When you have to access both sides of M140,
One data block (2
048 bytes). The access frequency of the memories 124 and 140 by the control electronics has been calculated on the basis of statistics and comparisons.

It is specified that the calculation is performed based on the range of a CD-ROM based on ISO9660.
All calculations were performed taking into account the worst case read / write access to the memory device when the RS code read error of the 9660 standard increased and a correction process had to be performed. However, as will be appreciated,
It is not normal to detect errors in each of the accesses to a normal CD-ROM disc. Nevertheless, as those skilled in the art agree,
The design of the control electronics of a CD-ROM drive must take into account the worst cases included in the design specifications.

Based on the above assumptions and through normal processing, the internal SR by read access controller 120
The access frequency to the AM 124 is calculated as 3,136 accesses. Data input: 98 × 32 = 3,136.

Thus, each data block (3
For a 2-byte 98 data frame), the EFM demodulator 122 sends a total of 3,136 bytes of data to the CIRC decoder 123. CIRC decoder 123 then stores these data in SRAM 124 and
One word (hereinafter referred to as C1) deinterleaving and error detection are performed on the CIRC encoded data. C1: 98 × (32 + 2 × 2) = 3,528.

At the stage of the C1 word, the data of each frame is processed in the following manner. The 32-byte RS code syndrome is first read, the errors contained therein are detected, and the error value is determined. Errors are then corrected. Typically, C1 can correct two errors by reading each error value and writing back the correct value. Therefore, all error correction processes
It includes two memory accesses, one read access and one write access to data. Up to 2
Since there are two allowed errors, the sum of the maximum read / write access times is 2 × 2 = 4 (including both read and write).

From the above, the maximum number of read / write accesses to each of the data frames is 36
Obviously, it becomes (32 + 2 × 2). However, since there are a total of 98 frames, a total of 3,528 times of S
RAM access is maximized at the C1 stage. then,
In the C2 (C2 word stage, hereinafter referred to as C2) stage, C2: 98 × (28 + 2 × 4) = 3,528. Becomes

In comparison with the (32, 28) RS code at the C1 stage, the RS code at the C2 stage is a (28, 24) RS code accompanied by 28 bytes of input data. Since C1 relays the delete bit to C2, C2 can identify up to four errors. As with C1, each error requires one read operation and one write operation to complete one error correction.

Thus, for C2, each data frame needs to be accessed a maximum of 36 (28 + 2 × 4) times in the SRAM. For a total of 98 data frames, a maximum of 3,528 (98 ×
(28 + 2 × 4)) read / write accesses are expected.

After the C1 and C2 stages of the error correction process, only 24 of the 32 bytes of each data frame are required to be relayed to the decoder. As a result,
It is predicted that 2,352 accesses in 98 data frames will be the maximum value. Data output: 98 × 24 = 2,352.

In summary, when a CD-ROM drive accesses a data block on the data surface of a disk, the S achieved by the read access controller 120
The number of accesses to the RAM 124 is predicted to be 12,544 at maximum. 98 × 32 + 98 × (32 + 2 × 2) + 98 × (8 + 2
× 4) + 98 × 24 = 12,544.

Under the same conditions as for the read access controller 120, for the signal controller 130, its access to the external DRAM 140 is analyzed as follows. Data entry: 2,340.

In accordance with the ISO / IEC 10149 standard, a total of 2,340 bytes out of 2,352 bytes sent by the read access controller 120 are required to be input to the DRAM 140 as other than the synchronization pattern and the header. .

P subcode: 2 × (43 × 26 + 2 × 1
× 43) = 2,408. The P subcode has 43 groups (26, 2) based on the MSB (most significant bit) and LSB (least significant bit).
4) can be obtained by organizing into two sets of RS codes. If one error had been corrected for each (26,24) RS code, 2 × 1 read / write accesses to the DRAM outside of signal decoder 130 would be required. Thus, there are a total of 2,408 read / write accesses. 2 × 43 × (26 + 2 × 1) = 2,408.

The first number 2 in the above equation indicates that there are two sets of data, MSB and LSB. On the other hand, 43 is 43 (26, 24) RS in total
Indicates that the sign is present. 26 indicates that there is 26 data in each RS code, and 2 × 1 indicates that both reading and writing are required to perform error correction.

Q subcode: 2 × 26 × (45 + 2 ×
1) = 2,444. The Q subcode is divided into two sets, each containing 26 groups of (45,43) RS codes based on MSB and LSB. Similarly, for each (45, 43) RS code with one corrected error, two accesses, read and write, are performed in the DRAM. Therefore, as in the case of the P subcode, DRA
The total number of accesses in M is 2,444. 2 × 26 × (45 + 2 × 1) = 2,444, and EDC: 2,068.

In accordance with the ISO / IEC 10149 standard, the EDC is composed of 2,068 bytes, and is therefore DR
A total of 2,068 accesses to the AM are required.

Data output: 2,048. When finally reaching the bus, the interface controller retrieves 2,048 bytes of data from the DRAM and places them on the output.

In summary, when a CD-ROM drive is accessing one data block on the storage surface of a disk, the signal decoder 130 will make a maximum of 11,308 accesses in the external DRAM. . 2,340 + 2 × 43 × (26 + 2) + 2 × 26 × (4
5 + 2) + 2,068 + 2,048 = 11,308.

Based on the above analysis calculations, the read access controller 120 and the signal decoder 130 are integrated,
And that all data accesses to the internal SRAM 124N are instead directed to the external DRAM 140 (in other words, the internal SRAM 124 is connected to the read access controller 1
20), the total number of memory accesses when the CD-ROM drive is reading one data block is simply the SRAM 124 and DR
It is the sum of the accesses in both AM 140. Suppose
When the RAM 124 is removed, the access to the DRAM 140 is 23,582 times in total. 12,544 + 11,308 = 23,852. For DRAM 140, this is effectively a doubled increase in access frequency.

Therefore, the read access controller 120 and the signal decoder 130 of the conventional CD-ROM drive control electronic circuit are integrated on a single IC chip, and the access toward the SRAM 124 inside the read access controller 120 is performed by a signal. Assuming that it is going to the DRAM 140 outside the decoder 130, a serious problem arises. This problem is due to the fact that DRAMs are inherently much slower than SRAMs. In a conventional CD-ROM drive, the SRAM 124 in the read access controller 120 is simply removed and the access is
Assuming heading to zero, the bandwidth of memory accesses in DRAM can be more than 10 times higher than standard single speed drives.
It never meets the requirements of D-ROM drives. In other words, if the internal SRAM is removed, a fast DRAM must be used. Otherwise, a data transfer failure will occur in the DRAM. However, it is well known that high speed DRAMs are expensive.

[0037]

SUMMARY OF THE INVENTION It is, therefore, one object of the present invention to provide an integrated circuit device which is combined with a read access controller and a signal controller of a conventional CD-ROM drive and assembled into one IC device. It is to provide a control circuit device with reduced cost.

Another object of the present invention is to provide for all the improved performance characteristics based on proper design of the data processing operation,
An object of the present invention is to provide a control circuit device which requires a reduced access frequency in an externally connected DRAM.

[0039]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is directed to a digital-to-analog converter that reads and decodes data stored on a CD-ROM disc and transfers the data to a host computer system via a bus interface. A circuit device for controlling a CD-ROM drive for data storage is provided. This apparatus reads out data stored on the surface of the CD-ROM disc by using a CD-ROM.
It has a digital signal processor (DSP) that controls the spindle motor and laser pickup head of the ROM disk and receives signals representing the read data transmitted by the RF amplifier; An EFM code demodulator receives the data output of the RF amplifier to perform EFM demodulation to obtain an EFM code. CIRC code processor is CI
To perform decoding of an RC code, an output of the EFM demodulator is received. Reed-Solomon decoding engine is R
Used to perform S decoding. RSPC / EDC
A processor receives the output of the CIRC processor and the Reed-Solomon code decoding engine to perform error detection and correction. The Reed-Solomon code decoding engine receives outputs of the CIRC processor and the RSPC / EDC processor to perform decoding of the Reed-Solomon code. The bus interface controller is
The digital data finally decoded by the control circuit device of the CD-ROM drive is relayed to the bus interface for transmission to the host computer system. The CIRC processor and the RSPC / EDC processor, together with a bus interface controller, are connected to the working memory device of the CD-ROM drive so as to be able to directly and independently access the memory space of the working memory device. Directly connected to

Other objects, aspects and advantages of the present invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. This description is made with reference to the accompanying drawings.

[0041]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 4, in the conventional CD-ROM drive of FIG.
The read access controller 120 and the signal decoder 130 implemented on a chip can be integrated into a single IC device. In the integrated control electronics, shown generically as circuit 400 for a CD-ROM drive, DS
P421, EFM demodulator 422, interface control unit 433, and DRAM address generator 431
Are assumed to have substantially the same or similar functions as their respective counterparts in the electronics of the conventional CD-ROM drive of FIG.

As shown in the drawing, the CIRC processor 5
00 differs from the CIRC decoder 123 in the control electronics of a conventional CD-ROM drive, essentially by the fact that the conventional internal SRAM 124 has been removed. In the embodiment described here, the CIRC processor 5
00 is the same memory that other functional units of the signal decoder (FIG. 1) access for operation, ie, DRAM 4
Share 40. In this case, the decoder unit 123 in the conventional read access controller 120 is eliminated.

As in the case of the conventional CD-ROM drive shown in FIG. 1, the embodiment of FIG. 4 has outstanding characteristics. In the embodiment described in the present invention, the CD-ROM drive originally has a separate CIRC decoder unit 123 and RSPC decoder 132 in the read access controller 120 and the signal controller 130, respectively, which The same RS decoding engine 432 is shared. CIRC and RSPC codes are basically R
Because of the S code, sharing the same RS decode engine can simplify the control electronics.

As described above, the read access controller 120 and the signal decoder 130 in the conventional CD-ROM drive are simply integrated into a single IC chip without appropriate design adjustments and improvements. If the external DRA used in the circuit configuration of FIG.
The M440 must have a very high access speed to avoid the above-mentioned data flow obstruction. In particular, for modern 10X (10X) or higher speed CD-ROM drives, the DRAM 440 used must operate at 100% or higher access speed to meet demand.

In contrast, in the preferred embodiment of the present invention, the circuit of FIG. 4 employs a CIRC processor 500 and an RSPC processor to reduce the frequency of access to the external DRAM.
A new configuration is used for both the / EDC processor 600. The amount of reduction in the frequency of access to the DRAM memory device can be at a reasonable level for a high-speed spindle type CD-ROM drive. With the novel configuration of the present invention, a DRAM with a normal access speed can be used for this purpose. The following section shows how this is achieved.

FIG. 5 shows a circuit configuration of the CIRC processor 500 in the main control electronic circuit of the CD-ROM drive constructed according to the preferred embodiment of the present invention. As shown, the data is EFM demodulator 422 one bit at a time.
To the CIRC processor 500. The received data first has a C1 having a 32 × 9 × 3 bit configuration.
Stored in buffer 501. This buffer 501
Are provided for use in deinterleaving C1. When the serial input data is accumulated in C1 buffer 501 to form a complete C1 data frame, C1
The 32 bytes of data in the data frame are then relayed to the syndrome generator 504.

The syndrome generator 504 then generates four syndrome values S1, S2, S based on the input data.
3. Generate S4. After receiving these four syndrome values and confirming the position of the delete bit in this particular data frame, the RS decode engine 432 can find the position of the error and the error value contained therein. These pieces of information are then relayed to the error corrector 503 of the CIRC processor 500. Based on the data relayed by RS decode engine 432, error corrector 503 corrects the erroneous data in C1 buffer 501 and sends the corrected data to DRAM 440 for subsequent C2 deinterleaving and RS decoding. Store.

The buffer is not suitable for processing because the depth of the C2 interleave extends over 108 layers representing a very large amount of data. As a result, at a point after C1 and before C2, the data still needs to be held in DRAM 440. On the other hand, at the point in time after the identification of C2 and before output, the output buffer 502 is still used to temporarily hold data because there are only two interlibrary layers. This is DRA
Avoid read / write access to M.

When the data is being processed in the C2 stage of the RS decoding, the processing up to the stage of sending the data to the RSPC / EDC processor 600 is as follows. First, C
Two data are retrieved from the external DRAM 440. on the other hand,
Each data is stored in the output buffer 502 as a temporary storage location. At the same time, as with the recording of the delete location, the data is also transferred to the syndrome generator 504 to generate a syndrome value, which allows the RS decode engine 432 to decode the (28, 24) RS code. You. The position where the error has occurred and the value of the error are sent back to the error corrector 503. Thus, RSPC / E
Each data sent to the DC processor 600 does not need to be retrieved from the DRAM. Rather, uncorrected data is
The data is read directly from the data output buffer 502 for correction by the error corrector 503 and the corrected data is processed by the RPSC / EDC processor 600 for further processing.
Sent to

The size of the storage space of the C1 buffer 501 and the data output buffer 502 is determined by the IEC 90 shown in FIG.
It is determined based on the CIRC rules outlined in the 8 standards. FIG. 2 schematically shows an outline of a processing flow in the CIRC decoding algorithm. As can be observed, in the processing of the CIRC decoding algorithm,
There is one interleaving layer between the data input and the C1 decode, so two data frames are required. In other words, one complete set of data supplied to the C1 decoder can be obtained only if all other data frames are present. When one frame of data is added to the EFM demodulator 422 for buffering input data, a total of three frames of data, that is, 32 × 9 × 3 =
864 bytes (or 32 × 8 × 3 = 768 bytes if the delete bit is excluded).

As in the case of the C1 buffer, there are two interleaving layers between the C2 decoder and the data output according to the IEC 908 standard outlined in FIG. In other words, before one complete data frame is obtained for processing in the RSPC / EDC processor 600, each of the other two
That is, there is one data frame. However, since the data of the C2 decoder is controllable,
With one buffer, there is little need to add extra data frames for the buffer. On the other hand, the output 24
The bytes of data need to be stored in the data output buffer (the input data to the C2 decoder is 28 bytes), so the size of the data output buffer is 24 × 9 ×
3 = 648 bytes.

As a result, the total number of accesses to the external DRAM 440 by the CIRC processor 500 is (9
Eight data frames (as a basis for the calculation) are determined by: 1. Decode C1 and write the identified result to DRAM: 98 frames × 28 bytes / frame = 2,744 bytes. 2. Retrieve data from DRAM and perform C2 decoding: 98 frames × 28 bytes / frame = 2,744 bytes. Thus, the total number of accesses is 5,488. 2,744 + 2,744 = 5,488.

FIG. 6 shows the circuit configuration of the RSPC / EDC processor in the main control electronic circuit of the CD-ROM drive constructed according to the preferred embodiment of the present invention. As shown, each data sent by the CIRC processor 500 is converted into two other electronic functional units, a P and Q syndrome generator 601 and an EDC generator, in the RSPC / EDC processor 600 of FIG. And at the same time as the external DRAM 440.

The P and Q syndrome values generated in the P and Q syndrome generator 601 are stored in a P syndrome buffer 602 and a Q syndrome buffer 603, respectively. The stored syndrome values are used to update the data held in these two buffers. The P syndrome buffer 603 is a buffer of 43 × 2 × 2 × 2 × 8 bytes, while the Q syndrome buffer 602 is a buffer of 26 × 2 × 2 × 2 bytes.
× 8-byte buffer. On the other hand, the EDC generator 60
5, the corresponding error detection code is ISO / IEC 101
It can be generated according to the T.49 standard. In view of the relationship between these two functional units, the function of the external DRAM 440 provides a data storage space that allows the execution of a data correction operation. In addition, the DRAM storage space in the control electronics of a typical CD-ROM drive can be used to provide cache space to improve overall data throughput characteristics.

Next, the Q syndrome buffer 602
The Q syndrome data organized into 26 × 2 is relayed to the RS decoding engine 432 so that the RS decoding is performed. The decoded result is relayed to the P syndrome corrector 604 for P syndrome correction.
The decoded result is also sent to EDC modifier 606 so that the EDC is modified. The decoded result is further sent to an error corrector 607 where the data stored in the DRAM 440 is corrected.

Once the Q syndrome value has been decrypted and the P syndrome buffer 603 has updated its contents,
The P syndrome buffer 603 transfers the P syndrome organized into 43 × 2 to an RS decode engine 432 for decoding an RS code. The result of this decoding is further sent to an error corrector 607 which corrects the data stored in the DRAM 440.

The size of the storage space of the Q syndrome buffer 602 and the P syndrome buffer 603 is determined first based on the data storage space required for storing two blocks of the Q and P syndrome values. In other words, when one data block is being decoded, the buffer space is sufficient to receive and hold the entire other data block. This is a means for maintaining a continuous flow of data in pipeline processing. FIG. 3 schematically shows P and Q subcodes at the time of CIRC encoding. According to FIG. 3, the Q syndrome value has 26 sets of (45, 43) RS code for both MSB and LSB. On the other hand, since the RS syndrome value includes two syndrome values, the storage space for the Q syndrome buffer 602 has a memory size of 1,664 bytes. 26 × 2 × 2 × 2 × 8 = 1,664.

However, in one data block, the P syndrome is 43 bits for both the MSB and the LSB.
The storage space for the P syndrome buffer 603 has a memory size of 2,752 bytes since it has a set of (26,24) RS codes, and in the case of the Q syndrome, each RS code has two syndrome values. . 43 × 2 × 2 × 2 × 8 = 2,752.

If the P and Q syndromes are CIRC
If extracted directly from the data sent by the processor 500, or if the P syndrome is updated directly from the error locations and values obtained from the Q syndrome,
Then the relationship between the P and Q positions in each input data can be obtained at the first position.

Referring to FIG. 3, n is an integer and represents the n-th data in the drawing. (NP, MP) represents the MPth data of the NPth set of P RSs. Similarly, (NQ, MQ) represents the MQth data of the NQth set of Q RSs. Thus, n,
The relationship between (NP, MP) and (NQ, MQ) is that if n≤1,117,

[0061]

(Equation 1)

[0062]

(Equation 2)

If n> 1,117

[0064]

(Equation 3)

Thus, based on equations (1) and (2), the corresponding (NP, MP) and (NQ, MQ) have n ≦
1,117. Further, equation (3)
(NQ, MQ) is determined for n> 1,117 based on For the RS code of P, the syndrome is

[0066]

(Equation 4)

Is as follows. Here, R (Np, i) is (NP, i)
Corresponding to the data. For the RS code of Q, the syndrome is

[0068]

(Equation 5)

When each data is sent to the RSPC / EDC processor 600 by the CIRC processor 500, the equation (4)
The P and Q syndromes are updated immediately based on (5).

When a set of Q RS codes is decoded,
Equation (2) is used to obtain (NP, MP) corresponding to the detected error, using P syndrome corrector 604.
Updates the corresponding syndrome held in the P syndrome buffer 603.

For example, if an error E occurs in (NPE, MPE), equation (4) is used to update the P syndrome as follows.

[0072]

(Equation 6)

The principle of operation of the EDC corrector 606 is similar to that of the P syndrome corrector. That is, when P or Q decodes one error, equations (1) and (2)
Is used to get N added by either the MSB or the LSB during processing. This is the ED
This is for positioning the map in C so that the EDC value can be corrected.

When the main control electronics for a CD-ROM drive using a combined and unitized DRAM configuration according to the present invention shown in FIGS. RSPC / ED which is one function unit
For the C processor 600, read / write accesses within the external DRAM 440 fall into three types.

The first type of memory access is the CIR
It is related to writing data of the C processor 500 to the external DRAM 440. This type of operation only requires that 2,048 bytes of data relayed on the IDE / ATA / SCSI bus of the CD-ROM drive be written to the DRAM 440.

The second type of memory access involves correcting RS code error data for the P subcode. Since each (26, 24) RS code has a capability of correcting one error, it is required to perform not only writing of corrected data but also reading operation when executing correction of one erroneous data. If external DR
Two accesses to the AM are required. CD-R
According to the OM drive standard, a total of 2
Since there are * 43 sets of RS codes, there are a total of 172 accesses in the memory for processing one block data as a whole. 2 × 43 × 2 = 172.

The third memory access involves correcting error data of the RS code for the Q subcode. Since each (45, 43) RS code has the ability to correct one error, it is required to perform not only writing of corrected data but also reading operation when executing correction of one erroneous data. In this case, two accesses to the external DRAM are required. Due to the fact that each data block contains a total of 2.times.26 sets of RS codes for the Q subcode, there will be a total of 104 accesses in memory. 2 × 26 × 2 = 104.

Thus, when an entire data block is considered, the sum of the three types of memory access operations described above is the total number of accesses introduced into the external DRAM of the RSPC / EDC processor. This sum is 2,32
Equivalent to 4 accesses. 2,048 + 104 + 172 = 2,324. For a complete data block, the interface controller 433 may control the IDE / ATA /
Reads 2,048 bytes of data on the SCSI bus.

Thus, in the embodiment shown in FIG. 4, the CIRC processor 500 has its external connection DRAM 4
A total of 5,488 accesses to 40 are performed. On the other hand, an RSPC / EDC processor 600
Will result in a total of 2,324 accesses. However, the interface controller 433 accesses this DRAM 2,048 times. As a result, a total of 9,860 accesses are performed in the DRAM for the control electronic circuit of the CD-ROM drive using the configuration of the present invention. 5,488 + 2,324 + 2,048 = 9,860.

[0080]

The total access frequency of the control electronics of the present invention is, by comparison, much lower than that required by conventional devices. This significantly improves the performance characteristics of the overall system. However, the SRAM built in the CIRC decoder in the conventional example is removed, and therefore, the IRC
The assembly cost of the C device is reduced.

Thus, the above items are intended to cover various modifications and alterations included within the spirit and scope of the appended claims. Should be interpreted in the broadest sense to encompass similar arrangements and modifications.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a main control electronic circuit in a conventional CD-ROM drive in which a read access controller and a signal decoder, which are two main functional units, are separated and implemented as a plurality of independent IC chips. FIG.

FIG. 2 is a diagram schematically showing a CIRC decoding algorithm.

FIG. 3 is a diagram schematically showing P and Q subcodes at the time of CIRC encoding.

FIG. 4 is a block diagram showing a circuit configuration of a main control electronic circuit in a CD-ROM drive constituted by a preferred embodiment of the present invention in which a main functional unit is realized as a single IC chip.

FIG. 5 shows a CIR in a main control electronic circuit of a CD-ROM drive constructed according to a preferred embodiment of the present invention.
FIG. 3 is a diagram illustrating a circuit configuration of a C processor.

FIG. 6 shows an RSP in a main control electronic circuit of a CD-ROM drive constructed according to a preferred embodiment of the present invention.
It is a figure showing the circuit composition of a C / EDC processor.

Claims (20)

(57) [Claims] 1. A circuit device for controlling a CD-ROM drive for storing digital data, capable of reading and decoding data stored on a CD-ROM disk and transferring the data to a host computer system via a bus interface. Controlling a spindle motor and a laser pickup head of the CD-ROM disc to read data stored on the surface of the CD-ROM disc, and receiving a signal representing the read data transmitted by a radio frequency (RF) amplifier. A digital signal processor (DSP) to perform the EFM demodulation to obtain an 8 to 14 modulation (EFM) code; an EFM code demodulator receiving the data output of the high frequency amplifier; To perform decoding of a Solomon (CIRC) code, the E A CIRC code processor that receives the output of the M demodulator; a Reed-Solomon code decoding engine; and a Reed-Solomon generator that receives the output of the CIRC processor and the Reed-Solomon code decoding engine to perform error detection and correction. A code / error detection and correction (RSPC / EDC) processor; and relays the digital data finally decoded by the control circuit device of the CD-ROM drive to the bus interface for transmission to the host computer system. A Reed-Solomon code decoding engine, for performing decoding of the Reed-Solomon code.
In a control circuit device for a CD-ROM drive which receives an output of the processor and the RSPC / EDC processor, the CIRC processor and the RSPC / EDC processor work together with the bus interface controller. Control circuit for a CD-ROM drive, which is directly coupled to the working memory device of the CD-ROM drive so that the memory space of the storage memory device can be directly accessed separately and independently. apparatus. 2. The control system according to claim 1, wherein said working memory device is a single memory device used as a memory storage space for decoding processing data and performing error detection and correction. Circuit device. 3. The working memory device is a memory device which is physically disposed outside the control circuit device and is used as a memory storage space for decoding processing data and executing error detection and correction. 2. The control circuit device according to claim 1, wherein: 4. The control circuit device according to claim 3, wherein said working memory device is a DRAM. 5. The control circuit device according to claim 1, wherein said control circuit device is assembled in a single integrated circuit device. 6. The control circuit device according to claim 4, wherein said control circuit device is assembled in a single integrated circuit device. 7. The control circuit device according to claim 1, wherein said CD-ROM drive reads a formatted CD-ROM disk. 8. The control circuit device according to claim 6, wherein said CD-ROM drive reads a formatted CD-ROM disk. 9. The control circuit device according to claim 1, wherein the CD-ROM drive has a bus interface. 10. The CD-ROM drive having a bus interface.
Control circuit device. 11. The CD-ROM drive according to claim 1, wherein the CD-ROM drive has a bus interface.
Control circuit device. 12. The CD-ROM drive according to claim 8, wherein said CD-ROM drive has a bus interface.
Control circuit device. 13. A circuit device for controlling a CD-ROM drive for storing digital data, capable of reading and decoding data stored on a formatted CD-ROM disk and transferring the data to a host computer system via a bus interface. A Reinterpolated Reed-Solomon (CIRC) code processor, a Reed-Solomon code decoding engine, and a Reed-Solomon generated code / error detection and correction (RSPC / ED).
C) a processor and a bus interface controller, wherein the CIRC processor and the RSPC / EDC processor are directly coupled together and can directly access a memory space of a working memory device. Control circuit device for a CD-ROM drive. 14. The control according to claim 13, wherein said working memory device is a single memory device used as a memory storage space for decoding processing data and performing error detection and correction. Circuit device. 15. The working memory device is a memory device which is physically disposed outside the control circuit device and is used as a memory storage space for decoding processing data and executing error detection and correction. 14. The control circuit device according to claim 13, wherein: 16. The working memory device is a DRAM
The control circuit device according to claim 15, wherein: 17. The control circuit device according to claim 13, wherein said control circuit device is assembled in a single integrated circuit device.
Control circuit device. 18. The control circuit device according to claim 16, wherein said control circuit device is assembled in a single integrated circuit device.
Control circuit device. 19. The CD-ROM drive according to claim 1, wherein the CD-ROM drive has a bus interface.
3 control circuit device. 20. The CD-ROM drive according to claim 1, wherein the CD-ROM drive has a bus interface.
3 control circuit device.