JP3314165B2 - Method of making a conductive lateral connection between two wiring layers on a substrate - Google Patents

Method of making a conductive lateral connection between two wiring layers on a substrate

Info

Publication number
JP3314165B2
JP3314165B2 JP2000508140A JP2000508140A JP3314165B2 JP 3314165 B2 JP3314165 B2 JP 3314165B2 JP 2000508140 A JP2000508140 A JP 2000508140A JP 2000508140 A JP2000508140 A JP 2000508140A JP 3314165 B2 JP3314165 B2 JP 3314165B2
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JP
Japan
Prior art keywords
substrate
teeth
metallization
polymer
injection molding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000508140A
Other languages
Japanese (ja)
Other versions
JP2001514450A (en
Inventor
ヘールマン マルセル
ファン プイムブレック ヨーゼフ
Original Assignee
シーメンス ソシエテ アノニム
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Application filed by シーメンス ソシエテ アノニム filed Critical シーメンス ソシエテ アノニム
Publication of JP2001514450A publication Critical patent/JP2001514450A/en
Application granted granted Critical
Publication of JP3314165B2 publication Critical patent/JP3314165B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B29—WORKING OF PLASTICS; WORKING OF SUBSTANCES IN A PLASTIC STATE IN GENERAL
    • B29L—INDEXING SCHEME ASSOCIATED WITH SUBCLASS B29C, RELATING TO PARTICULAR ARTICLES
    • B29L2031/00—Other particular articles
    • B29L2031/34—Electrical apparatus, e.g. sparking plugs or parts thereof
    • B29L2031/3493—Moulded interconnect devices, i.e. moulded articles provided with integrated circuit traces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0284—Details of three-dimensional rigid printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09118—Moulded substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】集積回路は常に接続部の数が増大してお
り、この場合常に一層小型化されてきた。この小型化の
進捗に伴い予期されるろうペーストの付着及び装備にお
ける困難は、新しいケーシング形状によって取り除か
れ、その際ここでは特に、ボール・グリッド・アレイ・
パッケージにおける単チップ、数チップ又は多チップの
モジュールを強調することができる（DE-Z productroni
c 5，1994，54，55 ページ）。これらのモジュールは貫
通接点接続せしめられる基板に基づくものであって、こ
の基板上では、チップが例えば接点接続ワイヤを介し
て、あるいはフリップチップ組立によって、接点接続さ
れている。基板の下面にはボール・グリッド・アレイ
（ＢＧＡ）があり、これはしばしばソルダー・グリッド
・アレイ、ランド・グリッド・アレイあるいはソルダー
・バンプ・アレイとも呼ばれる。ボール・グリッド・ア
レイは基板の下面上に扁平に配置されたろう接突起を包
含しており、このろう接突起は、導体プレートあるいは
構造群上での表面組立を可能にする。ろう接突起の扁平
な配置によって、例えば１．２７ｍｍの粗いラスタにお
ける大きな接続部の数を実現することができる。[0001] Integrated circuits are constantly increasing in the number of connections, in which case they have always been smaller. The difficulties in solder paste deposition and equipment expected with the progress of this miniaturization are eliminated by the new casing shape, in which the ball grid array
Highlight single-, multi- or multi-chip modules in a package (DE-Z productroni
c 5, 1994, 54, 55). These modules are based on a substrate to which through-contacts are made, on which the chips are connected, for example via contact connection wires or by flip-chip assembly. On the underside of the substrate is a ball grid array (BGA), often referred to as a solder grid array, land grid array or solder bump array. The ball grid array includes brazing projections that are flatly arranged on the lower surface of the substrate, and that allow for surface assembly on a conductor plate or structure. The flat arrangement of the brazing projections makes it possible to realize a large number of connections in a rough raster of, for example, 1.27 mm.

【０００２】いわゆるＭＩＤ技術（ＭＩＤ＝Moulded In
terconnection Devices）では、従来のプリント回路の
代わりに、一体の導体列を有する射出成形部品が使用さ
れる。三次元の基板の射出成形に適している高価値の熱
可塑性プラスチックはこの技術のベースである。このよ
うな熱可塑性プラスチックは、プリント回路用の従来の
基板材料に比べて、機械的、化学的、電気的及び環境技
術的な性質が優れている。ＭＩＤ技術の特別な方向であ
るいわゆるＳＩＬ技術（ＳＩＬ＝Spritzgiessteile mit
integrierten Leiterzuegen）においては、射出成形部
品上に取り付けられた金属層の構造化は、ほかの場合に
は普通であるマスク技術を放棄して、特別なレーザ構造
化法によって行われる。この場合構造化された金属被覆
を有する三次元の射出成形部品内に、複数の機械的かつ
電気的な機能が内蔵可能である。ケーシング支持機能は
同時に案内及びスナップ結合部が受け持つのに対し、金
属被覆層は配線機能及び接続機能のほかに、電磁遮へい
も行い、良好に熱を排出する。射出成形部品の互いに逆
の側の表面における２つの配線層の間の導電性の横接続
部を製作するために、既に射出成形の際に相応する貫通
接点接続孔が生ぜしめられる。次いでこれらの貫通接点
接続孔の内壁は、射出成形部品の金属被覆の際にやはり
金属層で被われる。一体の導体列を有する三次元の射出
成形部品の製作の更なる詳細については、例えば DE-A-
37 32 249 あるいは EP-A-0 361 192 から分かる。The so-called MID technology (MID = Moulded In)
In terconnection devices, injection molded parts having an integral conductor row are used instead of conventional printed circuits. High value thermoplastics suitable for injection molding of three-dimensional substrates are the basis of this technology. Such thermoplastics have superior mechanical, chemical, electrical and environmental properties compared to conventional substrate materials for printed circuits. The so-called SIL technology (SIL = Spritzgiessteile mit) which is a special direction of MID technology
In the case of integrierten Leiterzuegen, the structuring of the metal layer mounted on the injection-molded part is performed by a special laser structuring method, abandoning the mask technique which is otherwise usual. In this case, a plurality of mechanical and electrical functions can be built into a three-dimensional injection-molded part having a structured metallization. The casing support function is simultaneously provided by the guide and the snap connection, whereas the metallization layer provides electromagnetic shielding in addition to the wiring function and the connection function, and satisfactorily dissipates heat. In order to produce a conductive cross-connection between the two wiring layers on the opposite surfaces of the injection-molded part, corresponding through-contact holes are already produced during injection molding. The inner walls of these through-contact holes are then also covered with a metal layer during the metallization of the injection-molded part. For further details on the production of three-dimensional injection-moulded parts with integral conductor rows, see for example DE-A-
37 32 249 or EP-A-0 361 192.

【０００３】 EP-A-0 645 953 から公知のＭＩＤ技術の
変化形では、射出成形で製作されモジュールを備えてい
る基板上で順次に第１の導体平面、誘電体層及び第２の
導体平面が生ぜしめられ、次いで凹所内に電気的な構造
部材が入れられ、構造部材の接続部が基板上の所属の接
続面と有利にはボンディングによって導電性に接続さ
れ、次いで凹所をプラスチックで満たすことによって構
造部材が密封される。これにより大きな配線密度を有す
るコンパクトな、薄い構造体が生ずる。射出成形された
基板の凹所内に構造エレメントを沈めて取り付け、カプ
セル化することによって、厚さが減少せしめられるほか
に、構造エレメント及びその接続配線の光学的な保護が
達成される。[0003] A variant of the MID technology known from EP-A-0 645 953 is a method in which a first conductor plane, a dielectric layer and a second conductor plane are successively arranged on a substrate provided by injection molding and having a module. The electrical component is then placed in the recess, the connection of the component is electrically connected to the associated connection surface on the substrate, preferably by bonding, and then the recess is filled with plastic. This seals the structural member. This results in a compact, thin structure with a high wiring density. By submerging and encapsulating the structural element in the recess of the injection-molded substrate, optical protection of the structural element and its connecting wires is achieved in addition to reducing the thickness.

【０００４】 WO-A-96 096 46 から、いわゆるポリマー
・スタッド・グリッド・アレイ（ＰＳＧＡ）が公知であ
り、これはボール・グリッド・アレイ（ＢＧＡ）の利点
とＭＩＤ技術の利点とをまとめるものである。この場合
新しい構造形のポリマー・スタッド・グリッド・アレイ
（ＰＳＧＡ）としての呼称はボール・グリッド・アレイ
（ＢＧＡ）にならって行われており、その際「ポリマー
・スタッド」の概念は、基板の射出成形の際に一緒に形
成されるポリマー突起を表すものである。この、数チッ
プ又は多チップのモジュールに適した新しい構造形は、 − 電気絶縁性のポリマーから成る射出成形された三次
元の基板と、 − 基板の下面上に扁平に配置され、射出成形の際に一
緒に形成されるポリマー突起と、 − ポリマー突起上に、ろう接可能な端部表面によって
形成される外部接続部と、 − 基板上に配置されていて、その接続部を内部接続部
に導電性に接続されているチップと、 を包含している。[0004] From WO-A-96 096 46 a so-called polymer stud grid array (PSGA) is known, which summarizes the advantages of a ball grid array (BGA) and of MID technology. is there. In this case, the new structure of the polymer stud grid array (PSGA) has been named after the ball grid array (BGA), where the concept of "polymer stud" is based on the injection of the substrate. It represents a polymer projection formed together during molding. This new configuration suitable for multi-chip or multi-chip modules includes:-an injection-molded three-dimensional substrate made of an electrically insulating polymer; and-a flat arrangement on the underside of the substrate, -An external connection formed by a brazeable end surface on the polymer projection;-an electrical connection disposed on the substrate and conducting the connection to the internal connection. And a chip connected to the sex.

【０００５】ポリマー突起の、基板の射出成形の際の簡
単で安価な製作のほかに、ポリマー突起上の外部接続部
の製作も、ＭＩＤ技術若しくはＳＩＬ技術の場合に普通
の導体列の製作と一緒に行うことができる。ＳＩＬ技術
において有用なレーザ精密構造化によって、ポリマー突
起上の外部接続部は大きな接続部数をもって極めて細か
いラスタで実現することができる。更に強調すべきこと
は、ポリマー突起の温度膨張が基板の温度膨張及びモジ
ュールを受容する導体プレートの温度膨張と等しいこと
である。機械的な応力が生ずる場合には、ポリマー突起
はその弾性的な性質によって少なくとも部分的な補償を
可能にする。ポリマー突起上に形成された外部接続部の
形状安定性によって、修理及び交換の場合の安全性も、
ろう接突起によって形成される接続部を有しているボー
ル・グリッド・アレイに対して著しく増大せしめられ
る。ポリマー・スタッド・グリッド・アレイにおいて
は、ポリマー突起と単数又は複数のチップとは普通は基
板の同じ側に配置されている。貫通接点接続が行われる
基板においては、ポリマー突起及び単数又は複数のチッ
プは基板の互いに異なった側に配置しておくこともでき
る。このようにポリマー突起とチップとを基板の互いに
異なった側に配置することは、特に、多数の所属の外部
接続部を必要とする大型のチップの場合に興味あること
である。In addition to the simple and inexpensive production of polymer projections during the injection molding of substrates, the production of external connections on the polymer projections is the same as the production of ordinary conductor rows in the case of MID or SIL technology. Can be done. With laser precision structuring useful in SIL technology, external connections on polymer protrusions can be realized with very fine rasters with a large number of connections. It should be further emphasized that the temperature expansion of the polymer protrusions is equal to the temperature expansion of the substrate and of the conductor plate receiving the module. When mechanical stresses occur, the polymer projections allow at least partial compensation by their elastic nature. Due to the shape stability of the external connection formed on the polymer protrusion, safety in the case of repair and replacement,
This is significantly increased for ball grid arrays having connections formed by brazing projections. In a polymer stud grid array, the polymer protrusions and the chip or chips are usually located on the same side of the substrate. In the substrate where the through contact connection is made, the polymer protrusions and the chip or chips may be located on different sides of the substrate. This arrangement of polymer protrusions and chips on different sides of the substrate is of particular interest for large chips that require a large number of associated external connections.

【０００６】 WO-A-89 00346 から、表面取り付けに適
した単チップモジュールが公知であり、これは、貫通接
点接続孔を有する射出成形された三次元の基板をベース
としている。これらの貫通接点接続孔のほかに、基板は
射出成形の際に、表面中央に配置された１つの凹所と、
１つ又は２つの周辺列で下面上に配置された多数のポリ
マー突起とを形成される。上面上で凹所内に配置された
チップは細い接点接続ワイヤで、条片形に外方に導かれ
ている所属の導体路に接続される。これらの導体路は次
いで外側の範囲に配置されている貫通接点接続部を介し
て表面を金属被覆されている所属のポリマー突起に導電
性に接続されている。次いで基板の縁範囲が貫通接点接
続部の中心を通る切断線で切断されると、半円形の横断
面を有する導電性の横接続部が生じ、これらの横接続部
は、基板の上面上に配置された導体路の外方端部を基板
の下面上に配置されたポリマー突起に導電性に接続す
る。[0006] From WO-A-89 00346 a single-chip module suitable for surface mounting is known, which is based on an injection-molded three-dimensional substrate with through-contact holes. In addition to these through contact connection holes, the substrate is provided with one recess arranged in the center of the surface during injection molding,
One or two peripheral rows are formed with a number of polymer protrusions disposed on the lower surface. The chip, which is arranged in the recess on the upper surface, is connected with a thin contact connecting wire to an associated conductor track which is guided outward in a strip form. These conductor tracks are then conductively connected to the corresponding polymer projections whose surface is metallized via through-contact connections arranged in the outer area. If the edge area of the substrate is then cut with a cutting line passing through the center of the through-contact connection, conductive cross-connections having a semicircular cross-section are produced, these cross-connections being located on the upper surface of the substrate The outer ends of the arranged conductor tracks are conductively connected to polymer protrusions arranged on the lower surface of the substrate.

【０００７】請求項１に記載した発明の根底をなす課題
は、ＭＩＤ技術において、射出成形された基板の上面及
び下面上の２つの配線層の間の導電性の横接続部の製作
を簡単にすることである。この場合横接続部は特に、先
に説明したポリマー・スタッド・グリッド・アレイに対
しても適しているようにする。An object underlying the invention as defined in claim 1 is that in MID technology, the manufacture of a conductive lateral connection between two wiring layers on the upper and lower surfaces of an injection-molded substrate is simplified. It is to be. In this case, the lateral connections are particularly suitable for the polymer stud grid array described above.

【０００８】本発明により達成される利点は特に、従来
の金属被覆された孔を有する貫通接点接続技術に比べ
て、横接続部のより大きな確実性を有する著しく細かい
構造を実現し得ることである。基板の外方に向かって開
いている歯は、細い貫通接点接続孔の内壁と異なって、
極めて良好な層厚分布で金属被覆することができる。こ
の場合、歯の範囲内で金属被覆を少なくとも部分的に取
り除くことによって、金属被覆を個々の横接続部に構造
化することは、単にわずかな費用しか必要としない。[0008] The advantage achieved by the present invention is, in particular, that a significantly finer structure with greater certainty of the lateral connection can be realized as compared to the conventional through contact connection technology with metallized holes. . The teeth that open toward the outside of the board are different from the inner walls of the narrow through-contact connection holes,
Metallization can be achieved with a very good layer thickness distribution. In this case, structuring the metallization into individual cross-connects by at least partially removing the metallization within the teeth only requires very little expense.

【０００９】本発明による方法の有利な実施形態は請求
項２から９に記載されている。方法の特に有利な適用は
請求項１０に記載されている。[0009] Advantageous embodiments of the method according to the invention are described in claims 2 to 9. A particularly advantageous application of the method is defined in claim 10.

【００１０】請求項２に記載した実施形態は、射出成形
の際に歯の特に細かい構造化を可能にする。The embodiment according to claim 2 allows a particularly fine structuring of the teeth during injection molding.

【００１１】請求項３に記載した実施形態は、本発明に
よる横接続部をポリマー・スタッド・グリッド・アレイ
に適用することを可能にする。この場合強調すべきこと
は、歯及び単数又は複数のポリマー突起を射出成形の際
に同じ工程で生ぜしめることができることである。An embodiment according to claim 3 makes it possible to apply the lateral connection according to the invention to a polymer stud grid array. It should be emphasized here that the teeth and the polymer projection (s) can be produced in the same step during injection molding.

【００１２】請求項４に記載した実施形態は、金属被覆
を取り付ける際に、プリント回路の製作の際に長いこと
実証されて来た技術を使用することができるという利点
を有している。The embodiment according to claim 4 has the advantage that the technique which has been proven for a long time in the production of printed circuits can be used for applying the metallization.

【００１３】本発明による方法は原則的には半加算的技
術でも実施することができるけれども、請求項５に記載
した減算的技術はかなりの利点をもたらす。所望の導体
模様を簡単かつ経済的に生ぜしめるほかに、ここで特に
レーザ精密構造化の可能性を強調すべきである。レーザ
精密構造化は従来の高価な写真平版を断念して、三次元
の基板においても細かい構造を生ぜしめることを可能に
する。請求項６によれば抗腐食層はこの場合簡単な形式
で錫又は錫- 鉛の電気めっきによって取り付けることが
でき、次いでレーザ光線で加工することによって構造化
することができる。Although the method according to the invention can in principle also be implemented with a half-additive technique, the subtractive technique according to claim 5 offers considerable advantages. In addition to simply and economically producing the desired conductor pattern, the possibility of laser precision structuring should be emphasized here. Laser precision structuring allows to abandon conventional expensive photolithography and to produce fine structures even on three-dimensional substrates. According to claim 6, the anti-corrosion layer can be applied in a simple manner by electroplating tin or tin-lead, and can then be structured by machining with a laser beam.

【００１４】請求項７に記載した実施形態は、横接続部
を生ぜしめるための特に簡単かつ確実な金属被覆の機械
的な構造化を可能にする。特にこの、基板の端面の範囲
における機械的な構造化は、請求項８によれば歯の研削
によって、あるいは請求項９によれば歯の切断によっ
て、特に迅速かつ簡単に実施することができる。The embodiment described in claim 7 allows a particularly simple and reliable mechanical structuring of the metallization for producing the transverse connection. In particular, this mechanical structuring in the region of the end faces of the substrate can be carried out particularly quickly and simply by grinding the teeth according to claim 8 or by cutting the teeth according to claim 9.

【００１５】請求項１０によれば本発明による方法は、
基板の上面上に配置されたチップを有するポリマー・ス
タッド・グリッド・アレイの製作に特に適している。基
板の上面上にチップを配置し、基板の下面上に突起若し
くはポリマー・スタッドを配置することによって、ここ
で、アレイの寸法が大体においてチップの寸法に等しい
いわゆるチップ・スケール・パッケージを実現するため
の理想的な前提が生じる。According to claim 10, the method according to the invention comprises:
It is particularly suitable for fabricating polymer stud grid arrays having chips located on top of a substrate. By placing the chip on the upper surface of the substrate and the protrusions or polymer studs on the lower surface of the substrate, here to realize a so-called chip-scale package where the dimensions of the array are approximately equal to the dimensions of the chip The ideal assumption arises.

【００１６】本発明の１実施例は図面に示されており、
以下においてより詳細に説明する。One embodiment of the present invention is shown in the drawings,
This will be described in more detail below.

【００１７】図１によれば、出発点となる基板Ｓは、外
側の端面の範囲に互いに等間隔で配置された多数の歯Ｚ
を有している。歯Ｚ及び図７に関連して後述する突起Ｈ
を含めた基板の製作は射出成形によって行われ、その際
基板材料としてはポリエチルイミド、ポリエーテルスル
フォンあるいはポリアミドのような耐高温性の熱可塑性
プラスチックが適している。図２の三次元の描写は、歯
Ｚが平らな基面を有する波プロフィールの形に構成され
ていて、基板Ｓの上面Ｏと下面Ｕとの間で延びているこ
とを示している。図示の実施例では上面Ｏと下面Ｕとは
互いに平行に構成されており、換言すれば、もちろん基
板Ｓのほかの３つの端面にも一体に形成しておくことが
できる全ての歯Ｚは同じ長さである。図３に示すよう
に、歯Ｚは原理的には基板Ｓの切り欠きＡの範囲におい
ても、切り欠きＡの端面に一体に形成しておくことがで
きる。ここに図示した長方形の切り欠きＡのほかに、例
えば円形又は長孔状の形状のようなほかの形状も適して
いることができる。According to FIG. 1, a starting substrate S comprises a large number of teeth Z equally spaced from one another in the region of the outer end face.
have. The tooth Z and a projection H described later with reference to FIG.
Is manufactured by injection molding, and a high-temperature-resistant thermoplastic such as polyethylimide, polyethersulfone, or polyamide is suitable as the substrate material. The three-dimensional depiction of FIG. 2 shows that the teeth Z are configured in the form of a wave profile with a flat base surface and extend between the upper surface O and the lower surface U of the substrate S. In the illustrated embodiment, the upper surface O and the lower surface U are configured parallel to each other, in other words, of course, all the teeth Z that can be integrally formed on the other three end surfaces of the substrate S are the same. Length. As shown in FIG. 3, the teeth Z can be formed integrally with the end face of the notch A in principle even in the range of the notch A of the substrate S. In addition to the rectangular cutouts A shown here, other shapes such as, for example, circular or slotted shapes may also be suitable.

【００１８】射出成形で製作された基板Ｓはまず一連の
普通の前処理、特に浸漬、清浄化、核形成及び形成核の
活性化を施される。次いで図４に示すように、化学的銅
析出及び引き続く銅の電気めっきによって、金属被覆Ｍ
が基板Ｓの全面に取り付けられる。次いで化学的な錫析
出によって、あるいは錫の電気メッキによって、抗腐食
層ＡＲが金属被覆Ｍ上に取り付けられる。図４において
はここで興味のある基板の端面側の範囲だけしか示され
ていないが、金属被覆Ｍも、また抗腐食層ＡＲも、基板
Ｓ全面を被覆していることを指摘しておく。The substrate S produced by injection molding is first subjected to a series of conventional pretreatments, in particular immersion, cleaning, nucleation and activation of nuclei. Then, as shown in FIG. 4, metallization M by chemical copper deposition and subsequent electroplating of copper.
Is attached to the entire surface of the substrate S. The anti-corrosion layer AR is then applied to the metallization M by chemical tin deposition or by electroplating of tin. In FIG. 4, only the area of the end face side of the substrate of interest is shown here, but it should be pointed out that both the metal coating M and the anti-corrosion layer AR cover the entire surface of the substrate S.

【００１９】抗腐食層ＡＲを取り付けた後に、図５に示
すように、基板の上面Ｏ及び下面Ｕ（図２参照）上の金
属被覆Ｍの構造化が行われる。ここに示した実施例で
は、形成すべき配線層の所望の導体模様に相応していな
いすべての範囲において、抗腐食層ＡＲがレーザ光線に
よって再び取り除かれる。このようなレーザ構造化の更
なる細部については、例えば DE-A-37 32 249 から分か
る。次いで金属被覆Ｍの保護されていない範囲が腐食に
よって基板Ｓの表面まで除去される。図５から分かるよ
うに、この構造化過程によって基板Ｓの両面に導体路Ｌ
が生じ、これらの導体路はそれぞれ２つの歯Ｚの間で基
板Ｓの縁に向かって延びている。図５に示した分離線Ｔ
は、単に導体路Ｌを有する表面の金属被覆Ｍと端面側の
金属被覆Ｍとを区別するものに過ぎない。しかしながら
実際には金属被覆Ｍはなんら分離されることなしに、基
板Ｓ上で延びている。After the application of the anti-corrosion layer AR, the structuring of the metal coating M on the upper surface O and the lower surface U (see FIG. 2) of the substrate takes place, as shown in FIG. In the embodiment shown here, the anti-corrosion layer AR is again removed by the laser beam in all areas which do not correspond to the desired conductor pattern of the wiring layer to be formed. Further details of such laser structuring can be found, for example, in DE-A-37 32 249. The unprotected area of the metallization M is then removed by corrosion to the surface of the substrate S. As can be seen from FIG. 5, the structuring process allows conductor tracks L on both sides of substrate S.
And these conductor tracks each extend between the two teeth Z towards the edge of the substrate S. Separation line T shown in FIG.
Merely distinguishes the metallization M on the surface having the conductor path L from the metallization M on the end face. However, in practice, the metallization M extends on the substrate S without any separation.

【００２０】基板Ｓの上面Ｏ及び下面Ｕ（図２参照）上
に配線層がこのようにして形成された後に、歯Ｚが研削
あるいはまた切断によって除去される。図６によればこ
れによって、それまでの歯間隙の端面側の範囲に、互い
に電気絶縁された横接続部Ｑが生じる。After the wiring layer is thus formed on the upper surface O and the lower surface U (see FIG. 2) of the substrate S, the teeth Z are removed by grinding or cutting. According to FIG. 6, this results in lateral connections Q which are electrically insulated from one another in the region of the end face of the tooth gap up to that point.

【００２１】図７は、導体路Ｌと、横接続部Ｑと、下面
Ｕ上に扁平に配置されている既に述べた突起Ｈとを有す
る基板Ｓの側面図を示す。基板Ｓの上面Ｏ上にはチップ
Ｃが取り付けられており、このチップの接点接続は、左
側に示したワイヤボンディング技術ではボンディングワ
イヤＢにより、あるいは右側に示したフリップ・チップ
技術では接続部Ａにより行われる。ワイヤボンディング
技術ではチップＣは接着層Ｋを介して基板Ｓの上面Ｏと
接続されている。FIG. 7 shows a side view of a substrate S having a conductor track L, a lateral connection Q, and the above-mentioned projections H which are arranged flat on the lower surface U. A chip C is mounted on the upper surface O of the substrate S, and the contact connection of this chip is made by a bonding wire B in the wire bonding technique shown on the left or by a connecting portion A in the flip chip technique shown on the right. Done. In the wire bonding technique, the chip C is connected to the upper surface O of the substrate S via an adhesive layer K.

【００２２】図７から明りょうに分かるように、チップ
Ｃの個々の接続部は上面Ｏ上の導体路Ｌを介して、端面
側の横接続部Ｑを介してかつ下面Ｕ上の導体路Ｌを介し
て、所属の突起Ｈと導電性に接続されている。金属被覆
された突起Ｈ上には、ろう接可能な端部表面Ｅが設けら
れており、この端部表面は例えばニッケル及び金の層列
によって形成される。As can be clearly seen in FIG. 7, the individual connections of the chip C are provided via the conductors L on the upper surface O, via the lateral connections Q on the end face and on the lower surface U. Are electrically conductively connected to the associated projection H. On the metallized projections H, a solderable end surface E is provided, which is formed, for example, by a layer sequence of nickel and gold.

【００２３】図７に示した構成体は全体としてＰＳＧＡ
で示したポリマー・スタッド・グリッド・アレイであ
る。このようなポリマー・スタッド・グリッド・アレイ
の更なる詳細は例えば WO-A-96 09646 から明らかであ
る。The structure shown in FIG.
2 is a polymer stud grid array shown in FIG. Further details of such a polymer stud grid array are evident, for example, from WO-A-96 09646.

【００２４】図７に示したポリマー・スタッド・グリッ
ド・アレイ ＰＳＧＡにおいては、チップＣ及び基板Ｓ
の外寸法はほぼ同じ大きさである。したがってこれは、
チップ・スケール・パッケージと呼ばれるケーシング形
状である。更に明確に分かるように、端面側の横接続部
Ｑはその高度の製造精密性により、ポリマー・スタッド
・グリッド・アレイ ＰＳＧＡ全体の極めてコンパクト
な構成を可能にし、ひいてはチップ・スケール・パッケ
ージの実現に大きく寄与する。 ［図面の簡単な説明］In the polymer stud grid array PSGA shown in FIG. 7, a chip C and a substrate S
Are approximately the same size. So this is
It has a casing shape called a chip scale package. As can be more clearly seen, the lateral connection Q on the end face, due to its high degree of manufacturing precision, allows a very compact construction of the entire polymer stud grid array PSGA and thus the realization of a chip scale package. Contribute greatly. [Brief description of drawings]

【図１】外側の端面側の範囲に歯を一体に成形されてい
る基板の部分的平面図である。FIG. 1 is a partial plan view of a substrate in which teeth are integrally formed in a region on an outer end face side.

【図２】図１に示した歯を三次元的に示した図である。FIG. 2 is a view three-dimensionally showing the teeth shown in FIG. 1;

【図３】基板の切り欠きの範囲内に歯を一体に成形され
ている基板の部分的平面図である。FIG. 3 is a partial plan view of a substrate having teeth integrally formed within the notch of the substrate.

【図４】金属被覆及び抗腐食層を取り付けた後の図１に
示した基板の部分的平面図である。FIG. 4 is a partial plan view of the substrate shown in FIG. 1 after applying a metal coating and an anti-corrosion layer.

【図５】レーザ構造化した後の図４に示した基板の部分
的平面図である。FIG. 5 is a partial plan view of the substrate shown in FIG. 4 after laser structuring.

【図６】横接続部を形成するために歯を研削した後の図
４に示した基板の部分的平面図である。FIG. 6 is a partial plan view of the substrate shown in FIG. 4 after grinding teeth to form a lateral connection.

【図７】ポリマー・スタッド・グリッド・アレイとして
構成された基板の側面図である。FIG. 7 is a side view of a substrate configured as a polymer stud grid array.

【符号の説明】[Explanation of symbols]

Ａ 切り欠き、接続部、 ＡＲ 抗腐食層、 Ｂ ボン
ディングワイヤ、 Ｃ チップ、 Ｅ 端部表面、 Ｈ
突起、 Ｋ 接着層、 Ｌ 導体路、 Ｍ 金属被覆
Ｏ 上面、 ＰＳＧＡ ポリマー・スタッド・グリッ
ド・アレイ、 Ｑ 横接続部、 Ｓ 基板、 Ｔ 分離
線、 Ｕ 下面、 Ｚ 歯A Notch, connection, AR anti-corrosion layer, B bonding wire, C chip, E end surface, H
Projection, K adhesive layer, L conductor track, M metallized O top surface, PSGA polymer stud grid array, Q lateral connection, S substrate, T separation line, U bottom surface, Z tooth

フロントページの続き (56)参考文献 特開 平５−55399（ＪＰ，Ａ) 特開 平６−349979（ＪＰ，Ａ) 特開 平８−32183（ＪＰ，Ａ) 実表 平10−511873（ＪＰ，Ｕ) 実表 平10−512402（ＪＰ，Ｕ) 実表 平11−502064（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 21/60 Continuation of the front page (56) References JP-A-5-55399 (JP, A) JP-A-6-349979 (JP, A) JP-A-8-32183 (JP, A) Table 10-511873 (JP) , U) Base table 10-512402 (JP, U) Base table 11-502064 (JP, U) (58) Fields studied (Int. Cl. 7 , DB name) H01L 23/12 H01L 21/60

Claims (10)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 基板（Ｓ）の上面（Ｏ）及び下面（Ｅ）
上の２つの配線層の間の導電性の横接続部（Ｑ）を製作
する方法であって、次の段階： ａ） 電気絶縁性のプラスチックから基板（Ｓ）を射出
成形で製作すること、その際基板（Ｓ）の外側の端面範
囲内で、及び又は基板（Ｓ）の切り欠き（Ａ）の範囲内
で、互いに間隔をおいて配置され上面（Ｏ）と下面
（Ｅ）との間で延びている複数の一体的な歯（Ｚ）が射
出成形の際に一緒に成形される； ｂ） 基板（Ｓ）上に金属被覆（Ｍ）を全面にわたって
取り付けること； ｃ） 少なくとも、所望の導体模様に境を接する範囲に
おいてかつ歯（Ｚ）の端面側の範囲において、金属被覆
（Ｍ）を取り除いて、歯（Ｚ）の間に互いに電気絶縁さ
れた横接続部（Ｑ）が生じるようにすること； を有している、基板上の２つの配線層の間の導電性の横
接続部を製作する方法。1. An upper surface (O) and a lower surface (E) of a substrate (S).
A method for producing a conductive lateral connection (Q) between two upper wiring layers, comprising the following steps: a) Injection molding a substrate (S) from electrically insulating plastic; The upper surface (O) and the lower surface (E) are spaced apart from each other within the outer end surface area of the substrate (S) and / or within the notch (A) of the substrate (S). A plurality of integral teeth (Z) extending together during injection molding; b) mounting a metallization (M) over the substrate (S) over the entire surface; c) at least the desired The metal coating (M) is removed in the area bordering the conductor pattern and in the area of the end faces of the teeth (Z) so that transversely electrically connected parts (Q) are formed between the teeth (Z). A conductive lateral connection between two wiring layers on a substrate, comprising: How to make a. 【請求項２】 段階ａ）において、基板（Ｓ）の射出成
形の際に、波プロフィール状に歯（Ｚ）を形成すること
を特徴とする、請求項１記載の方法。2. The method according to claim 1, wherein in step a), during injection molding of the substrate, the teeth are formed in a wave profile. 【請求項３】 段階ａ）において、基板（Ｓ）の射出成
形の際に、基板の下面（Ｅ）上に扁平に配置されたポリ
マー突起（Ｈ）を一緒に形成し、金属被覆（Ｍ）を取り
付けた後に、ろう接可能な端部表面（Ｅ）をポリマー突
起（Ｈ）上に取り付けることを特徴とする、請求項１又
は２記載の方法。3. In step a), during the injection molding of the substrate (S), flatly arranged polymer projections (H) are formed together on the lower surface (E) of the substrate, and the metallization (M) 3. The method according to claim 1, wherein after mounting, the solderable end surface (E) is mounted on the polymer protrusions (H). 【請求項４】 金属被覆（Ｍ）を、銅の化学的析出及び
電気メッキによって、基板（Ｓ）上に取り付けることを
特徴とする、請求項１から３までのいずれか１項記載の
方法。4. The method according to claim 1, wherein the metallization is applied to the substrate by chemical deposition of copper and electroplating. 【請求項５】 段階ｂ）の後に、抗腐食層（ＡＲ）を金
属被覆上に取り付け、抗腐食層（ＡＲ）を、少なくとも
所望の導体模様に境を接する範囲においてレーザ光線に
よって再び取り除き、次いで金属被覆（Ｍ）の露出して
いる部分を基板（Ｓ）の表面まで腐食除去することを特
徴とする、請求項１から４までのいずれか１項記載の方
法。5. After step b), an anti-corrosion layer (AR) is applied on the metallization, and the anti-corrosion layer (AR) is removed again by means of a laser beam, at least in the region bordering the desired conductor pattern, 5. The method according to claim 1, wherein the exposed portions of the metallization (M) are etched off to the surface of the substrate (S). 【請求項６】 抗腐食層（ＡＲ）を、錫又は錫- 鉛の電
気めっきによって、取り付けることを特徴とする、請求
項５記載の方法。6. The method according to claim 5, wherein the anti-corrosion layer (AR) is applied by tin or tin-lead electroplating. 【請求項７】 歯（Ｚ）の端面側の範囲の金属被覆
（Ｍ）を機械的に取り除くことを特徴とする、請求項１
から６までのいずれか１項記載の方法。7. The method as claimed in claim 1, wherein the metal coating (M) in the region of the end faces of the teeth (Z) is mechanically removed.
7. The method according to any one of claims 1 to 6. 【請求項８】 歯（Ｚ）の端面側の範囲の金属被覆
（Ｍ）を、歯（Ｚ）の研削によって取り除くことを特徴
とする、請求項７記載の方法。8. The method according to claim 7, wherein the metallization (M) in the region of the end faces of the teeth (Z) is removed by grinding the teeth (Z). 【請求項９】 歯（Ｚ）の端面側の範囲の金属被覆
（Ｍ）を、歯（Ｚ）の切断によって取り除くことを特徴
とする、請求項７記載の方法。9. The method according to claim 7, wherein the metallization (M) in the region of the end faces of the teeth (Z) is removed by cutting the teeth (Z). 【請求項１０】 基板（Ｓ）の上面上にワイヤボンディ
ング技術あるいはフリップ・チップ技術で配置されたチ
ップを有しているポリマー・スタッド・グリッド・アレ
イ（ＰＳＧＡ）を製作する際に、請求項３から９までの
いずれか１項記載の方法を適用すること。10. When fabricating a polymer stud grid array (PSGA) having chips arranged on the upper surface of a substrate (S) by wire bonding or flip chip technology. Applying the method described in any one of the above items 9 to 9.
JP2000508140A 1997-08-22 1998-08-18 Method of making a conductive lateral connection between two wiring layers on a substrate Expired - Fee Related JP3314165B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19736654.6 1997-08-22
DE19736654 1997-08-22
PCT/EP1998/005251 WO1999010926A1 (en) 1997-08-22 1998-08-18 Method for producing electrically conductive cross connections between two layers of wiring on a substrate

Publications (2)

Publication Number Publication Date
JP2001514450A JP2001514450A (en) 2001-09-11
JP3314165B2 true JP3314165B2 (en) 2002-08-12

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JP (1) JP3314165B2 (en)
KR (1) KR100334373B1 (en)
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WO (1) WO1999010926A1 (en)

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DE10145348C1 (en) * 2001-09-14 2003-03-27 Siemens Dematic Ag Intermediate carrier for electronic component has suction used for removal of excess solder at foot of contact projections formed integral with plastics carrier body
DE10250621B4 (en) * 2002-10-30 2004-09-02 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. A method of producing encapsulated chips and generating a stack of the encapsulated chips
CN101815409B (en) * 2010-04-23 2012-05-02 陈国富 Method for manufacturing circuit board through injection molding
JP5720278B2 (en) * 2011-02-07 2015-05-20 ソニー株式会社 Conductive element and manufacturing method thereof, information input device, display device, and electronic apparatus

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WO1999010926A1 (en) 1999-03-04
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TW411741B (en) 2000-11-11
KR20010023051A (en) 2001-03-26

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