JP3311227B2 - Memory address output circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for outputting address signals to a ROM and a DRAM in a computer system or the like.

[0002]

2. Description of the Related Art In general, computer systems such as personal computers and printers mainly include a microprocessor (hereinafter abbreviated as CPU), ROM, RAM and I / O.
/ O etc. In recent years, since a large-capacity memory is required for a system, a DRAM is generally used as a RAM. ROM, RAM, I
Control circuits for / O and the like are often configured by ASICs.

On the other hand, the CPU has a bus width (AD bus) that multiplexes an address bus and a data bus and uses them in a time-division manner in order to increase the bus width for improving the performance and to reduce the number of pins of the IC. Is becoming more common.

In the case where the CPU has an AD bus configuration, in order to generate an address signal of a memory such as a ROM or a DRAM, a control circuit configured as an ASIC requires a processing time of a bus cycle of the CPU. It is necessary to temporarily latch address information output on the AD bus.

[0005]

However, with the increase in the capacity of the memory, a large number of address signals to the memory are required. Therefore, the ASIC for outputting the address signal has to use a large number of pins. . This has hindered the miniaturization and price reduction of the printed circuit boards constituting the system.

When an additional DRAM is added,
Since the load of the address signal of the DRAM becomes heavy, it is necessary to prepare an output buffer having a large driving ability.
This has been a factor of increasing unnecessary noise such as radiation noise.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is possible to minimize the number of output pins required for outputting an address signal to a memory and to make the load of the address signal uniform even when a memory is added. It is intended to provide an address output circuit to a memory.

[0008]

In order to achieve the above object, the present invention focuses on the fact that the number of address signals is small because the address signals to the DRAM are multiplexed of row addresses and column addresses. It has the following configuration.

Address for latching input address
A latch unit, and an address latched by the address latch unit.
The upper and lower of the address are two inputs and the two inputs are
A first selection signal for outputting one of them according to a first selection signal.
And an address latched by the address latch unit.
The upper and lower parts of are two inputs and one of the two inputs
A second selector for outputting the shift in response to a second selection signal
And the address latched by the address latch unit.
If the memory block shown is a ROM,
The address higher order from the first selection unit and the address higher order from the second selection unit
The lower address is output in parallel, and the memory block
In the case of AM, the address from the first selector is
Output the upper and lower parts of the memory block in chronological order
Is an additional DRAM, the second selection unit
Output the upper and lower parts of the address in chronological order.
And a control unit.

[0010]

FIG. 1 is a drawing showing the features of the present invention best, and an embodiment according to the present invention will be described in detail with reference to the drawings.

In FIG. 1, 1 is a ROM, 2 and 3 are D
Reference numeral 3 denotes a RAM, particularly a DRAM for extension. 4 is an address control unit. Reference numeral 5 denotes an AD bus of a CPU (not shown), and reference numerals 6 and 9 denote control signals from the CPU, which are input to the address control unit 4. The address information output on the AD bus 5 by the control signal 6 is latched by the address control unit 4. The latched address information is divided into address signals 7 and 8 in the ROM.
1 and output to the DRAMs 2 and 3. The lower side of the divided address information is the address signal 7, which is connected to the address input of the DRAM 2 and the lower address input of the ROM 1, and the upper side of the divided address information is the address signal 8, which is the address input of the additional DRAM 3. And R
Connected to the upper address input of OM1. In this way, by dividing and outputting the latched address signal to different blocks of the DRAM, it can be shared with the address signal of the ROM, and the number of pins of the address signal to the memory in the ASIC can be reduced. be able to.

FIG. 2 is a block diagram showing the configuration of the address control unit 4 in FIG. 2, reference numeral 201 denotes an address latch unit, 202 denotes a control unit, and 203 and 204 denote Ds.
A selector for switching between a row address and a column address when accessing the RAM. The address information on the AD bus 5 is latched in the address latch unit 1 by the address latch signal 6 of the CPU, and the address signals 214 to 216
And output. The address signal 214 is the uppermost part of the latched address information, and is input to the control unit 202. The control signal 9 is output from the CPU and is output according to the bus cycle of the CPU.

The address signals 215 and 216 are the upper and lower parts of the divided address information,
And 204 are connected to the inputs. The control unit 202 outputs signals 219 and 220 at a predetermined timing according to the bus cycle of the CPU based on the address signal 214 and the control signal 9. The memory device has a top address signal 214
Therefore, whether to control as a ROM or as a DRAM is determined according to the value of the signal 214. Therefore, if the bus cycle is an address output by the signal 9, the address signal is controlled according to the type of the device that can be determined by the signal 214 as described later.

Signals 219 and 220 are connected to select inputs of selectors 3 and 4, respectively. The output signal 17 of the selector 3 and the output signal 18 of the selector 4 are R in FIG.
OM1 is an address input for the DRAMs 2 and 3.

The operation of address output will be described below with reference to the configuration of FIG. 2 and the timing of FIG.

The CPU outputs address information to the AD bus 5 and operates control signals 6 and 9. As a result, the address information is latched in the address latch unit 1. When the access from the CPU is the ROM (which can be determined by the upper address signal 214), the control unit 202 sets the output signals 219 and 220 to the “L” level, and the selectors 203 and 204 output the A input side. Therefore, in this case, the upper address 215 and the lower address 216 of the latched address are output as output signals 7 and 8, respectively.

On the other hand, when the access from the CPU is a DRAM, the operation is different. First, in the case of accessing the DRAM 2 (which can be determined by the highest address 214), only the signal 8 is required as the address signal to the DRAM 2, and the signal 219 is set to the "L" level and the signal 220 is set to the "H".
Level, and the signal 215 on the upper side of the latched address signal is output from the signal 8 as a DRAM row address (timing T1 in FIG. 3). Next, the signal 220 is set to "L" level at a predetermined timing, and the lower address signal 216 is output from the signal 8 as a column address (timing T2). As a result, the upper side is output to the DRAM 2 as a row address and the lower side is output as a column address. Since the address output signal 7 to the DRAM 3 is Don't Care, the level of the signal 219 may be either.

Next, the access from the CPU is changed to the DR on the extension side.
If it is AM3, first, the signals 219 and 220 are set to the "L" level (timing T3), and the signal 219 is set to the "H" level at a predetermined timing thereafter (timing T4). As a result, the address signal of the DRAM 3 is output on the upper side as a row address and on the lower side as a column address, as in the case of the DRAM 2 described above.

Although the above embodiment has been described on the assumption that the number of address signals to the ROM can be divided into 22 and the number of address signals to the DRAM can be divided exactly 11, the number of these signals can be changed depending on the configuration of the ROM, DRAM and the like. However, in that case, the appropriate combination may be changed.

The ROM and the DRAM may be constituted by a plurality of ICs such as modules. Furthermore, ROM
Instead, an SRAM, flash memory, or the like may be used.

[0021]

As described above, in the memory address output circuit according to the present invention, the number of address output pins to the memory can be reduced, and the size and cost of the device can be reduced.

Further, even if the DRAM is added, the load of the address signal does not become heavy, and a buffer having a high driving capability is not required for driving the bus.

[0023]

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory address output circuit according to an embodiment.

FIG. 2 is a block diagram illustrating a configuration of an address control unit according to the embodiment.

FIG. 3 is a timing chart of an address control signal of the DRAM in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ROM 2 DRAM 3 DRAM (expansion part) 4 Address control part

Claims (1)

(57) [Claims] An address for latching an input address is provided.
A latch unit, and a high-order address latched by the address latch unit.
And the lower input are two inputs, and one of the two inputs is
A first selection unit that outputs in response to a first selection signal; and a higher-order address latched by the address latch unit.
And the lower input are two inputs, and one of the two inputs is
A second selection unit that outputs in response to a second selection signal, and an address latched by the address latch unit.
If the memory block to be read is a ROM, the first
The upper address from the selector is added from the second selector.
Memory block is output in parallel and the memory block is DRAM
In the case of the above, from the first selection unit,
Control to output the order and lower order in time series, and when the memory block is an additional DRAM, to output the upper and lower order of the address in time series from the second selector.
Memory address output circuit, characterized in that it comprises a part.