JP3307970B2 - Inserter and dropper in user / network interface - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inserter and a dropper in a user / network interface such as a primary rate interface.

In an ISDN user / network interface, a D channel data (signal channel data) is inserted into a B channel or H channel data (information channel data) output from a terminal side. An inserter for creating structure data and a dropper for extracting D-channel data from data input from the line side are used.

In order to further increase the speed and bandwidth of the user / network interface, a more multiplexed interface structure has been proposed, and an inserter and a dropper capable of handling data of a large number of signal channels have been proposed to spread the interface structure. Requested.

[0004]

2. Description of the Related Art FIG. 6 is a block diagram showing a conventional inserter and dropper for handling data of a plurality of D channels.

As shown in FIG. 6, conventionally, in order to handle data of a plurality of D channels, a plurality of inserters 81a, 81b, 81c and droppers 83a, 83c are provided.
b, 83c are provided.

The inserters 81a, 81b, 81c are:
Each of them is constituted by a hardware circuit, and is used to insert transmission D-channel data input thereto into a predetermined time slot for each frame.

In each of the inserters 81a, 81b, and 81c, the time slot position at which D-channel data is inserted is determined by hardware, for example, time slots 2, 3, and 4, respectively.

[0008] Droppers 83a, 83b, 83c
Are each configured by a hardware circuit, and are for extracting data of a D channel at a predetermined time slot position of a received signal input thereto for each frame.

In each of the droppers 83a, 83b, 83c, the time slot position at which the data of the D channel is extracted is determined in hardware, for example, time slots 2, 3, and 4, respectively.

The time slot exchange section 82 is for exchanging the time slot positions in advance so that there is no B channel data at the time slot position where the D channel data is inserted by the inserters 81a, 81b and 81c. is there. The time slot exchanging section 84 is for exchanging the time slot positions in advance so that data of a predetermined D channel comes to the time slot positions extracted by the droppers 83a, 83b, 83c.

When data of m B channels is transmitted from the PBX side, each time slot position is adjusted by the time slot exchange section 82, and the inserter 81
According to a, 81b, and 81c, data of a total of n D channels is sequentially inserted into predetermined time slot positions.
As a result, the transmission signal (m
× B channel + n × D channel) is created and transmitted to the line side.

The received signal input from the line side is
Each time slot position is adjusted by the time slot exchange unit 84, and the droppers 83a, 83b, 83
By c, data of the D channel at a predetermined time slot position is sequentially extracted and sent to the PBX side as a data group of the information channel.

[0013]

However, as is apparent from the above description, in the prior art, the number n of inserters 81a, 81b, 81 corresponding to the number n of D-channels is known.
c and the droppers 83a, 83b, 83c were required.

Therefore, as the number of D-channels increases due to the progress of multiplexing, the required number of inserters and droppers increases, which causes a problem that the size of the apparatus and the cost increase.

The conventional inserter and dropper are:
Since the time slot position at which data is inserted or extracted is determined depending on the hardware circuit, the time slot exchange units 82 and 84 are indispensable, and the flexibility of the system is reduced.

The present invention has been made in view of the above problems, and has as its object to provide a low-cost and flexible inserter and dropper capable of inserting or extracting data of a large number of signal channels.

[0017]

According to a first aspect of the present invention, there is provided an inserter for storing data of an information channel, as shown in FIG.
Memory area 33, a second memory area 34 for storing signal channel data, a third memory area 35 for storing frame data constituting one frame, and serially input as a data string. A first memory control means 36 for writing data of an information channel to the first memory area 33; a second memory control means 37 for writing data of a signal channel to the second memory area 34; , The first memory area 33
And a third memory control means 38 for organizing said frame data and transfers the data stored in the second memory area 34 to the third memory area 35, but it
Has two data interchange 21 provided, respectively, and an output unit 24 for outputting the frame data read out from said third memory area 35 as a serial data stream, prior to
One data exchange unit of the two data exchange units 21
21 reading data from the third memory area 35
During data writing, the other data exchange unit 21 writes data.
And knitting .

As shown in FIG. 2, the dropper 15 according to the second aspect of the present invention has a fourth memory area 43 for storing frame data constituting one frame, and a data area for storing signal channel data. Fifth memory area 44
A sixth memory area 45 for storing information channel data, a fourth memory control means 46 for writing frame data serially input as a data string to the fourth memory area 43, Fifth memory control means 47 for transferring signal channel data of the frame data stored in the fourth memory area 43 to the fifth memory area 44; a sixth memory control unit 48 for transferring data information channels of the stored frame data in the memory area 45 of the sixth, but each provided
Has two data interchange 26, the two data exchange
Of the data exchange unit 26 of one of the exchange units 26
Data from the memory area 45 and the fifth memory area 44
During data reading, the other data exchange unit 26
Write data to the fourth memory area 43
It is configured as follows.

[0019]

In the inserter 12, the serially input information channel data is stored in the first memory area 33.
The signal channel data is stored in the second memory area 34.
Are written respectively. These written data are selectively transferred to the third memory area 35 to organize the frame data.

The data read from the third memory area 35 is output from the output unit 24 as a serial data string. In the dropper 15, the serially input frame data is written to the fourth memory area 43. Of the written data, the signal channel data is transferred to the fifth memory area 44, and the information channel data is transferred to the sixth memory area 45.

By reading data from the fifth memory area 44 or the sixth memory area 45, data of the signal channel or the information channel is obtained, respectively.

[0022]

FIG. 3 is a block diagram of an interface device 2 according to the present invention. The interface device 2 has m B
Based on channel data and n D-channel data, a transmission signal ST having an interface structure of (m + n) channels is organized, and the number of channels is (m + n).
It is decomposed into m B-channel data and n D-channel data based on the received signals SR having the three interface structures.

The interface device 2 includes a mixer unit 1 for organizing a transmission signal ST based on data output via HWC (highway control) or the like.
1, inserter 12, and time slot exchange unit 13
And a time slot exchange unit 14, a dropper 15, and a demixer unit 16 for outputting data obtained by decomposing the received signal SR to an HWC or the like.

The mixer section 11 converts n D-channel data sequentially input in parallel into a serial data string. The data of the D channel is, for example, L (not shown).
It is created by P (local processor) or the like.

The inserter 12 synchronizes with the data stream of the B channel output from the time slot
D-channel data serially output from the mixer unit 11 is inserted, and one serial data string is output as a transmission signal ST.

The time slot exchange section 13 is for rearranging the time slot positions in advance with respect to the m B channel data transmitted from the PBX side so that the inserter 12 can easily organize the data. is there.

The time slot exchange section 14 is for rearranging the time slot positions in advance with respect to the data of the D channel included in the received signal SR so that the dropper 15 can easily extract the data. .

The dropper 15 is a time slot exchange unit 1
The data of the D channel is extracted from the serial data string output from 4. The demixer unit 16 includes the dropper 1
5, the serial D channel data string output from
It is for converting into parallel data and outputting it.

FIG. 1 is a block diagram of an inserter 12 according to the present invention. The inserter 12 includes two data exchange units 21, serial / parallel conversion units 22 and 23, and a parallel / serial conversion unit 24. Although two data exchange units 21 are provided, their configurations are the same, and they operate alternately. Therefore, only one of them is illustrated and described.

The data exchange unit 21 includes a memory control unit 31 including a CPU and a ROM in which programs are stored.
And a readable / writable memory 32 such as a DRAM.

The memory 32 stores a first memory area 33 for storing B channel data, a second memory area 34 for storing D channel data, and frame data constituting one frame. A third memory area 35 is provided.

The memory control section 31 has a first memory control section 36 for writing B channel data in the first memory area 33 and a second memory control section 36 for writing D channel data in the second memory area 34. Memory control unit 37, a third memory control for selectively transferring data stored in the first memory area 33 and the second memory area 34 to the third memory area 35 and organizing frame data. A part 38 is provided.

The first to third memory control units 36 to 3
Numerals 8 are each formed functionally by the CPU performing a processing operation according to a program. The serial / parallel converter 22 converts the serial B channel data output from the time slot exchanger 13 into parallel data for each B channel. The serial / parallel converter 23 converts serial D-channel data output from the mixer 11 into parallel data for each D-channel. The parallel-serial conversion unit 24 converts data read in parallel from the third memory area 35 for each time slot into a serial data string.

Next, the first to third memory areas 33 to 35
The operation of the memory control unit 31 will be described with reference to FIG. In the example shown here, the number of time slots in one frame is 32, and each time slot is 8 bits.

The memory controller 31 receives information or commands relating to the interface structure, a clock signal, and the like. Based on the information, the memory controller 31 specifies the address of the memory 32 and performs reading and writing. First to third memory areas 33
To 35 each have a capacity capable of storing 32 pieces of 8-bit data.

First, B-channel data B00 to B31 and D-channel data D00 to D31 for one frame.
Is stored in the first memory area 33 or the second memory area 34, respectively. In this case, data serially output from the serial / parallel converters 22 and 23 are stored in order from the first time slot position of each of the memory areas 33 and 34.

Next, the data of each channel constituting one frame is selectively read from the first memory area 33 or the second memory area 34 and stored in each time slot position of the third memory area 35. Written. by this,
In the third memory area 35, frame data for one frame is organized and stored in order from the first time slot position to the last time slot position.

Next, the data is sequentially read from the first time slot position of the third memory area 35, and the read data is converted into a serial data string by the parallel / serial conversion unit 24 and output as a transmission signal ST. You.

During reading of data from the third memory area 35 of one of the two data exchange units 21, data writing and organization are performed in the other data exchange unit 21. Are performed alternately, so that the parallel-to-serial converter 24 continuously outputs the transmission signal ST.

FIG. 2 is a block diagram of the dropper 15 according to the present invention. The dropper 15 has two data exchange units 2
6, a serial / parallel converter 27 and two parallel / serial converters 28 and 29. Although two data exchange units 26 are provided, as in the case of the data exchange unit 21 described above, their configurations are the same as each other and they operate alternately, so only one of them is used. It is illustrated and described.

The data exchange unit 26 includes a memory control unit 41 including a CPU, a ROM storing programs, and the like.
And a readable / writable memory 42 such as a DRAM.

The memory 42 has a fourth memory area 43 for storing frame data constituting one frame,
A fifth memory area 44 for storing D-channel data and a sixth memory area 45 for storing B-channel data are provided.

The memory control unit 41 includes a fourth memory control unit 46 for writing the frame data output from the serial / parallel conversion unit 27 to the fourth memory area 43,
A fifth memory control unit 47 for transferring D-channel data of the frame data stored in the fourth memory area 43 to the fifth memory area 44, a frame stored in the fourth memory area 43; A sixth memory control unit 48 for transferring data of the B channel among the data to the sixth memory area 45 is provided.

The fourth to sixth memory control units 46 to 4
Numerals 8 are each formed functionally by the CPU performing a processing operation according to a program. The serial / parallel converter 27 converts the data of the received signal SR serially output from the time slot exchanger 14 into parallel data for each time slot. The parallel-to-serial conversion unit 28 reads B from the sixth memory area 45 in parallel for each time slot.
Converts channel data to a serial data string. The parallel-serial converter 29 converts D-channel data read in parallel from the fifth memory area 44 for each time slot into a serial data string.

Next, the fourth to sixth memory areas 43 to 45
The operation of the memory control unit 41 will be described with reference to FIG. The interface structure is the same as in the above-described example, and the fourth to sixth memory areas 43 to 45
Each has a capacity capable of storing 32 pieces of 8-bit data.

First, one frame of frame data is stored in the fourth memory area 43. Next, of the data stored in the fourth memory area 43, the data of the B channel is stored in the sixth memory area 45, and the data of the D channel is stored in the fifth memory area 45.
Are transferred and stored in the memory area 44 of.

Next, the data stored in the sixth memory area 45 and the fifth memory area 44 are sequentially read from the first time slot position, and the read data is read by the parallel / serial conversion section 28. , 29 are converted into serial data strings. As a result, data of the D channel is extracted from the reception signal SR. The extracted data of the D channel is sent for control using HWC or the like, or is processed internally.

While data is being read from the sixth memory area 45 and the fifth memory area 44 of one data exchange section 26, data writing to the fourth memory area 43 is performed by the other data exchange section 26. The received signal SR is continuously processed by performing these operations alternately.

As described above, the inserter 12 performs data organization while inputting the data stream of the B channel and the data stream of the D channel in parallel at the same speed to form the data stream of the transmission signal ST having a predetermined interface structure. create. Also,
The dropper 15 creates two data streams of the same speed of the B channel and the D channel in parallel from one data stream based on the received signal SR.

The above-described interface device 2 can be provided, for example, in an input interface unit of a PBX (private branch exchange) having a function of a network terminal 2 (NT2) specified by ISDN.

According to the above-described embodiment, the memory control unit 3
1, 41 and the memories 32, 42, the insertion and extraction of a large number of multiplexed D-channel data are performed in a software manner. Therefore, even if the number of D-channels increases, the cost is low. In addition, it is possible to prevent an increase in size. In addition, it is possible to easily cope with an increase or decrease in the number of D-channels, and to easily cope with any interface structure by changing a program.

Also, by changing the time slot position (write address or read address) at the time of writing or writing to the memories 32 and 42 or their order, the data of the B channel or D channel can be changed to an arbitrary time. Since it is possible to correspond to the slot position, the time slot exchange units 13 and 14 can be omitted by doing so.

In the above embodiment, the memory control unit 3
Both functions 1 and 41 may be obtained by one CPU. The first to third memory regions 33 to 35 and the fourth to sixth memory regions 43 to 45 can be provided on one or a plurality of memory elements. D channel and B
The number of channels can be set arbitrarily.
The type of the channel can be appropriately selected. The configurations of the inserter 12, the dropper 15, and the interface device 2 can be variously changed in addition to the above.

[0054]

According to the present invention, it is possible to provide a low-cost and flexible inserter or dropper capable of inserting or extracting data of a large number of signal channels.

[Brief description of the drawings]

FIG. 1 is a block diagram of an inserter according to the present invention.

FIG. 2 is a block diagram of a dropper according to the present invention.

FIG. 3 is a block diagram of an interface device according to the present invention.

FIG. 4 is a diagram showing an example of contents of first to third memory areas;

FIG. 5 is a diagram showing an example of contents of fourth to sixth memory areas.

FIG. 6 is a block diagram showing a conventional inserter and dropper for handling data of a plurality of D channels.

[Explanation of symbols]

 12 Inserter 15 Dropper 24 Parallel / Serial Converter (Output) 33 First Memory Area 34 Second Memory Area 35 Third Memory Area 36 First Memory Controller (First Memory Controller) 37 Second Memory controller (second memory controller) 38 Third memory controller (third memory controller) 43 fourth memory area 44 fifth memory area 45 sixth memory area 46 fourth memory control Unit (fourth memory control unit) 47 fifth memory control unit (fifth memory control unit) 48 sixth memory control unit (sixth memory control unit)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-173943 (JP, A) JP-A-1-265646 (JP, A) JP-A-2-244836 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04L 12/02

Claims (2)

(57) [Claims] A first memory area for storing data of claim 1 the information channel, for storing a second memory area for storing data of signal channels, the frame data constituting one frame third memory area of the first memory control hand stage for writing data information channels inputted serially into the first memory area as a data string, the data of the signal channel second second memory control hand stage, the first memory territory Iki及 beauty the second of the data stored in the memory area a third memory for burn them in the memory area in the book <br/> third memory controlling hand stage for organizing said frame data is transferred to the realm
When, but has two data exchange unit provided respectively, and an output unit for outputting the third memory area or al frame data read out as a serial data stream, wherein the two data interchange Of one of the data exchange units
While reading data from the third memory area,
Write and organize data in
Performed, the inserter in the user-network interface, characterized in that. Wherein the fourth memory area for storing frame data constituting one frame, for storing a fifth memory area of for storing data of signal channels, the data of the information channel 6th memory area
Band and a fourth memory control hand stage for writing the frame data inputted as a data string to the serial in the memory area of the fourth, of the frame data stored in the memory area of the fourth wherein the data signal channel fifth memory area of
To transfer <br/> fifth and memory control hand stage, the memory area data of said sixth information channel of the fourth memory area frame data stored in for transfer to a sixth memory control hand stage for, provided but, respectively it
Is having two data exchange unit, the one of the data exchange unit of said two data interchange
From the sixth memory area and the fifth memory area
While reading data, the other data exchange
Data is written into the serial fourth memory area, dropper in the user-network interface, characterized in that.