JP3307256B2 - Mounting method of work with bump - Google Patents
Mounting method of work with bumpInfo
- Publication number
- JP3307256B2 JP3307256B2 JP1086697A JP1086697A JP3307256B2 JP 3307256 B2 JP3307256 B2 JP 3307256B2 JP 1086697 A JP1086697 A JP 1086697A JP 1086697 A JP1086697 A JP 1086697A JP 3307256 B2 JP3307256 B2 JP 3307256B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive paste
- work
- bumps
- substrate
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
Landscapes
- Adhesives Or Adhesive Processes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Wire Bonding (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、バンプ付きワーク
のバンプを基板のパッド上に固着するバンプ付きワーク
の実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a bumped work, which fixes a bump of the bumped work on a pad of a substrate.
【０００２】[0002]
【従来の技術】フリップチップなどのバンプ付きワーク
を基板に実装する方法として、銀ペーストのような導電
性ペーストを用いる方法が知られている。従来の導電性
ペーストは、未硬化状態では導電性を有しておらず、加
熱処理を行って硬化させると導電性を発揮することか
ら、従来は次のようにしてバンプ付きワークを実装して
いた。2. Description of the Related Art As a method for mounting a work with a bump such as a flip chip on a substrate, a method using a conductive paste such as a silver paste is known. Conventional conductive paste does not have conductivity in the uncured state, and exhibits conductivity when cured by heat treatment.Therefore, conventionally, a work with bumps is mounted as follows. Was.
【０００３】すなわち、バンプ付きワークのバンプ若し
くは基板のパッド上に導電性ペーストを付着させた後、
バンプをパッド上に着地させてバンプ付きワークを基板
に搭載する。次に加熱処理を行って導電性ペーストを硬
化させることによりバンプをパッド上に固着する。導電
性ペーストを硬化させたことにより、導電性ペーストは
はじめて導電性を発揮することとなる。そこで基板の検
査用パッドに検査手段のプローブを接触させ、バンプ付
きワークの機能検査を行う。そして検査結果が合格であ
れば、バンプ付きワークと基板の間に必要に応じてアン
ダーフィルを注入した後、再度加熱処理を行ってアンダ
ーフィルを硬化させる。以上により実装は終了する。That is, after a conductive paste is deposited on bumps of a work having bumps or pads of a substrate,
The bump is landed on the pad, and the work with the bump is mounted on the substrate. Next, heat treatment is performed to cure the conductive paste to fix the bumps on the pads. By hardening the conductive paste, the conductive paste will exhibit conductivity for the first time. Then, the probe of the inspection means is brought into contact with the inspection pad of the substrate, and the function inspection of the work with bumps is performed. If the inspection result is acceptable, an underfill is injected between the work with bumps and the substrate as necessary, and a heating process is performed again to cure the underfill. With the above, the implementation is completed.
【０００４】[0004]
【発明が解決しようとする課題】上記検査の結果が不合
格の場合には、バンプ付きワークを基板から取りはずし
てリペアすることが行われる。ところが従来方法は、導
電性ペーストを硬化させた後でなければ上記検査を行え
なかったため、リペア作業を行うには、バンプをパッド
に固着する硬化した導電性ペーストを治具を用いるなど
して剥がさねばならず、リペア作業に多大な手間を要す
るという問題点があった。If the result of the above inspection is rejected, the work with bumps is removed from the substrate and repaired. However, according to the conventional method, the above-described inspection cannot be performed until after the conductive paste is cured.To perform the repair work, the cured conductive paste for fixing the bumps to the pads is peeled off using a jig or the like. However, there is a problem that the repair work requires a great deal of trouble.
【０００５】また上記従来方法では、検査結果が合格で
あれば、アンダーフィルを注入して再度加熱処理を行
い、アンダーフィルを硬化させる場合が多いため、かな
りの時間を要する加熱工程が前後２回必要であって生産
性があがらないだけでなく、バンプ付きワークは２回加
熱されるので熱ダメージを受けやすく、さらにはアンダ
ーフィルを加熱して硬化させる際に、その熱応力のため
に、先にパッドに固着されたバンプがパッドからはがれ
てしまうことがあるという問題点があった。In the above conventional method, if the inspection result is acceptable, the underfill is often injected and heat-treated again to cure the underfill. Not only is it necessary to reduce the productivity, but also the work with bumps is heated twice so that it is susceptible to thermal damage. In addition, there is a problem that the bump fixed to the pad may come off from the pad.
【０００６】したがって本発明は、上記従来方法の問題
点を解消し、バンプ付きワークの機能検査の結果が不合
格の場合には、バンプ付きワークのリペアを容易に行う
ことができるバンプ付きワークの実装方法を提供するこ
とを目的とする。Therefore, the present invention solves the problems of the above-described conventional method, and when the result of the function test of the work with bumps is rejected, the work with bumps can be easily repaired. The purpose is to provide an implementation method.
【０００７】[0007]
【課題を解決するための手段】請求項１記載の発明は、
常温の未硬化状態で導電性を有する導電性ペーストを用
いるバンプ付きワークの実装方法であって、バンプ付き
ワークのバンプを前記導電性ペーストを介して基板のパ
ッド上に付着させてバンプ付きワークを基板に搭載する
工程と、導電性ペーストが未硬化の状態で検査手段によ
りチップの機能検査を行う工程と、前記機能検査で合格
の場合には加熱処理を行って前記導電性ペーストを硬化
させ、前記バンプを前記パッド上に固着する工程と、を
含む。According to the first aspect of the present invention,
A method for mounting a work with bumps using a conductive paste having conductivity in an uncured state at room temperature, wherein the bumps of the work with bumps are attached to pads of a substrate via the conductive paste to form a work with bumps. A step of mounting on a substrate, a step of performing a function test of the chip by a test means in a state where the conductive paste is uncured, and, if the function test passes, performing a heat treatment to cure the conductive paste, Fixing the bump on the pad.
【０００８】請求項２記載の発明は、常温の未硬化状態
で導電性を有する導電性ペーストを用いるバンプ付きワ
ークの実装方法であって、バンプ付きワークのバンプを
前記導電性ペーストを介して基板のパッド上に付着させ
てバンプ付きワークを基板に搭載する工程と、導電性ペ
ーストが未硬化の状態で検査手段によりチップの機能検
査を行う工程と、前記機能検査で合格の場合には前記バ
ンプ付きワークと前記基板の間にアンダーフィルを注入
する工程と、加熱処理を行って前記導電性ペーストと前
記アンダーフィルを共に硬化させ、前記バンプを前記パ
ッド上に固着する工程と、を含む。According to a second aspect of the present invention, there is provided a method of mounting a work with bumps using a conductive paste having conductivity in an uncured state at room temperature, wherein the bumps of the work with bumps are mounted on the substrate via the conductive paste. a step is deposited onto the pad mounting the bumped work on the substrate, a conductive Bae
Performing a function test of the chip by the inspection means in a state where the paste is in an uncured state, a step of injecting an underfill between the work with bumps and the substrate if the function test passes, and performing a heat treatment. Curing the conductive paste and the underfill together to fix the bumps on the pads.
【０００９】[0009]
【発明の実施の形態】請求項１記載の発明は、常温の未
硬化状態で導電性を有する導電性ペーストを用いること
により、導電性ペーストを加熱処理して硬化させる前に
バンプ付きワークの機能検査を行うことが可能となり、
したがって検査結果が不合格の場合でも、バンプ付きワ
ークのリペアを容易に行うことができる。DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 uses a conductive paste having conductivity in an uncured state at room temperature, so that the function of a work with bumps can be improved before the conductive paste is cured by heat treatment. Inspection can be performed,
Therefore, even if the inspection result is rejected, the work with bumps can be easily repaired.
【００１０】請求項２記載の発明は、導電性ペーストと
アンダーフィルを一緒に加熱処理してこれらを硬化させ
ることができ、したがって加熱処理は１回でよいので工
程数を削減して生産性をあげることができ、さらには導
電性ペーストと共にアンダーフィルが硬化することによ
り、熱応力によってバンプがパッドからはがれるのを防
止し、バンプをパッド上に確実に固着することができ
る。According to the second aspect of the present invention, the conductive paste and the underfill can be heat-treated together to cure them, so that only one heat-treatment is required, so that the number of steps is reduced and the productivity is reduced. In addition, by curing the underfill together with the conductive paste, the bump can be prevented from peeling off from the pad due to thermal stress, and the bump can be firmly fixed on the pad.
【００１１】図１、図２、図３、図４、図５、図６、図
７、図８、図９は本発明の一実施の形態のバンプ付きワ
ークの実装工程図であって、実装順に示している。なお
本実施の形態のバンプ付きワークはフリップチップであ
る。以下、図１〜図９を参照してフリップチップの実装
工程を説明する。FIG. 1, FIG. 2, FIG. 3, FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. They are shown in order. The work with bumps in the present embodiment is a flip chip. The flip chip mounting process will be described below with reference to FIGS.
【００１２】図１において、１はフリップチップであ
り、その下面にバンプ２を有している。３は導電性ペー
ストであり、浅い容器４に貯溜されている。導電性ペー
スト３の表面は、スキージ（図示せず）により平滑され
ている。この導電性ペースト３は、未硬化でも導電性を
有するものであり、その詳細は後述する。In FIG. 1, reference numeral 1 denotes a flip chip, which has a bump 2 on its lower surface. Reference numeral 3 denotes a conductive paste, which is stored in a shallow container 4. The surface of conductive paste 3 is smoothed by a squeegee (not shown). The conductive paste 3 has conductivity even when it is not cured, and will be described later in detail.
【００１３】図１〜図３に示すように、フリップチップ
１をノズル５の下端部に真空吸着して保持し、導電性ペ
ーストに対して下降・上昇動作を行わせることにより、
バンプ２の下面に導電性ペースト３を付着させる。As shown in FIGS. 1 to 3, the flip chip 1 is held by vacuum suction at the lower end of the nozzle 5, and the lowering and raising operations are performed on the conductive paste.
The conductive paste 3 is attached to the lower surface of the bump 2.
【００１４】図４において、１０は基板であり、その上
面にはパッド１１と検査用パッド１２が形成されてい
る。パッド１１と検査用パッド１２は配線１３で接続さ
れている。図示するように、ノズル５に保持されたフリ
ップチップ１を基板１０の上方へ移動させ、そこでノズ
ル５を下降させることによりバンプ２をパッド１１上に
着地させ、次いで真空吸着状態を解除してノズル５を上
昇させることにより、フリップチップ１は基板１０に搭
載される。In FIG. 4, reference numeral 10 denotes a substrate, on which pads 11 and test pads 12 are formed. The pad 11 and the inspection pad 12 are connected by a wiring 13. As shown in the figure, the flip chip 1 held by the nozzle 5 is moved above the substrate 10, and the nozzle 5 is lowered there to land the bump 2 on the pad 11. Then, the vacuum suction state is released and the nozzle 5 is released. By raising 5, flip chip 1 is mounted on substrate 10.
【００１５】次に、図５に示すようにフリップチップ１
の機能検査が行われる。この機能検査は、検査手段２０
のプローブ２１を検査用パッド１２に接触させ、フリッ
プチップ１に電流を流すことにより行われる。導電性ペ
ースト３は未硬化であるが、この導電性ペースト３は本
発明のために開発されたものであって未硬化でも導電性
を有する新規なものであり、この検査を行うことができ
る。なお後で図１１を参照して述べるように、実験結果
によれば、この機能検査は、４０℃〜６０℃程度に導電
性ペースト３を暖めて行うと、良い検査結果が得られ
た。その理由は不明である。但し、４０℃〜６０℃程度
では、導電性ペースト３は未硬化状態のままである。Next, as shown in FIG.
Is performed. This function inspection is performed by the inspection unit 20.
This is performed by bringing the probe 21 into contact with the inspection pad 12 and passing a current through the flip chip 1. Although the conductive paste 3 is uncured, the conductive paste 3 has been developed for the present invention and is a new material having conductivity even when uncured, so that this inspection can be performed. As will be described later with reference to FIG. 11, according to the experimental results, a good inspection result was obtained when the conductive paste 3 was warmed to about 40 ° C. to 60 ° C. The reason is unknown. However, at about 40 ° C. to 60 ° C., the conductive paste 3 remains uncured.
【００１６】図６および図７はこの検査結果が合格の場
合を示している。すなわち検査の結果が合格であれば、
図６に示すように注入器３０のニードル３１からアンダ
ーフィル３２を注出し、フリップチップ１と基板１０の
間に注入する。このアンダーフィル３２は熱硬化性の樹
脂である。次に加熱炉（図示せず）内で加熱処理を行っ
て導電性ペースト３とアンダーフィル３２を同時に加熱
することにより、これらを共に硬化させれば実装は終了
する（図７）。FIGS. 6 and 7 show a case where the inspection result is acceptable. In other words, if the result of the inspection passes,
As shown in FIG. 6, the underfill 32 is poured out from the needle 31 of the injector 30 and injected between the flip chip 1 and the substrate 10. The underfill 32 is a thermosetting resin. Next, a heat treatment is performed in a heating furnace (not shown) to simultaneously heat the conductive paste 3 and the underfill 32, thereby curing them together, and the mounting is completed (FIG. 7).
【００１７】このように本方法は、上記検査結果が合格
の場合には、導電性ペースト３とアンダーフィル３２は
同時に加熱処理を行って一緒に硬化させることができ
る。したがって加熱処理は１回で済み、前後２回の加熱
処理が必要であった従来方法よりも工程数を削減して生
産性をあげることができ、またフリップチップ１が受け
る熱ダメージも小さくなる。さらには、アンダーフィル
３２が硬化することにより、熱応力によってバンプ２が
パッド４からはがれるのを防止でき、バンプ２をパッド
４上に確実に固着することができる。As described above, according to the present method, if the above inspection result is acceptable, the conductive paste 3 and the underfill 32 can be simultaneously heated and cured together. Therefore, only one heat treatment is required, the number of steps can be reduced and productivity can be improved as compared with the conventional method which requires two heat treatments before and after, and the heat damage to the flip chip 1 is reduced. Furthermore, by curing the underfill 32, the bump 2 can be prevented from peeling off from the pad 4 due to thermal stress, and the bump 2 can be securely fixed on the pad 4.
【００１８】図８および図９は、上記検査結果が不合格
の場合を示している。この場合、図８に示すようにフリ
ップチップ１を基板１０から取りはずし、次に図９に示
すように基板１０のパッド１１上に残存付着する導電性
ペースト３を拭きとる。図８の工程は、導電性ペースト
３が未硬化の状態で行われるので、フリップチップ１を
難なく基板１０から取りはずし、またパッド１１上の導
電性ペースト３をきれいに拭きとることができる。なお
基板１０は一般に高価であり、導電性ペースト３をきれ
いに拭きとることにより再使用できる。FIGS. 8 and 9 show a case where the above inspection result is rejected. In this case, the flip chip 1 is removed from the substrate 10 as shown in FIG. 8, and then the conductive paste 3 remaining on the pads 11 of the substrate 10 is wiped off as shown in FIG. Since the process of FIG. 8 is performed in a state where the conductive paste 3 has not been cured, the flip chip 1 can be easily removed from the substrate 10 and the conductive paste 3 on the pad 11 can be wiped clean. The substrate 10 is generally expensive and can be reused by wiping the conductive paste 3 clean.
【００１９】次に、未硬化状態で導電性を有する上記導
電性ペースト３について説明する。（表１）は上記導電
性ペースト３の材料および配合比（重量％）を示すもの
である。また（表２）は、硬化しないと導電性を有しな
い従来の導電性ペーストの成分および配合比を示すもの
である。Next, the conductive paste 3 having conductivity in an uncured state will be described. Table 1 shows the materials and the mixing ratio (% by weight) of the conductive paste 3. Table 2 shows the components and the mixing ratio of the conventional conductive paste which does not have conductivity unless cured.
【００２０】[0020]
【表１】 [Table 1]
【００２１】[0021]
【表２】 [Table 2]
【００２２】（表２）において、従来は硬化剤としてジ
シアンジアミド及びイミダゾールを用いていた。これに
対し（表１）に示す本実施の形態の導電性ペーストの硬
化剤は、トリエタノールアミン及びイミダゾールを用い
ている。なお硬化剤としては、一般にアミン系の物質が
用いられる。In Table 2, dicyandiamide and imidazole were conventionally used as curing agents. On the other hand, as the curing agent for the conductive paste of the present embodiment shown in (Table 1), triethanolamine and imidazole are used. In addition, as a curing agent, an amine-based substance is generally used.
【００２３】図１０は、本発明の一実施の形態の測定対
象基板の断面図、図１１は同導電性ペーストの導電性特
性図である。図１０において、パッド１１は銅パッドで
あり、パッド間隔Ｌは６０μｍ、パッドピッチＰは１２
０μｍである。また基板１０はガラエポ基板である。抵
抗計３３によりパッド間の抵抗値を測定した結果を図１
１に示している。FIG. 10 is a sectional view of a substrate to be measured according to an embodiment of the present invention, and FIG. 11 is a view showing the conductive characteristics of the conductive paste. In FIG. 10, a pad 11 is a copper pad, a pad interval L is 60 μm, and a pad pitch P is 12
0 μm. The substrate 10 is a glass epoxy substrate. FIG. 1 shows the result of measuring the resistance value between the pads by the resistance meter 33.
It is shown in FIG.
【００２４】図１１において、ａは（表１）に示す本実
施の形態の導電性ペースト，ｂは（表２）に示す従来の
導電性ペーストの導電性特性をそれぞれ示している。図
１１に示すように、従来の導電性ペーストは１００℃以
下の未硬化状態では抵抗値はきわめて大きく、１００℃
以上に加熱して硬化が始まらないと抵抗値は小さくなら
ない。これに対し本実施の形態の導電性ペーストは低温
（常温）の未硬化状態でも抵抗値は小さく、十分な導電
性を有している。なお図１１に示すように、本実施の形
態の導電性ペーストは、特に４０℃以上で抵抗値がより
小さくなるので、図５に示す検査は、４０〜６０℃程度
で行うことが望ましく、この程度の温度であれば、フリ
ップチップが熱ダメージを受けたり、バンプがパッドか
ら剥がれたりすることはない。In FIG. 11, a shows the conductive property of the conductive paste of the present embodiment shown in (Table 1), and b shows the conductive property of the conventional conductive paste shown in (Table 2). As shown in FIG. 11, the conventional conductive paste has an extremely large resistance value in an uncured state at 100 ° C. or lower,
The resistance value does not decrease unless curing is started by heating as described above. On the other hand, the conductive paste of the present embodiment has a small resistance even in an uncured state at a low temperature (normal temperature) and has sufficient conductivity. As shown in FIG. 11, the resistance of the conductive paste of the present embodiment becomes smaller particularly at 40 ° C. or higher. Therefore, the inspection shown in FIG. 5 is desirably performed at about 40 to 60 ° C. At such temperatures, the flip chip is not thermally damaged and the bumps do not peel off the pads.
【００２５】本発明は上記実施の形態に限定されないの
であって、例えば導電性ペースト３は図２および図３に
示す転写方式でバンプ２に付着させているが、スクリー
ン印刷法により基板１０のパッド１１上に付着させても
よい。The present invention is not limited to the above-described embodiment. For example, the conductive paste 3 is adhered to the bumps 2 by the transfer method shown in FIGS. 11 may be attached.
【００２６】[0026]
【発明の効果】請求項１記載の発明は、常温の未硬化で
導電性を有する導電性ペーストを用いることにより、導
電性ペーストを加熱処理して硬化させる前にバンプ付き
ワークの機能検査を行うことが可能となり、したがって
検査結果が不合格の場合でも、バンプ付きワークのリペ
アを容易に行うことができる。According to the first aspect of the present invention, the use of a conductive paste which is uncured at room temperature and has conductivity allows the functional inspection of the work with bumps before the conductive paste is cured by heating. Therefore, even if the inspection result is rejected, the work with bumps can be easily repaired.
【００２７】請求項２記載の発明は、導電性ペーストと
アンダーフィルを一緒に加熱処理してこれらを硬化させ
ることができ、したがって加熱処理は１回でよいので工
程数を削減して生産性をあげることができ、さらにはア
ンダーフィルが硬化することにより、熱応力によってバ
ンプがパッドからはがれるのを防止し、バンプをパッド
上に確実に固着することができる。According to the second aspect of the present invention, the conductive paste and the underfill can be heat-treated together to cure them, so that only one heat-treatment is required, so that the number of steps is reduced and the productivity is reduced. In addition, by curing the underfill, it is possible to prevent the bump from peeling off from the pad due to thermal stress, and to securely fix the bump on the pad.
【図１】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 1 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図２】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 2 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図３】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 3 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図４】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 4 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図５】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 5 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図６】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 6 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図７】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 7 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図８】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 8 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図９】本発明の一実施の形態のバンプ付きワークの実
装工程図FIG. 9 is a mounting process diagram of a work with bumps according to an embodiment of the present invention.
【図１０】本発明の一実施の形態の測定対象基板の断面
図FIG. 10 is a sectional view of a substrate to be measured according to an embodiment of the present invention.
【図１１】本発明の一実施の形態の導電性ペーストの導
電性特性図FIG. 11 is a diagram showing the conductivity characteristics of a conductive paste according to an embodiment of the present invention.
１ フリップチップ ２ バンプ ３ 導電性ペースト １０ 基板 １１ パッド １２ 検査用パッド ２０ 検査手段 ２１ プローブ ３２ アンダーフィル DESCRIPTION OF SYMBOLS 1 Flip chip 2 Bump 3 Conductive paste 10 Substrate 11 Pad 12 Inspection pad 20 Inspection means 21 Probe 32 Underfill
───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/52 H01L 21/60 H05K 3/32 C09J 9/02 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 21/52 H01L 21/60 H05K 3/32 C09J 9/02
Claims (2)
ペーストを用いるバンプ付きワークの実装方法であっ
て、バンプ付きワークのバンプを前記導電性ペーストを
介して基板のパッド上に付着させてバンプ付きワークを
基板に搭載する工程と、導電性ペーストが未硬化の状態
で検査手段によりチップの機能検査を行う工程と、前記
機能検査で合格の場合には加熱処理を行って前記導電性
ペーストを硬化させ、前記バンプを前記パッド上に固着
する工程と、を含むことを特徴とするバンプ付きワーク
の実装方法。1. A method of mounting a work with bumps using a conductive paste having conductivity in an uncured state at room temperature, wherein a bump of the work with bumps is attached to a pad of a substrate via the conductive paste. The process of mounting the work with bumps on the substrate by pressing, and the conductive paste is in an uncured state
A step of performing a function test of the chip by a test means, and a step of performing a heat treatment to cure the conductive paste if the function test passes, and fixing the bump on the pad. A method for mounting a work with bumps, characterized in that:
ペーストを用いるバンプ付きワークの実装方法であっ
て、バンプ付きワークのバンプを前記導電性ペーストを
介して基板のパッド上に付着させてバンプ付きワークを
基板に搭載する工程と、導電性ペーストが未硬化の状態
で検査手段によりチップの機能検査を行う工程と、前記
機能検査で合格の場合には前記バンプ付きワークと前記
基板の間にアンダーフィルを注入する工程と、加熱処理
を行って前記導電性ペーストと前記アンダーフィルを共
に硬化させ、前記バンプを前記パッド上に固着する工程
と、を含むことを特徴とするバンプ付きワークの実装方
法。2. A method of mounting a work with bumps using a conductive paste having conductivity in an uncured state at room temperature, wherein the bumps of the work with bumps are attached to pads on a substrate via the conductive paste. The process of mounting the work with bumps on the substrate by pressing, and the conductive paste is in an uncured state
A step of performing a chip functional inspection by inspection means, and a step of injecting an underfill between the bumped work and the substrate if the functional inspection passes, and performing a heat treatment on the conductive paste. Curing the underfill together and fixing the bump on the pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1086697A JP3307256B2 (en) | 1997-01-24 | 1997-01-24 | Mounting method of work with bump |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1086697A JP3307256B2 (en) | 1997-01-24 | 1997-01-24 | Mounting method of work with bump |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002059939A Division JP2002353602A (en) | 2002-03-06 | 2002-03-06 | Conductive paste for mounting work with bumps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10209217A JPH10209217A (en) | 1998-08-07 |
| JP3307256B2 true JP3307256B2 (en) | 2002-07-24 |
Family
ID=11762279
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1086697A Expired - Fee Related JP3307256B2 (en) | 1997-01-24 | 1997-01-24 | Mounting method of work with bump |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3307256B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361299C (en) * | 2005-12-21 | 2008-01-09 | 威盛电子股份有限公司 | Packed module with positioning structure, electronic device and inspection after assembly |
| JPWO2021214813A1 (en) * | 2020-04-20 | 2021-10-28 |
-
1997
- 1997-01-24 JP JP1086697A patent/JP3307256B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10209217A (en) | 1998-08-07 |
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