JP3305090B2 - Image display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device, and more particularly to an image display device used for a liquid crystal.

[0002]

2. Description of the Related Art FIG. 23 is a sectional view showing a typical cell structure of a conventional image display device using a liquid crystal. 13, reference numeral 1301 denotes a transparent substrate; 1302, a semiconductor layer forming a transistor for driving a liquid crystal;
Reference numerals 03, 1304, and 1305 denote a drain portion, a source portion, and a gate portion of the transistor, respectively. Drain part 13
03 is in electrical contact with a transparent electrode 1307 (hereinafter, pixel electrode) for applying a voltage to the liquid crystal layer 1306,
An image signal is sent to the source section 1304 by a signal wiring 1308. Reference numeral 1309 denotes an interlayer insulating film. In order to hold the potential given to the pixel electrode 1307 until the next writing period, the wiring 1310 and the drain 130
3, and a storage capacitor is formed.

[0003]

The above structure has the following problems. 1. There is a problem that the potential of the pixel electrode fluctuates due to a change in the potential of the signal and ON / OFF of the gate due to a parasitic capacitance between the signal wiring 1308 and the gate line 1305. Another problem is that the potential of the pixel electrode changes due to transistor leakage. It is effective to increase the storage capacitance in order to further stabilize the potential of the pixel electrode. However, increasing the overlapping area of the wiring 1310 and the pixel electrode decreases the aperture ratio of the display device and increases the display screen. Is dark. 2. As can be seen from FIG.
Reference numeral 06 is provided on the transistor portion 1302 and each wiring, and is provided on a surface having a step. Therefore, the thickness of the liquid crystal layer 1306 varies within the cell, the alignment characteristics of the liquid crystal slightly change, and causes color shift. In addition, rubbing is performed before filling the liquid crystal in order to orient the liquid crystal. However, there is a problem that the rubbing is not performed uniformly due to the influence of the step and the alignment of the liquid crystal is not uniform in each cell. This causes a phenomenon in which, when black is displayed on the cell, the entire cell does not become black but light is partially transmitted, causing a problem that the contrast of the display screen is reduced and the number of gradations is reduced.

An object of the present invention is to solve the above problems and to provide an image display device with high luminance, high gradation and high contrast without impairing the aperture ratio of the display device.

[0005]

According to the present invention, an n-type or a p-type is provided on one surface side of a semiconductor layer or a semiconductor substrate.
Well region and the n-type or p-type well region
Forming a transistor having a formed p-type or n-type source and drain and a wiring thereof, and applying a liquid crystal voltage to a liquid crystal on the other surface side of the semiconductor layer or the semiconductor substrate. electrode is formed, and source of the transistor
Or the drain and the liquid crystal voltage applying electrode are connected to each other through an opening in the semiconductor layer or the semiconductor substrate, and at least a part of a capacitor provided for holding a voltage of the liquid crystal voltage applying electrode is connected to the opening. And an image display device formed on the side wall of the image display device.

Further, an image display device being characterized in that given by wiring the electric potential of the Well.

Further, the present invention relates to an image display device, characterized in that a wiring for fixing the potential of the Well is formed on the other surface side of the semiconductor layer or the semiconductor substrate on the side where the transistor is formed. The present invention relates to an image display device, wherein wiring for fixing the potential of a well is formed so as to shield the transistor from light.

According to the present invention, since the pixel electrode is formed on the side opposite to the side on which the transistor and the wiring are formed, disturbance of the liquid crystal alignment due to a step is eliminated. Further, the fluctuation of the pixel electrode potential due to the signal line and the gate line is reduced. Further, since the drain of the driving transistor and the pixel electrode are connected via the trench groove, and an additional capacitance is provided between the side wall and the semiconductor layer of the transistor portion, there is a problem that the aperture ratio decreases due to the formation of the capacitance. Can be avoided.

[0009]

【Example】

(First Embodiment) FIG. 1 is a sectional view of a cell structure according to a first embodiment of the present invention. In this example, it is a PMOS with silicon
Will be described as an example of a driving transistor.

Reference numeral 101 denotes an n-type silicon layer.
02 is a LOCOS oxide film. A drain 103, a source 104, a low-concentration electric field relaxation layer 105 for improving withstand voltage,
The gate 106 forms a pixel driving transistor. The drain 103 contacts the p ⁺ polysilicon 108 buried inside the oxide film 107 formed in the trench groove, and is connected to the pixel electrode 109. Source 104
Are connected to the signal line 110. The potential of the silicon layer 101 is given by the wiring 111. A passivation film 112 is provided above the transistor, and is bonded to a transparent substrate (eg, glass) 114 with an adhesive 113. A passivation film 11 under the pixel electrode
5 and the liquid crystal layer 116 is interposed between the liquid crystal layer 116 and the counter substrate. The image signal input to the signal line 110 is
The voltage is written to the pixel electrode 109 while the voltage for turning on the transistor is applied to 6, and is held at that potential while the transistor is turned off by the control of the gate 106.

As compared with the conventional example, in this embodiment, the interface between the liquid crystal layer 116 and the device substrate is flat. As a result, there is no influence of the steps at all, the disorder of the liquid crystal alignment is reduced, and color shift and in-plane non-uniformity are eliminated. In addition, a decrease in contrast and a decrease in the number of gradations due to non-uniform rubbing can be suppressed, and a uniform image display device with high gradation and high luminance can be realized. Pixel electrode 10
The potential of No. 9 can be stabilized by the capacitance between the silicon layer 101 and the polysilicon 108, and the influence of transistor leakage and the like can be reduced. However,
In this case, if the potential of the silicon layer 101 fluctuates, the potential of the pixel electrode also fluctuates. Therefore, the potential of the silicon layer 101 needs to be fixed by the wiring 111. Forming the additional capacitor in this manner does not lower the aperture ratio as in the conventional example, but also eliminates the need to newly draw a wiring for forming a capacitor, thereby simplifying the process. Furthermore, since the distance from the pixel electrode to the gate line and signal line that causes the swing becomes longer, and the silicon layer acts as a shield between them, the potential fluctuation of the pixel electrode due to the swing should be reduced. Can be. From these, an image display device having a high aperture ratio, high luminance, high gradation, and high uniformity can be realized. In this embodiment, the additional capacitance is formed by an oxide film capacitance. However, it is also possible to form a junction capacitance by burying polysilicon without oxidizing the side wall of the trench.

Although there is no description about the light-shielding layer in FIG. 1, it goes without saying that light may be shielded by using Al or the like on the TFT in the same step as the TFT process.

A method for manufacturing the image display device having the cell structure shown in FIG. 1 will be described with reference to steps a to j shown in FIGS.
An oxide film 202 is formed on a semiconductor substrate 201 by LOCOS oxidation.
Are formed to form regions to be element isolation and openings (steps a and b). Next, a trench groove 203 is opened (step c), an inner wall is oxidized to form an oxide film 204, and then p ⁺ polysilicon 205 is buried. This structure has an aspect ratio of 1:
It is possible to make from 5 to 1:10. Thereafter, n-type impurities are implanted into a region where the transistor is to be formed so that the transistor has a desired threshold value, thereby forming a well region 206 (step d). Next, after a gate oxide film 207 is formed by oxidation (step e), a contact hole is opened, and gate poly 208 and 2 are formed.
Then, boron is implanted with a gate self-alignment to form a low-concentration electric field relaxation layer 210. Further, boron is implanted, and the source 211 and the drain 2 of the transistor are formed.
12 is formed. In order to obtain a potential of a silicon layer forming a transistor, a deep n region 213 is formed by implantation of phosphorus or arsenic, and a signal line 214 and a wiring 215 are formed.
Is formed by evaporating aluminum (step f). Next, after the passivation film 216 is applied, the substrate on which the transistor is formed and the transparent substrate 218 are bonded with the adhesive 217 (step g). This substrate is polished or etched from the back side to obtain the shape shown in step h. The termination at this time can be easily detected based on whether or not the oxide layer 202 is exposed. In the future, a process will be performed on the back side,
The OCOS-oxidized region 202 is transparent, and the alignment mark can be seen through the oxide film. A pixel electrode (for example, ITO) 219 is formed on the back side, and a passivation film 220 is formed thereon (step i).
Finally, rubbing is performed on the passivation film to sandwich the liquid crystal layer 221 between the passivation film and the opposing substrate (step j).

Compared with the conventional example, the step of the passivation film 220 is clearly smaller in this embodiment, and the thickness of the liquid crystal layer 221 is uniform in the cell. Also,
Since the level difference is reduced, rubbing is performed uniformly, and it is expected that the contrast of the display screen, the aperture ratio, and the number of gradations will be improved. In addition, since a capacitor is formed between the polysilicon 205 and the well region 206 by utilizing the side wall of the trench, the storage capacitor is formed without lowering the aperture ratio and without increasing the number of processes. Thus, a display device with a small number of gray levels and a high gradation can be realized.

Next, the effect of the present invention will be described for an example in which the present embodiment is used for an electronic viewfinder. When trying to create a 200,000 pixel finder with a panel size of 13 × 10 mm, the size of one pixel is approximately 26 × 2
5 μm. Assuming that the liquid crystal application voltage is 5 V, in order to obtain 64 gradations, the potential change of the pixel between the writing to the pixel and the next writing (1/30 sec) needs to be 80 mV or less. 1 × 10 leakage current of transistors
Assuming ^-13 A, a storage capacitance of about 80 pF is required. When this capacitance is formed via a 500 ° SiO ₂ film, its area is about 60 μm ² . This is one of the pixel cell area
8%. On the other hand, if the width of each wiring is 2 μm and the size of the transistor is 6 × 3 μm, the area occupied by the wiring and the transistor is about 190 μm ² and the aperture ratio is 50%.
Becomes Furthermore, if the area around the opening is light-shielded by 2 μm in order to shield the portion where the alignment of the liquid crystal is disturbed due to the influence of steps such as wiring, the aperture ratio becomes 35%. On the other hand, in the present embodiment, when the thickness of the Si layer is 10 μm, the width of the transistor is 6 μm, and the thickness of the oxide film in the trench is 500 °, the aperture ratio is not reduced for forming the capacitance.
A capacitance of pF can be obtained. Further, since the disorder in the alignment of the liquid crystal is reduced, an aperture ratio of about 70% can be obtained.

Similarly, if a viewfinder of 300,000 pixels is to be manufactured as in the conventional example, the aperture becomes several percent, which is practically difficult to realize. % Aperture ratio can be obtained.

The effects of the present invention are also effective when a PTV (projection television) is configured using the display device of the present invention. FIG. 5 shows an example of the configuration of the PTV. The amount of transmitted light from the light source is controlled by each pixel on the liquid crystal panel, and an image is displayed on a screen. At this time, a color display can be realized by attaching a color filter to each pixel. Alternatively, color display can be realized by using three liquid crystal panels and superimposing them on a screen using light sources of three colors.

As an example in which the present embodiment is applied to a PTV, a case will be described in which a liquid crystal display device for a PTV compatible with Hi-Vision is constructed. In HDTV, the horizontal scanning line is 102
When there are four liquid crystal panels, the number of pixels is about 19
It becomes 10,000 pixels. When the projection liquid crystal panel has a size of 55 × 30 mm, the size of one pixel is approximately 30 μm.
m × 30 μm. Estimating the aperture ratio in the case where this is constituted by the conventional technique in the same manner as the viewfinder described above, it is 60 μm ² for forming the capacitance, 340 μm ² for the wiring and the transistor, and the shielding of the transmitted light due to the disorder of the alignment of the liquid crystal. For this purpose, 100 μm ² is used for other than the opening, and the opening ratio is about 65%. According to the present invention, when a liquid crystal display device for a PTV having the same size is configured, the aperture ratio is approximately 75%. From this, in the present invention, it is possible to configure a PTV that is about 15% brighter with the same light source than the prior art. Alternatively, if the light amount of the light source is 1
A PTV having a display luminance equivalent to that of the conventional example can be constructed even if the PTV is smaller by 5%.

(Second Embodiment) FIG. 6 shows a second embodiment according to the present invention.
1 shows a cross-sectional view of the cell structure of the embodiment. In this example, a description will be given of an example in which a PMOS is formed of silicon to be a driving transistor.

Reference numeral 301 denotes an n-type silicon layer;
02 is a LOCOS oxide film. A drain 303, a source 304, a low-concentration electric field relaxation layer 305 for improving withstand voltage,
The gate 306 forms a pixel driving transistor. The drain 303 contacts the p ⁺ polysilicon 308 buried inside the oxide film 307 formed in the trench, and is connected to the pixel electrode 309. Source 304
Are connected to the signal line 310. The potential of the silicon layer 301 is given by a wiring 311. A passivation film 312 is provided above the transistor, and is attached to a transparent substrate (eg, glass) 314 with an adhesive 313. A passivation film 31 is provided below the pixel electrode.
5 and the liquid crystal layer 316 is interposed between the liquid crystal layer 316 and the counter substrate. The image signal input to the signal line 310 is
6 is written to the pixel electrode 309 while the voltage for turning on the transistor is applied to the pixel electrode 6, and is held at that potential while the transistor is turned off by the control of the gate 306.

As compared with the conventional example, in this embodiment, the interface between the liquid crystal layer 316 and the device substrate is flat. As a result, there is no influence of the steps at all, the disorder of the liquid crystal alignment is reduced, and color shift and in-plane non-uniformity are eliminated. In addition, a decrease in contrast and a decrease in the number of gradations due to non-uniform rubbing can be suppressed, and a uniform image display device with high gradation and high luminance can be realized. Pixel electrode 30
The potential of No. 9 can be stabilized by the capacitance between the silicon layer 301 and the polysilicon 308, and the influence of transistor leakage and the like can be reduced. Forming the additional capacitor in this manner does not lower the aperture ratio as in the conventional example, but also eliminates the need to newly draw a wiring for forming a capacitor, thereby simplifying the process. Furthermore, since the distance from the pixel electrode to the gate line and signal line that causes the swing becomes longer, and the silicon layer acts as a shield between them, the potential fluctuation of the pixel electrode due to the swing should be reduced. Can be. From these facts, it is possible to realize an image display device having a high aperture ratio, high luminance, high gradation, and high uniformity. In this embodiment, the additional capacitance is formed by an oxide film capacitance. However, it is also possible to form a junction capacitance by burying polysilicon without oxidizing the side wall of the trench. Further, in this embodiment, in addition to the effect obtained in the first embodiment, since the wiring 311 for obtaining the well potential is formed on the back surface side of the silicon layer 301, the aperture ratio is reduced by drawing the wiring 311. Can be prevented, and a display device with a bright display screen can be formed.

A method of manufacturing the image display device having the cell structure shown in FIG. 6 will be described with reference to steps a to j of FIGS. An oxide film 402 is formed on the semiconductor substrate 401 by LOCOS oxidation, and regions for element isolation and openings are formed (steps a and b). Next, a trench groove 403 is opened (step c), the inner wall is oxidized to form an oxide film 404, and then p ⁺ polysilicon 405 is buried. This structure has an aspect ratio of 1:
It is possible to make from 5 to 1:10. Thereafter, n-type impurities are implanted into a region where the transistor is to be formed so that the transistor has a desired threshold value, thereby forming a well region 406 (step d). Next, after a gate oxide film 407 is formed by oxidation (step e), a contact hole is opened and gate poly 408 and gate poly 408 are formed.
Then, boron is implanted with a gate self-alignment to form a low-concentration electric field relaxation layer 410. Further, boron is implanted, and the source 411 and the drain 4
12 is formed. Then, the signal line 413 is formed by evaporating aluminum (step f). Next, the passivation film 4
After attaching 14, the substrate on which the transistor is formed and the transparent substrate 416 are bonded with the adhesive 415 (step g). This substrate is polished or etched from the back side to obtain the shape shown in step h. In the future, a process will be performed on the rear surface side, but the LOCOS-oxidized region 402 is transparent, and the alignment mark can be seen through the oxide film. A wiring 417 for obtaining a well potential is provided on the back side by aluminum evaporation, and a pixel electrode (for example, ITO) is provided.
418 are formed, and a passivation film 419 is formed thereon.
(Step i). Finally, rubbing is performed on the passivation film to sandwich the liquid crystal layer 420 between the passivation film and the opposing substrate (step j).

As compared with the conventional example, the step of the passivation film 419 is clearly smaller in the present embodiment, and the thickness of the liquid crystal layer 420 is uniform in the cell. Also,
Since the level difference is reduced, rubbing is performed uniformly, and it is expected that the contrast of the display screen, the aperture ratio, and the number of gradations will be improved. In addition, since the capacitance is formed between the polysilicon 405 and the well region 406 by utilizing the side wall of the trench, the storage capacitance is formed without lowering the aperture ratio and without increasing the number of processes. Thus, a display device with a small number of gray levels and a high gradation can be realized.

Next, the effect of the present invention will be described for an example in which the present embodiment is used for an electronic viewfinder. As described in the first embodiment, the panel size is 13 × 1
If an attempt is made to create a 200,000 pixel finder with 64 gradations of 0 mm, the aperture ratio will be 35%. In contrast,
In this embodiment, as in the first embodiment, the capacitance can be obtained without lowering the aperture ratio for forming the capacitor, and the wiring for obtaining the potential of the silicon layer does not cause a reduction in the aperture ratio. An aperture ratio of about 80% can be obtained.

Similarly, if a viewfinder of 300,000 pixels is to be manufactured as in the conventional example, the aperture becomes several percent, which is practically difficult to realize. % Aperture ratio can be obtained.

The effect of the present invention is also effective when a PTV is formed using the display device of the present invention. As an example, a case will be described in which a liquid crystal display device for a high-definition PTV is configured. In HDTV, the horizontal scanning line is 102
When there are four liquid crystal panels, the number of pixels is about 19
It becomes 10,000 pixels. When the projection liquid crystal panel has a size of 55 × 30 mm, the size of one pixel is approximately 30 μm.
m × 30 μm. Estimating the aperture ratio in the case where this is constituted by the conventional technique in the same manner as the viewfinder described above, it is 60 μm ² for forming the capacitance, 340 μm ² for the wiring and the transistor, and the shielding of the transmitted light due to the disorder of the alignment of the liquid crystal. For this purpose, 100 μm ² is used for other than the opening, and the opening ratio is about 65%. According to the present invention, when the same size liquid crystal display device for PTV is configured, the aperture ratio is approximately 85%. From this, in the present invention, it is possible to construct a PTV that is about 30% brighter with the same light source than the prior art. Alternatively, if the light amount of the light source is 3
Even if it is smaller by 0%, a PTV having the same display luminance as that of the conventional example can be formed.

(Third Embodiment) FIG. 10 is a sectional view of a cell structure according to a third embodiment of the present invention. In this example, a description will be given of an example in which a PMOS is formed of silicon to be a driving transistor.

Reference numeral 501 denotes an n-type silicon layer.
02 is a LOCOS oxide film. A drain 503, a source 504, a low-concentration electric field relaxation layer 505 for improving withstand voltage,
A pixel driving transistor is configured by the gate 506. The drain 503 is in contact with the p ⁺ polysilicon 508 buried inside the oxide film 507 formed in the trench, and is connected to the pixel electrode 509. Source 504
Are connected to the signal line 510. The potential of the silicon layer 501 is given by a wiring 511. A passivation film 512 is provided above the transistor, and is attached to a transparent substrate (eg, glass) 514 with an adhesive 513. A passivation film 51 is provided below the pixel electrode.
5, and the liquid crystal layer 516 is sandwiched between the liquid crystal layer 516 and the counter substrate. The image signal input to the signal line 510 is applied to the gate 50.
6 is written to the pixel electrode 509 while a voltage for turning on the transistor is applied to the pixel 6, and is kept at that potential while the transistor is turned off by control of the gate 506.

As compared with the conventional example, in this example, the interface between the liquid crystal layer 516 and the device substrate is flat. As a result, there is no influence of the steps at all, the disorder of the liquid crystal alignment is reduced, and color shift and in-plane non-uniformity are eliminated. In addition, a decrease in contrast and a decrease in the number of gradations due to non-uniform rubbing can be suppressed, and a uniform image display device with high gradation and high luminance can be realized. Pixel electrode 50
The potential of No. 9 can be stabilized by the capacitance between the silicon layer 501 and the polysilicon 508, and the influence of transistor leakage and the like can be reduced. Forming the additional capacitor in this manner does not lower the aperture ratio as in the conventional example, but also eliminates the need to newly draw a wiring for forming a capacitor, thereby simplifying the process. Furthermore, since the distance from the pixel electrode to the gate line and signal line that causes the swing becomes longer, and the silicon layer acts as a shield between them, the potential fluctuation of the pixel electrode due to the swing should be reduced. Can be. From these facts, it is possible to realize an image display device having a high aperture ratio, high luminance, high gradation, and high uniformity. In this embodiment, the additional capacitance is formed by an oxide film capacitance. However, it is also possible to form a junction capacitance by burying polysilicon without oxidizing the side wall of the trench.

In this embodiment, when the wiring 511 for obtaining the well potential is formed on the back surface of the silicon layer 501, the back surface of the transistor is formed to be shielded from light. When light enters the transistor, hole-electron pairs are generated, and a leak current is generated. This causes deterioration in contrast and gradation of the display device.

In the prior art, the light shielding of the transistor is performed by forming a light shielding filter on a substrate different from the substrate on which the transistor is formed, and bonding the substrates to each other. However, in this technique, it is necessary to perform light shielding in consideration of the bonding accuracy, and there is a problem that stray light enters because there are several interlayer films between the semiconductor layer and the light shielding layer of the transistor.

In order to avoid the above problems, it is necessary to increase the light-shielding area. However, this has the drawback that the aperture ratio decreases and the luminance of the display device decreases.
In this embodiment, since the light shielding of the transistor is performed using the wiring 511, there is no need to expect a large margin unlike bonding. Further, since the wiring 511 is close to the semiconductor layer, the influence of stray light is smaller than that of the related art. The light shielding by the wiring 511 may cover the entire transistor, but may cover the depletion layer region contributing to the leakage current and the periphery thereof by a free process of carriers.

As described above, in this embodiment, in addition to the effects obtained in the second embodiment, it is possible to achieve higher luminance by improving the aperture ratio, higher gradation by lowering the leak current of the transistor, and higher contrast. it can.

A method of manufacturing the image display device having the cell structure shown in FIG. 10 will be described with reference to steps a to j of FIGS. An oxide film 6 is formed on the semiconductor substrate 601 by LOCOS oxidation.
02 is formed, and regions for element isolation and openings are formed (steps a and b). Next, a trench groove 603 is opened (step c), an inner wall is oxidized to form an oxide film 604, and p ⁺ polysilicon 605 is buried. This structure can be made from an aspect ratio of about 1: 5 to about 1:10.
Thereafter, n-type impurities are implanted into a region where the transistor is to be formed so that the transistor has a desired threshold value, thereby forming a well region 606 (step d). Next, after a gate oxide film 607 is formed by oxidation (step e), a contact hole is opened and gate poly films 608 and 6 are formed.
Then, boron is implanted with a gate self-alignment to form a low-concentration electric field relaxation layer 610. Further, boron is implanted to form a source 611 and a drain 6 of the transistor.
12 is formed. Then, the signal line 613 is formed by evaporating aluminum (step f). Next, the passivation film 6
After attaching 14, the substrate on which the transistor is formed and the transparent substrate 616 are bonded with the adhesive 615 (step g). This substrate is polished or etched from the back side to obtain the shape shown in step h. In the future, a process will be performed on the rear surface side, but the LOCOS-oxidized region 602 is transparent, and the alignment mark can be seen through the oxide film. A wiring 617 for obtaining a well potential is formed on the back side by aluminum deposition, and a pixel electrode (for example, ITO) is provided.
618 is formed, and a passivation film 619 is formed thereon.
(Step i). Finally, rubbing is performed on the passivation film to sandwich the liquid crystal layer 620 between the passivation film and the opposing substrate (step j). Through the above steps, the shape shown in FIG. 10 can be obtained.

The liquid crystal display device according to the structure of the present embodiment is different from the electronic viewfinder, PTV,
Needless to say, it is effective in HMD.

(Fourth Embodiment) In this embodiment, a case where a display device according to the present invention is formed using an SOI substrate will be described.

FIG. 14 is a sectional view of a cell structure according to a fourth embodiment of the present invention. In this example, a description will be given of an example in which a PMOS is formed of silicon to be a driving transistor. 7
01 is an n-type silicon layer, and 702 is LOCO
This is an S oxide film. Reference numeral 703 denotes an oxide film below the silicon layer. A pixel driving transistor is composed of a drain 704, a source 705, a low-concentration electric field relaxation layer 706 for improving withstand voltage, and a gate 707. Drain 704
Are in contact with the p ⁺ polysilicon 709 buried inside the oxide film 708 formed in the trench, and the pixel electrode 710
It is connected to the. The source 705 is connected to the signal line 711. The potential of the silicon layer 701 is given by a wiring 712. A passivation film 713 is provided above the transistor, and is attached to a transparent substrate (for example, glass) 715 with an adhesive 714. A passivation film 716 is provided below the pixel electrode, and a liquid crystal layer 717 is interposed between the passivation film 716 and the counter substrate. In the image signal input to the signal line 711, the transistor
The data is written to the pixel electrode 710 while the voltage for applying N is applied, and is kept at that potential while the transistor is turned off by the control of the gate 707.

As compared with the conventional example, in this embodiment, the interface between the liquid crystal layer 717 and the device substrate is flat. As a result, there is no influence of the steps at all, the disorder of the liquid crystal alignment is reduced, and color shift and in-plane non-uniformity are eliminated. In addition, a decrease in contrast and a decrease in the number of gradations due to non-uniform rubbing can be suppressed, and a uniform image display device with high gradation and high luminance can be realized. Pixel electrode 71
The potential of 0 can be stabilized by the capacitance between the silicon layer 701 and the polysilicon 709, and the influence of transistor leakage and the like can be reduced. Forming the additional capacitor in this manner does not lower the aperture ratio as in the conventional example, but also eliminates the need to newly draw a wiring for forming a capacitor, thereby simplifying the process. Furthermore, since the distance from the pixel electrode to the gate line and signal line that causes the swing becomes longer, and the silicon layer acts as a shield between them, the potential fluctuation of the pixel electrode due to the swing should be reduced. Can be. From these facts, it is possible to realize an image display device having a high aperture ratio, high luminance, high gradation, and high uniformity.

In this embodiment, the additional capacitance is formed by an oxide film capacitance. However, it is also possible to form a junction capacitance by burying polysilicon without oxidizing the side wall of the trench. In this embodiment, the wiring 71 for obtaining the Well potential is used.
When 2 is formed on the back side of the silicon layer 701, the back side of the transistor is formed so as to shield the light, and the same effect as obtained in the third embodiment can be obtained.

A method of manufacturing the image display device having the cell structure shown in FIG. 14 will be described with reference to steps a to j in FIGS. Reference numeral 801 denotes an SOI substrate (for example, SIMOX),
There are an insulating layer 802 and a silicon layer 803 on the surface. The silicon layer 803 is LOCOS-oxidized to form an oxide film 804, and an area for element isolation and an opening is formed (step a,
b). Next, a trench 805 is opened (step c),
After forming the oxide film 806 by oxidizing the inner wall, p ⁺ polysilicon 8
07 is embedded. This structure can be made from an aspect ratio of about 1: 5 to about 1:10. Thereafter, an n-type impurity is implanted into a region where the transistor is to be formed, so that the transistor has a desired threshold value.
An 11 region 808 is formed (step d). Next, after forming a gate oxide film 809 by oxidation (step e), a contact hole is opened, and gate poly 810 and 811 are formed.
Boron is implanted with a gate self-alignment to form a low-concentration electric field relaxation layer 812. Further, boron is implanted to form a source 813 and a drain 814 of the transistor. Then, the signal line 815 is formed by evaporating aluminum (step f). Next, after the passivation film 816 is applied, the substrate on which the transistor is formed and the transparent substrate 818 are bonded with the adhesive 817 (step g). This substrate is polished or etched from the back side to obtain the shape shown in step h. At this time, by using the insulating layer 802 as an etching stopper, the shape shown in the step h can be easily realized as compared with the first to third embodiments. Next,
A process is performed on the rear surface side, and the LOCOS-oxidized region 804 is transparent, and the alignment mark can be seen through the oxide film. A wiring 819 for obtaining a well potential is provided on the back surface side by aluminum evaporation, a pixel electrode (for example, ITO) 820 is formed, and a passivation film 821 is provided thereon (step i). Finally,
Rubbing is performed on the passivation film, and a liquid crystal layer 822 is sandwiched between the passivation film and the opposing substrate (step j).

The shape shown in FIG. 14 is obtained by the above steps. In this embodiment, since the etching of the back surface is performed using the insulating layer 802 as a stopper, the insulating film thickness and the silicon film thickness after the etching become uniform in the plane. . Further, if the thickness of the silicon layer 803 of the SOI substrate is constant between wafers, a display device having a desired silicon thickness and insulating film thickness can be easily obtained. This makes it possible to control discoloration and reduction in luminance due to interference of transmitted light. As a result, it is possible to provide a display device in which both the color and the luminance are uniform within the panel, and the color tone and the luminance do not differ between the panels.

The liquid crystal display device according to the structure of the present embodiment is different from the electronic viewfinder, PTV,
Needless to say, it is effective in HMD.

(Fifth Embodiment) In the first embodiment, the gate electrode 208 is formed after the polysilicon 205 is buried in the trench, but the trench is formed by a single polysilicon deposition. It is also possible to form polysilicon and a gate electrode. The process is shown in FIG.
Will be described according to the steps a to d.

An oxide film 902 is formed on a semiconductor substrate 901 by LOCOS oxidation to form regions for element isolation and openings (steps a and b). Next, the trench 903 is opened. Further, n is set so that the transistor has a desired threshold in a region where the transistor is formed by ion implantation.
A well region 906 is formed by performing a type impurity implantation. Thereafter, the inner wall of the trench is oxidized to form an oxide film 904.
Is formed (step c). Thereafter, the source region 911 and the drain region 9 of the transistor are implanted by boron ion implantation.
After the formation of the oxide film 12, an oxide film 902 is formed in order to make electrical contact between the polysilicon formed in a later step and the drain region.
After a hole is made in a part of the substrate, polysilicon is deposited, and a gate 908 and polysilicon 909 in the trench groove are formed. Thereafter, the low-concentration electric field relaxation layer 9 is formed by gate self-alignment.
After forming a contact hole 10 and opening a contact hole, a wiring is connected to the source region. Through the above steps, the structure shown in FIG. 18D can be obtained. Further, by performing the steps after the step g in the first embodiment, the liquid crystal display device according to the fifth embodiment of the present invention is obtained. Steps a to d of the fifth embodiment
Can be applied to the second to fourth embodiments.

(Sixth Embodiment) In the first to fifth embodiments, the storage capacitor for the voltage applied to the liquid crystal electrode is formed only on the inner wall of the trench isolation groove. Even if the capacitance value is increased, the effect of the present invention is effective. The steps of the sixth embodiment according to the present invention are shown in FIGS.
Will be described according to the steps a to e.

An oxide film 1002 is formed on the semiconductor substrate 1001 by LOCOS oxidation to form regions for element isolation and openings (steps a and b). Next, n is set so that the transistor has a desired threshold value in a region where the transistor is formed.
After a well region 1006 is formed by performing a type impurity implantation, a trench groove 1003 is opened, and an inner wall and a surface are oxidized to form an oxide film 1004. Next, polysilicon is deposited and the polysilicon 1005 in the trench is deposited.
And a gate electrode 1008 are formed (step d). Further, the source region 1011 and the drain region 10 are formed by ion implantation.
After forming 12, a low-concentration electric field relaxation layer 1010 is formed by gate self-alignment. Further, after an interlayer insulating film 1013 is formed, contact holes are opened in a part of the insulating film 1013 and the oxide film 1002. Further, polysilicon is deposited so as to contact the polysilicon 1005 in the trench groove and to cover the gate electrode 1010 via the insulating film 1013 to obtain the structure of FIG. 20E. Thereafter, processes h to h of the first embodiment are performed.
The liquid crystal display device according to the present invention can be obtained in the same manner as in j.

In the structure of the sixth embodiment, the storage capacitor is formed not only on the inner wall of the trench but also on the gate electrode 10.
10, the capacitance value becomes larger, and even if a leakage current of the transistor occurs, the fluctuation of the potential of the pixel electrode is small, the contrast is high, and a liquid crystal display device with high gradation can be obtained.

(Seventh Embodiment) FIG. 21 is a top view of a seventh embodiment according to the present invention. Reference numeral 1101 denotes an isolation wall of the semiconductor region, and 1102 and 1103 denote source and drain regions of the transistor, respectively. 1104 is a gate electrode of the transistor, 1105 is a trench groove, 11
Reference numeral 06 denotes an oxide film formed on the inner wall of the trench.
Is polysilicon filled in the trench. 110
8 is a contact for taking the potential of the semiconductor region,
Reference numeral 1109 denotes a wiring (for example, aluminum).

[0049] In this embodiment, not only the capacitance between the drain 1103 and the polysilicon 1107 over the oxide film 1106 is formed, and between the semiconductor region and the port Li silicon 1107 via a gate oxide film Capacity 1110
Are formed, and the two capacitors are electrically connected in parallel. By adopting such a structure, it is possible to form a larger capacitance than in the first to sixth embodiments.

(Eighth Embodiment) FIG. 22 shows a top view of an eighth embodiment according to the present invention. Reference numeral 1201 denotes an isolation wall of the semiconductor region, and 1202 and 1203 denote source and drain regions of the transistor, respectively. Reference numeral 1204 denotes a gate electrode of the transistor; 1205, a trench groove;
206 is an oxide film formed on the inner wall of the trench, 120
Reference numeral 7 denotes polysilicon filled in the trench. 12
08 is a contact for taking the potential of the semiconductor region, and 1209 is a wiring (for example, aluminum).

In this embodiment, since the trench 1206 is divided into a plurality of grooves and opened, the inner wall 12
06 can have a larger surface area, and a larger capacity can be obtained. When the structure obtained by the seventh and eighth embodiments is applied to a switching transistor of a liquid crystal display device and a storage capacitor for a pixel electrode potential, it goes without saying that a display device with high gradation and high contrast can be obtained.

[0052]

As described above, according to the present invention, the pixel electrode and the pixel transistor electrode are connected through the opening formed in the semiconductor layer, and the capacitance is formed by using the side wall of the opening.
The pixel electrode can be provided with additional capacitance without impairing the aperture ratio of the display device, and a display device with high luminance, high gradation, and high contrast can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view of a cell structure according to a first embodiment of the present invention.

FIG. 2 shows a manufacturing process (step a) of the first embodiment according to the present invention.
It is explanatory drawing of-d).

FIG. 3 shows a manufacturing process (step e) of the first embodiment according to the present invention.
FIG.

FIG. 4 shows a manufacturing process (step h) of the first embodiment according to the present invention.
It is explanatory drawing of-j).

FIG. 5 is an explanatory diagram showing an example of a configuration of a PTV (projection television) to which the present invention can be applied.

FIG. 6 is a sectional view of a cell structure according to a second embodiment of the present invention.

FIG. 7 shows a manufacturing process (step a) of a second embodiment according to the present invention.
It is explanatory drawing of-d).

FIG. 8 shows a manufacturing process (step e) of a second embodiment according to the present invention.
FIG.

FIG. 9 shows a manufacturing step (step h) of a second embodiment according to the present invention.
It is explanatory drawing of-j).

FIG. 10 is a sectional view of a cell structure according to a third embodiment of the present invention.

FIG. 11 is an explanatory diagram of manufacturing steps (steps a to d) of a third embodiment according to the present invention.

FIG. 12 is an explanatory diagram of manufacturing steps (steps e to g) of the third embodiment according to the present invention.

FIG. 13 is an explanatory view of the manufacturing steps (steps h to j) of the third embodiment according to the present invention.

FIG. 14 is a sectional view of a cell structure according to a fourth embodiment of the present invention.

FIG. 15 is an explanatory diagram of manufacturing steps (steps a to d) of a fourth embodiment according to the present invention.

FIG. 16 is an explanatory diagram of manufacturing steps (steps e to g) of the fourth embodiment according to the present invention.

FIG. 17 is an explanatory diagram of the manufacturing steps (steps h to j) of the fourth embodiment according to the present invention.

FIG. 18 is an explanatory diagram of manufacturing steps (steps a to d) of a fifth embodiment according to the present invention.

FIG. 19 is an explanatory diagram of manufacturing steps (steps a to d) of a sixth embodiment according to the present invention.

FIG. 20 is an explanatory view of a manufacturing step (step e) of the sixth embodiment according to the present invention.

FIG. 21 is a top view of the seventh embodiment according to the present invention.

FIG. 22 is a top view of the eighth embodiment according to the present invention.

FIG. 23 is a sectional view of a conventional cell structure.

[Explanation of symbols]

101, 301, 501, 701 Silicon layer 102, 302, 502, 702 LOCOS oxide film 103, 303, 503, 704 Drain 104, 304, 504, 705 Source 105, 305, 505, 706 Low-concentration electric field relaxation layer 106, 306 , 506, 707 Gate 107, 307, 507, 703, 708 Oxide film 108, 308, 508, 709 p ⁺ polysilicon 109, 309, 509, 710 Pixel electrode (transparent electrode) 110, 310, 510, 711 Signal line 111 , 311, 511, 712 Wiring 112, 115, 312, 315, 512, 515, 7
13,716 Passivation film 113,313,714 Adhesive 114,314,514,715 Transparent substrate 116,316,516,717 Liquid crystal layer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-55529 (JP, A) JP-A-5-257171 (JP, A) JP-A-4-170520 (JP, A) JP-A-2- 154232 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G02F 1/1368 H01L 29/786

Claims (4)

(57) [Claims] 1. An n-type or p-type well region and an n-type or p-type well region on one surface side of a semiconductor layer or a semiconductor substrate.
A p-type or n-type source formed in the well region;
Forming a transistor having a drain and its wiring, forming a liquid crystal voltage application electrode for applying a voltage to liquid crystal on the other surface side of the semiconductor layer or the semiconductor substrate,
A source or a drain of the transistor is connected to the liquid crystal voltage application electrode through an opening in the semiconductor layer or the semiconductor substrate, and at least a part of a capacitor provided for holding a voltage of the liquid crystal voltage application electrode is connected. An image display device formed on a side wall of the opening. 2. The image display device according to claim 1, wherein the potential of the well region is given by wiring. 3. The image display apparatus according to claim 1 or 2, formed on the other surface side to the side where the wiring forming the transistor of the semiconductor layer or the semiconductor substrate for fixing the potential of the Well region An image display device comprising: 4. The image display apparatus according to any one of claims 1 to 3, the image display device in which wires for fixing the potential of the Well region characterized by being formed so as to shield the transistors .