JP3302158B2 - Computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laptop or notebook type portable computer system, and more particularly to a power supply status such as battery information by communication from a power supply controller to a CPU.
To notify the computer system.

[0002]

2. Description of the Related Art In recent years, various portable personal computers of a laptop type or a notebook type have been developed. This type of portable computer is configured to be driven by a battery, and performs various power management operations to extend the operable time of the battery and displays the remaining battery power and the like.
Such power supply management is performed based on a power supply status notified from the power supply controller, such as the remaining battery capacity and whether or not the AC adapter power supply is connected.

[0003] Between the CPU and the power supply controller,
Communication for receiving such information on the power supply from the power supply controller is performed. Conventionally, this communication is performed by a polling method, and in order for the CPU to receive necessary information from the power supply controller, it is necessary to sequentially issue a status read command from the CPU to the power supply controller. For this reason, there is a problem that communication between the CPU and the power supply controller takes a relatively long time.

For example, it takes 10 milliseconds to transfer data from one of a CPU and a power supply controller to the other, and
Communication between the power supply controller and the power supply controller.
ACK transfer to the power supply controller and status transfer from the power supply controller to the CPU, the communication between the CPU and the power supply controller requires a total of 30 milliseconds.

[0005] Therefore, there is no problem when the number of information exchanges between the CPU and the power supply controller is relatively small, but when the number of exchanges increases, communication between the CPU and the power supply controller becomes difficult.
The PU is occupied for a lot of time, which causes a problem that the processing performance of the entire system is reduced.

The number of communications between the CPU and the power supply controller increases as the number of types of power supply status increases. For this reason, if the type of the power supply status is increased in order to extend the function of the power management function of the system, the number of times of communication is increased by that amount and the system performance is degraded.

[0007]

In the conventional portable computer, the transmission of the power status from the power controller to the CPU is performed by a polling method in which the CPU issues a command to the power controller. For this reason, there has been a disadvantage that the number of times of data transfer between the CPU and the power supply controller is increased, thereby lowering the system performance. Further, even when the power status has not changed at all, the CPU needs to communicate with the power controller, so that useless communication is required. Further, when the power management function is expanded, the types of power statuses that need to be transmitted from the power supply controller to the CPU are increased, and there is a drawback that the execution of application programs for power management is hindered. Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a portable computer capable of efficiently transmitting a power status from a power controller to a CPU without deteriorating system performance. And

[0009]

SUMMARY OF THE INVENTION The present invention provides
In a computer system having a CPU, various I / O units, and a power supply controller for controlling power supply to these units, various data provided between the CPU and the power supply controller and exchanged between the CPU and the power supply controller Is set, and the fact that data is set in the register
In order to notify the PU,
Means for generating an interrupt signal to the CPU in response to an instruction to generate a reset signal, wherein the power supply controller responds to a mode setting request from the CPU.
Set the power controller operation mode to polling mode or
And event mode.
Previous in response to power status indicating the power switch is off
Set the power controller to polling mode.
Means for setting a power status relating to power control of the computer system to the register in response to a status read request supplied from the CPU via the register in the polling mode; and Monitors various power statuses related to the power management of the computer system, and when a change in the power status is detected, sets data indicating the changed power status in the register and issues an instruction to generate the interrupt signal. means are provided.

[0010] In this computer system, the power supply controller has an event mode in addition to the polling mode. In the event mode, the power controller monitors various statuses of the computer system related to power control. When an event requiring power control occurs, that is, when a change in the power status is detected, the power controller indicates the detected event. Set status in register. At this time, an interrupt signal is supplied to the CPU, thereby notifying the CPU that the power status has been set by the power controller.
In this way, in this system, the power status changed each time an event of a power status change occurs is notified to the CPU by the interrupt signal. No commands need to be issued. Therefore, the power supply status can be efficiently transmitted from the power supply controller to the CPU. Also, power control
The rollers are polled during the system startup sequence.
System startup sequence.
There is no problem of being interrupted by venting.

[0011]

[0012]

[0013]

In this system, a power supply
The two operating modes of the Troller can be changed programmably
It is configured to be able to. Therefore, when the CPU is executing an uninterruptible program such as an application program for high-speed communication, the power supply controller is switched from the event mode to the polling mode. Inconveniences such as generation of trouble can be prevented.

Immediately after the system power is turned on or immediately before the system power is turned off, if the power controller is set to the event mode, the power-on sequence and the power-off sequence are interrupted by interruption from the power controller. Therefore, it is preferable to set the power supply controller to the polling mode immediately after the system power is turned on or immediately before the system power is turned off.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a system configuration of a portable computer according to an embodiment of the present invention. This portable computer is a laptop or notebook type computer that can be driven by a battery, and is configured to be battery driven. This portable computer includes a CPU 11, a system controller 12, a main memory 13, a BIOS ROM 14,
Bus conversion circuit 15, real-time clock (RTC) 1
6, a power supply controller 17, and a power supply circuit 18.

The CPU 11 and the main memory 13
CPU local bus 19 including a 2-bit data bus
It is connected to the. The CPU local bus 19 is connected to a bus including a 16-bit data bus via a bus conversion circuit 15.
It is connected to a system bus 20 of the SA specification. The system controller 12, the BIOS ROM 14, and the real-time clock (RTC) 16 are connected to the system bus 2
Connected to 0.

The system bus 20 is connected to various other I / O devices such as an interrupt controller, a keyboard controller, a system timer, and the like.
As the CPU 11, for example, a microprocessor SL Enhanc manufactured and sold by Intel Corporation in the United States
ed Intel 486 is used. SLEnhan
Ced Intel 486 has the following system management functions.

That is, the CPU 11 has a system management mode (SMM; System Ma) in addition to a real mode, a protect mode, and a virtual 86 mode for executing programs such as an application program and an OS.
The system has an operation mode for executing a system management program referred to as “nagement mode”.

The real mode is a mode in which a memory space of a maximum of 1 Mbyte can be accessed, and a physical address is determined by an offset value from a base address represented by a segment register.

Protect mode is up to 4 per task
This mode allows access to a G-byte memory space.
A linear address is determined using an address mapping table called a descriptor table. This linear address is finally converted to a physical address by paging.

The virtual 86 mode is a mode for operating a program configured to operate in the real mode in the protect mode. A program in the real mode is treated as one task in the protect mode.

The system management mode (SMM) is a pseudo real mode. In this mode, the descriptor table is not referred to and paging is not executed. System management interrupt (SMI; System Management Interrupter)
When (rupt) is issued to the CPU 11, the operation mode of the CPU 11 is switched from the real mode, the protect mode, or the virtual 86 mode to the SMM. In the SMM, a system management program is executed.

The SMI is a kind of the non-maskable interrupt NMI, and is the highest priority interrupt having a higher priority than the normal NMI and the maskable interrupt INTR. This SM
By issuing I, various SMI service routines prepared as a system management program can be started without depending on the application program being executed or the OS environment.

In this computer system, the SMI is used for transmitting various power statuses from the power controller 17 to the CPU 11. in this case,
The power supply status is notified to the CPU 11 by the SMI every time the status change occurs.

The system controller 12 is a gate array for controlling memories and I / O in the system, and includes a SM for generating an SMI signal to the CPU 11.
I generation circuit 121, CPU 11 and power supply controller 17
There are provided a register 122 used for communication between them, a register 123 in which data designating SMI generation is set, and the like.

In addition to the registers 122 and 123, the system controller 12 is provided with a register in which data indicating an operation status (busy / idle, etc.) of the power supply controller 17 itself is set.

The main memory 13 stores an operating system, an application program to be processed, user data created by the application program, and the like. SMRAM (System M
The storage RAM) 50 is the main memory 1
3 is an overlay mapped to the address space from address 30000H to 3FFFFH,
Access is enabled only when a signal is input to the CPU 11. Here, the address range in which the SMRAM is mapped is not fixed, and can be changed to an arbitrary location in the 4 Gbyte space by a register called SMBASE. The SMBASE register cannot be accessed unless it is in SMM. The default value of the SMBASE register is address 3000H.

When the CPU 11 shifts to the SMM, C
PU status, ie the CPU when the SMI was generated
Eleven registers and the like are saved in the SMRAM 50 in a stack format. The SMRAM 50 includes a BIOS R
Instructions for calling the system management program of the OM 14 are stored. This instruction is issued by the CPU 11
This is the first instruction to be executed when the instruction is entered, and the execution of this instruction transfers control to the system management program.

The BIOS ROM 14 stores the system BIOS.
This is for storing S (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. The system BIOS is
It is configured to operate in the real mode. This system BIOS includes an I / O executed at system boot time.
An RT routine, a device driver for controlling various I / O devices, and a system management program are included. The system management program is an interrupt program executed in the SMM, and executes an interrupt process such as receiving the power status issued from the power controller 17 and storing the status in the CMOS memory of the real-time clock 16.

The bus conversion circuit 15 is a bridge device for connecting the CPU local bus 19 and the system bus 20, and has a bus width between the 32-bit data bus of the CPU local bus 19 and the 16-bit data bus of the system bus 20. Performs conversion, etc.

The real-time clock 16 is a clock module having a unique operation battery, and has a CMOS memory to which power is constantly supplied from the battery. This C
The MOS memory is used for storing setup information indicating a system configuration, power status information, and the like.

The power supply controller 17 controls the power supply circuit 18 to supply power to each unit in the system, and is constituted by a one-chip microcomputer. The power controller 17 includes a reset switch 21, a main power switch 22, and batteries (first battery BATT1, second battery BATT2).
23, AC adapter 24, display panel open / close detection switch 25, etc., that is, the power supply status.
, Brightness control of the speaker 27, volume control of the speaker 27, and the like.

The power supply controller 17 has two operation modes for communication with the CPU 11, that is, an event mode and a polling mode. These modes can be changed by a command from the CPU 11 or the like.

In the event mode, the power supply controller 17 monitors a change in the power supply status, and when the change in the power supply status is detected, sets the changed power supply status in the register 122. Thereafter, the power supply controller 17 stores the SMI generation instruction data in the register 123 so that the SMI generation circuit 121 generates an SMI signal.
Set to.

As described above, when the power supply controller 17 is in the event mode, every time the power supply status changes, the changed power supply status is transmitted to the CPU by the SMI signal.
11 is notified. The CPU 11 executes the system management program in response to the SMI signal, stores the power status of the register 122 in the CMOS memory, and returns to the interrupted program.

When it becomes necessary to read the power status, the CPU 11 reads the power status from the CMOS memory. The power status of the CMOS memory is also used for displaying the power status using a pop-up screen.

On the other hand, in the polling mode, the power supply controller 17 collects the requested power supply status in response to the status read request from the CPU 11 and sets it in the register 122. In this case, the process of setting the SMI generation instruction data to the register 123 is not performed, and no SMI signal is generated.

Note that even when the power supply controller 17 is in the event mode, when the CPU 11 issues a status read request, the power supply controller 17
The requested power status is set in the register 122 in the same manner as in the polling mode. Also in this case, SM
No I signal is generated.

FIG. 2 shows an example of a storage format of the power supply status in the CMOS memory. The power status received from the power controller 17 is stored in a storage position (index) of the CMOS memory corresponding to the type of the power status. That is, 8-bit power status information 1 is stored in the index 70 of the CMOS memory, 8-bit power status information 2 is stored in the index 71, and 8-bit power status information is stored in the index 71.

Bit 0 of the power status information 1 is a status (Received Low Battery) indicating that the battery 2 received from the power controller 17 is in a low battery state.
Power Off (LBI)).

Similarly, Bit 1 is set to the power controller 17
(Received Main SW Power Off) indicating that the main power switch 22 has been turned off,
t2 is a status (Received Panel Close Power Off) indicating that a power off request due to display panel closing received from the power supply controller 17 is generated, and Bit 3 is a return of an acknowledgment ACK to the power off sequence start command from the power supply controller 17. (Received Ack to CMD (91)) indicating the status, Bit7 is an acknowledgment ACK for another command from the power supply controller 17
Is used to store the status (Recived ACK) indicating that the is returned.

Bit 0 of the power status information 2 indicates the status (AC Adapter) received from the power controller 17 indicating the attachment of the AC adapter 24, and Bit 1 indicates that the first battery received from the power controller 17 is in the first low battery state. (1st Low Bat)
tery LBO) and Bit 2 are used to store a status (2stLow Battery LBO) received from the power supply controller 17 and indicating that the first battery is in the second low battery state.

Here, the first and second low battery states indicate the degree of decrease in the remaining battery capacity. In addition, the index 72 of the CMOS memory contains
The status (1st Battery Capacity) indicating the capacity of the first battery received from the power supply controller 17 and the index 73 indicating the remaining usage time of the first battery (1st Battery Capacity) received from the power supply controller 17.
Tim Value), an index 74 indicates a status (2nd Battery Capacity) indicating the capacity of the second battery received from the power supply controller 17, and an index 75 indicates a status indicating the remaining use time of the second battery received from the power supply controller 17. (2nd Battery Tim Value) is stored.

Next, the CPU 11 and the power supply controller 17
The types of commands transmitted and received between them will be described. CP
The command sent from the U11 to the power supply controller 17 is issued by the system BIOS or operating system executed by the CPU 11, and issues the following various commands for setting the mode of the power supply controller 17 and instructing operation. I do. (Command) (Command details) 40 Read SW status 41 Read PS microcomputer version (upper) Read 42 PS microcomputer version (middle) 43 Read PS microcomputer version (lower) 80 PS status read 91 Start power off sequence (Starts the same operation as when the power switch is pressed.) 9F Power off (power off immediately) A0 Enable power switch A1 Enable auto power off alarm A2 Disable auto power off alarm A5 Enable power-off by panel closing A6 Disable power-off by panel closing Extend waiting time for AC power-off command to 30 seconds B * Panel backlight control C0 (1st Battery) Battery level ( Upper (lead) lead C1 (1st Battery) Remaining battery (lower) lead C2 (1st Battery) Read remaining time calculation value C8 (2nd Battery) Read remaining battery (upper) C9 (2nd Battery) Read remaining battery (lower) CA (2nd Battery) Read remaining time calculation D * Set battery capacity E * Current coefficient setting during backup F0 Polling mode setting F1 Event mode setting FF ACK Further, the following command is sent from the power supply controller 17 to the CPU 11. (Command) (Content of command) (Cause command) 4 * SW status 40 4 * Version value 41,42,43 8 * PS status 80 90 Power off by LBI 91 Command 91 (Start of power off sequence) ACK 91 92 Panel Power off request by closing 98 Change speaker volume A * Battery level (upper) C0, C3 B * Battery level (lower) C1.C9 C * (1st Battery) remaining time calculation value C2 D * (2nd Battery) remaining Time calculation value CA FF ACK Among these commands, the command of the code of bit 7 = 0 is not the event data, so that no SMI is generated even in the event mode. On the other hand, the command of the code of bit 7 = 1, that is, the commands 8 * to 9 * are event data, and therefore, in the event mode, the power supply controller 1 automatically receives no command from the system.
7 and is notified to the CPU 11 by the SMI.

Note that data other than 8 * / 9 * is stored in the power controller 1 in a polling format even in the event mode.
7 to the CPU 11. Next, the procedure when the CPU 11 transfers a command to the power supply controller 17 is as follows.

Procedure 1. The power controller 17 is referred to by referring to the status register of the
Is not Busy. Procedure 2. Command transmission to power supply controller 17 Procedure 3. Within 25 ms (transmission 10 mS + reception 10 m
(S + margin) to confirm receipt of a response from the power supply controller 17. If reception is not possible within this time, retry from procedure 2 as timeout.

The response from the power supply controller 17 is CP
Depending on the type of command issued by U11, ACK, which is an acknowledgment, is returned from power supply controller 17 except when data is received from power supply controller 17 as in the status read.

Also, depending on the command, even if the command receives data from the power supply controller 17, actual data is transferred after the ACK is returned from the power supply controller 17.

Next, referring to the flowchart of FIG.
The operation procedure of the power supply controller 17 when transferring the power supply status from the power supply controller 17 to the CPU 11 will be described.

As described above, the power supply controller 17
Has two operation modes, an event mode and a polling mode. When the event mode is set (step S11), the power supply status such as the presence or absence of the AC adapter 24 and the remaining battery capacity is monitored. .

That is, the power supply controller 17 sequentially checks various power supply statuses (step S1).
2) It is checked whether or not the checked power supply status has changed from the previous state (step S13).
When there is a change in the power supply status, the power supply controller 17 sets the changed power supply status in the register 122 of the system controller 12 (step S14), and then sets the SMI generation data in the register 123 (step S15). .

On the other hand, when the polling mode is set (step S11), the power supply controller 17
When a read command for the power status such as the presence / absence of the adapter 24 and the remaining battery capacity is received (step S16), the power status requested by the command is checked (step S17), and it is stored in the register 122 of the system controller 12. It is set (step S18).

Next, referring to the flowchart of FIG.
The sequence when the power is turned on will be described. The power controller 17 is operating even when the system is in the power-off state (step S21). When the power switch 22 is turned on in this state, the power controller 17 controls the power circuit 18 to power on the system. (Step 22). At this time, the power supply controller 17 is operating in the polling mode.

The system BIOS includes a power controller 1
7 is issued, and the initial value of the power state is read from the power controller 17 (step S23). Then
The system BIOS issues a command for setting the operation of the power supply controller 17 in accordance with the setup information of the CMOS memory (steps S24 to S27), and thereafter issues an event mode command to set the power supply controller 17 to the event mode (step S24). S2
8).

As described above, the power supply controller 17 defines the polling mode as a default value.
It operates in the polling mode immediately after power-on. Therefore, execution of the power-on sequence is performed by the power controller 1
7 or a malfunction due to an SMI occurring before the system is ready for SMI processing can be prevented.

Next, referring to the flowchart of FIG.
The sequence when the power is turned off will be described. When the power switch 22 is turned off while the system is powered on, the power controller 17 issues a command indicating that the power switch is turned off (step S3).
1). At this time, the event mode is automatically switched to the polling mode in response to the turning off of the power switch.

The system BIOS executes processing to be performed before power-off such as suspend processing as necessary (step S32), and thereafter issues a power-off command to the power supply controller 17 (step S33). The power controller 17 controls the power circuit 18 to power off the system (step 34).

As described above, the power supply controller 17 automatically switches to the polling mode in response to the detection of the power switch being turned off. For this reason, even if the power status changes during the execution of the power-off sequence, no SMI is generated from the power supply controller 17, so that a trouble such as interruption of the power-off sequence can be prevented.

As described above, in this example, in the event mode, the power supply controller 17 monitors changes in various power supply statuses, and detects the occurrence of an event requiring power supply control, that is, the change in the power supply status. Then, the power status is set in the register 122. At this time, the SMI is supplied to the CPU 11, whereby the CPU 11 is notified that the power supply status has been set by the power supply controller 17.

As described above, in this system, the power status changed each time an event of power status change occurs is notified to the CPU 11 by the SMI.
It is not necessary for U11 to issue a command to power supply controller 17.

Therefore, the power supply controller 17
The power status can be efficiently transmitted to the PU 11. Since the power status sent from the power controller 17 is stored in the CMOS memory, the CPU 1
1 can obtain the latest power status whenever necessary.

Therefore, it is possible to efficiently prevent the occurrence of useless communication as compared with the related art in which the command transfer from the CPU 11 to the power supply controller 17 is required even when the power supply status has not changed.

Since the SMI is used as an interrupt signal to the CPU 11, the power supply status can be efficiently passed from the power supply controller 17 to the CPU 11 without affecting the running application program.

Further, the power supply controller 17 has two operation modes, an event mode and a polling mode similar to the conventional one, and the operation mode is configured to be programmable. For this reason, when the CPU 11 is executing an uninterruptable program such as an application program for high-speed communication, the power supply controller 17 is switched from the event mode to the polling mode.
It is possible to prevent problems such as the occurrence of a timeout error of the application program due to I.

In this embodiment, the case where the CPU 11 which has received the power status by the SMI saves the power status in the CMOS memory has been exemplified.
Instead of the PU 11 saving the power status in the CMOS memory by the SMI process, when the power status is received in the event mode, the hardware that automatically saves the power status to a dedicated register readable by the CPU 11 is provided in the system controller 12. And the CPU 11 may read the dedicated register to read the power supply status.

In this case, it is necessary to provide a dedicated register group corresponding to the indexes 70 and 71 of the CMOS memory in FIG. Further, if the power supply controller 17 itself is configured to select and designate a register to be set according to the type of power supply status, the address from the power supply controller 17 can be decoded without providing dedicated hardware, The power status can be set to the register corresponding to the power status only by providing an address decoder for selecting a register according to the decoding result.

By using such a method, even when an application program for performing high-speed communication is executed,
The power supply status can be received from the power supply controller 17 without interrupting the processing of the CPU 11 at all.

Further, the SMI issuance may be performed not only by setting the SMI issuance instruction data in the register 123 as in this embodiment, but also by another method. For example, the SMI can also be generated by configuring the SMI generation circuit 121 to automatically generate an SMI upon detecting that data is set in the register 122.

[0070]

As described above, according to the present invention, every time an event of a power status change occurs,
The changed power supply status is changed to C by the interrupt signal.
Since the notification is made to the PU, unlike the conventional polling communication, the CPU does not need to issue a command to the power supply controller. Therefore, the power supply status can be efficiently transmitted from the power supply controller to the CPU. Further, since the SMI is used, the CMI can be executed without affecting the running application program.
The PU can efficiently receive the power status from the power controller.

The power supply controller has two operation modes, an event mode and a polling mode, and the operation mode is configured to be programmable. Therefore, when the CPU is executing an uninterruptible program such as an application program for high-speed communication, the power supply controller is switched from the event mode to the polling mode. Inconveniences such as generation of trouble can be prevented.

Further, immediately after the system power is turned on or immediately before the system power is turned off, the power controller operates in the polling mode, so that the power-on sequence and the power-off sequence are interrupted by the interruption from the power controller. Can also be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to one embodiment of the present invention.

FIG. 2 is a view showing an example of a power supply status saved in a CMOS memory of the computer system of FIG. 1;

FIG. 3 is an exemplary flowchart for explaining the operation of a power supply controller provided in the computer system of FIG. 1;

FIG. 4 is an exemplary flowchart for explaining the power-on operation of the computer system shown in FIG. 1;

FIG. 5 is an exemplary flowchart for explaining an operation at the time of power off in the computer system of FIG. 1;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... CPU, 12 ... System controller, 13 ... Main memory, 14 ... BIOS ROM, 16 ... Real time clock, 17 ... Power supply controller, 18 ... Power supply circuit, 21 ... Reset switch, 22 ... Power (power) switch, 23 ... Battery , 24 ... AC adapter, 25 ...
Display panel open / close detection switch, 26: backlight, 27: speaker, 50: SMRAM.

Claims (3)

(57) [Claims] 1. A computer system having a CPU, various I / O units, and a power supply controller for controlling power supply to these units, wherein the computer system is provided between the CPU and the power supply controller, and is provided between the CPU and the power supply controller. A register in which various data to be transmitted and received are set, and a CPU informing that data is set in the register.
Interrupt from the power supply controller to notify
Means for generating an interrupt signal to the CPU in response to an instruction to generate a power signal, wherein the power supply controller responds to a mode setting request from the CPU.
The polling mode and event mode.
Set the system to one of the
The power supply in response to a power status indicating that the switch is off.
Mode setting to set the controller to polling mode
Means for setting a power status relating to power control of the computer system to the register in response to a status read request supplied from the CPU via the register in the polling mode; and monitor the various power status relating to the power management, setting data in the register indicating the altered power status when detecting a change in power status bets
Means for issuing an instruction to generate the interrupt signal . 2. A CPU, various I / O units, and
Power supply controller that controls power supply to these units
In a computer system having the power con
The controller operates various power supplies related to the power management of the computer system.
Monitor power status and detect changes in power status
An event occurrence detecting means that detects a change before the event is detected by the event occurrence detecting means.
The data indicating the power supply status is transmitted by the CPU.
First setting means for setting a predetermined readable register
And a status read request supplied from the CPU.
In response, the power related to the power control of the computer system is
Second setting means for setting a power source status in said register
And the power controller includes the event occurrence detecting means and
And an event mode in which the second setting means operates;
A polling mode in which the second setting means operates.
And a system that responds to turning on of the system power switch.
During the startup sequence, the system operates in the polling mode.
A computer system characterized by making. 3. The power supply controller according to claim 1 , wherein
System startup sequence in response to power switch on
Response to power down and system power switch off
Operates in the polling mode during the power-off sequence
3. The computer system according to claim 2, wherein
Tem.