JP3302023B2 - Signal synchronization device and image recording device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal synchronizer and an image recording apparatus. More specifically, the present invention relates to a signal synchronizer and an image recording apparatus that scans a photosensitive drum with a laser beam modulated with image data.

[0002]

2. Description of the Related Art An image recording apparatus using a laser beam is
A method is used in which a latent image is obtained by scanning a laser beam polarized by a polygon mirror on the surface of a photosensitive drum rotating at a constant speed, and then the image is recorded on paper through a process of development and fixing.

FIG. 7 shows a part of an image forming process of the image recording apparatus. In FIG. 1, reference numeral 18 denotes a beam detector, which is located on the scanning start point side where the laser beam scans the photosensitive drum 20, and obtains a synchronization signal (hereinafter, referred to as a BD signal) for synchronizing the transmission of image data.

[0004] Reference numeral 19 denotes a state in which the laser beam polarized by the polygon mirror scans the photosensitive drum 20.

When the character "AB" shown in FIG. 1 is to be recorded at a predetermined position on the paper, the data "AB" must be printed in synchronism with the position L from the beam detector 18 every time scanning is performed. . If the synchronization is not properly established, the character "AB" is recorded as a character distorted in the main scanning direction (the direction of rotation of the drum), resulting in deterioration of the character.

Generally, in order to prevent the deterioration of characters, for example, in a 300 dpi (dot / inch) laser beam printer, the synchronization accuracy of 1/8 of one dot (± 1/1) is used.
8 dots) is required.

FIG. 8 shows a BD synchronizing circuit for obtaining the above-mentioned synchronizing accuracy by the prior art. In the figure,
XL is a crystal oscillator, which cooperates with an oscillation circuit OSC,
Eight times the frequency of the image clock (frequency f ₀ ) for generating an image in dot units is obtained.

Reference numerals 24, 25, and 26 denote flip-flop circuits, each of which has a function of dividing each input clock by half. That is, when the reset terminals are in the reset release state, they cooperate to operate as a 1/8 frequency divider.

Reference numeral 23 denotes a flip-flop circuit, and BD
The signal is reset by a signal, and reset after the completion of transmission of image data for one scan.

Accordingly, when the flip-flop 23 is set at the rising edge of the BD signal from the reset state, the flip-flops 24, 25 and 26 are released from the reset state and start 1/8 frequency division in synchronization with the release point. .

Thus, a clock signal synchronized with the BD signal can be generated.

[0012]

However, the conventional synchronous circuit described above has the following disadvantages.

First, a basic clock having a frequency eight times the image clock frequency f ₀ is required to synchronize with the BD signal. For example, in a 300 dpi laser beam recording apparatus having a recording speed of 8 sheets per minute, the image clock frequency is about 2 MHz, and thus the basic clock frequency is 16 MHz. Since the clock frequency becomes higher in this way, it is difficult to take measures for EMI (prevention of unnecessary radiation noise).
There was an inconvenience that the cost for measures such as covering with a shield plate increased.

Secondly, a printing apparatus having a high printing speed, a printing apparatus having a printing density higher than 300 dpi, or increasing only the pixel density in the main scanning direction, for example, printing one dot of 300 dpi pixel in eight equal parts only in the main scanning direction In such a case, the image clock is further increased, and a synchronizing circuit cannot be formed with a normal TTL IC, so that ECL logic must be used. In some cases, it may even be impossible to implement a circuit even with ECL logic.

For example, in an 800 dpi laser beam recording apparatus having a recording speed of 8 sheets per minute, the image clock frequency is about 14 MHz and the basic clock frequency is about 11
2 MHz. In this case, the BD synchronization circuit exceeds the frequency limit (about 80 MHz to 100 MHz) of a normal TTL logic or CMOS logic, and a circuit cannot be constructed without ECL logic. As a result, circuit costs are increased, and inexpensive integration such as gate array cannot be performed.

Third, as a method for eliminating the above-mentioned inconvenience, a method of using a delay line and appropriately selecting a predetermined clock from clocks having various delay times can be considered. A sudden change in the waveform at the time of synchronization causes noise, or there is a problem that the image clock cannot be used for other functions due to a risk of malfunction.

Accordingly, an object of the present invention is to provide
It is an object of the present invention to provide a signal synchronizer and an image recording apparatus which can appropriately perform signal synchronization so that a phase of a clock signal to be output does not suddenly change when a synchronization signal is input. .

[0018]

To achieve the above object, a signal synchronizer according to the present invention comprises input means for inputting a basic clock signal, and delays the basic clock signal input by the input means. A circuit for generating a plurality of clock signals having mutually shifted phases, a selecting means for selecting one clock signal from the plurality of clock signals having mutually shifted phases, and a synchronizing signal. The previously selected clock based on what was entered
Select from signal to clock signal synchronized with the synchronization signal
When switching between the clock signals,
Shift operation to sequentially shift the selected clock signal.
The output from the selection means.
The selection means so that the phase of the
Control to switch to the synchronized clock signal.
And selection control means. here,
This signal synchronization device can be constituted by an integrated circuit. Further, an image recording apparatus according to the present invention is an image recording apparatus that scans a photosensitive drum with a laser beam modulated with image data. A signal synchronizer for generating a synchronized clock signal; the signal synchronizer having input means for inputting a basic clock signal; and delay means for delaying the basic clock signal input by the input means. A circuit for generating a plurality of clock signals having phases shifted from each other;
Selecting means for selecting one clock signal from the plurality of clock signals having mutually shifted phases; and a clock signal which has been selected based on the input of the synchronization signal.
Clock signal to a clock signal synchronized with the synchronization signal.
When switching the selection, among the plurality of clock signals,
Shift operation for sequentially shifting the selected clock signal
The output from the selection means is
The selection means so that the phase of the lock signal changes stepwise
To switch to the synchronized clock signal.
And selection control means for performing the selection.

[0019]

According to the present invention having the above-described structure, the selection has been made based on the input of the synchronization signal.
Clock signal synchronized with the synchronization signal
When switching selection to a signal, the plurality of clock signals
Shifts the clock signal selected from
Output from the selection means by performing the
So that the phase of the clock signal
Controlling the selection means to switch to the synchronized clock signal;
Replacement can be performed .

Specifically, according to the present invention, a clock signal synchronized with the BD signal can be obtained using a clock signal having the same frequency as the image clock frequency. In addition, since there is no sudden change in the selected image clock signal, there is an advantage that a hidden system can be used and the image clock signal can be used as another clock signal.

Of course, since a frequency higher than necessary is not used, the generation of a synchronizing signal can be performed without a significant increase in cost.

[0022]

Next, embodiments of the present invention will be described in detail.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, XL is a crystal oscillator, OSC generates a basic signal S ₀ of a predetermined frequency and there cooperating with an oscillation circuit. DLY is the delay control circuit generates a plurality of clock signals having a length of time when a predetermined with respect to the input signal S _0. DTC is a signal detection circuit, and a delay control circuit D
It has a function of detecting a delayed clock signal whose phase is closest to the BD signal among the delayed clock signals output from LY. If the corresponding delay clock signal cannot be detected, an error signal ER is generated.

SCON is an output signal control circuit, and BD
In response to the signal, a signal different from the currently output clock signal by one delay is sequentially selected and output.
When the delay clock signal specified by the TC is selected, the output is made constant.

[0025] By performing the above control, predetermined accuracy with respect to the BD signal (e.g., ± 1/8 of the fundamental signal S _o)
To obtain the synchronization signal S ₀ ′.

The oscillation circuit OSC and the delay control circuit DL
Y, signal detection circuit DTC, output signal control circuit SCON
Are all integrated into a single-chip IC.

FIGS. 2 and 3 show the detailed configuration and timing of the signal detection circuit DTC. In FIG. 2, reference numerals 1 to 8 denote flip-flops, which latch the delayed clock signals DS0 to DS7 at the rising edge of the BD signal. Reference numeral 9 denotes a logic circuit, which receives the latch signals L0 to L7 and follows the delay clock signals DS0 to DS according to the timing shown in FIG.
A signal having the phase closest to the BD signal is detected from S7. If no signal is detected, an error signal ER is generated.

Reference numeral 10 denotes a data holding unit which holds data SL0 to SL7 indicating the result of signal detection. The data to be retained is Fifo (First In Firsts) in which the first retained result of the previous result is output first.
t Out). When the power is turned on, the immediately preceding (n-1) th data is the result of detecting ADS0.

Reference numeral 11 denotes a bit arithmetic unit having a function of calculating a difference between the current (n-th) detection result and the immediately preceding detection result.

Reference numeral 12 denotes an encoder having a function of coding the result of the bit operation. Here, 0-7
The output is a 3-bit signal CD0 to CD2.

FIG. 4 is a detailed diagram of the output signal control circuit SCON. Here, reference numeral 13 denotes a shift enable signal generation circuit. Using the BD signal as a start signal, the code signal C output from the signal detection circuit DTC with respect to the signal DS0
A signal SFTEN that enables shifting by the number of clocks corresponding to the binary value indicated by D0 to CD2
Is output. The count of the numerical value is reset when it becomes 0 in the subtraction method.

Reference numeral 14 denotes a shift circuit, which outputs signals R0 to R7.
, One signal is “High” and all others are “Lo”.
w ". When the shift enable signal SFTEN is valid, it has a function of shifting the data of the signals R0 to R7 to the right or left in accordance with the clock signal DS0.

Reference numeral 15 denotes a signal selection circuit.
The ND gate is shown. This is the delay clock signal D
The clock specified by the signals R0 to R7 output from the shift circuit 14 is selected from S0 to DS7. Therefore, when the shift circuit 14 is operating, the clock signals are sequentially selected.

Reference numeral 16 denotes an OR circuit.
By performing a logical sum operation on the output of (1), a BD synchronization signal S ₀ ′ is output.

Note that the signals R0 to R7 are generated when the power is turned on.
Set to select DS0.

FIG. 5 shows the basic clock signal S ₀ , the BD signal, the shift enable signal SFTEN, the number of shifts Si
5 shows a timing chart of ft, BD synchronization signal S ₀ ′.

As described above, in this embodiment, the optimum delay clock is not selected and output immediately, but as is apparent from FIGS. 4 and 5, the shift enable signal SFT is used.
By sequentially selecting and outputting the delay clocks DS0 to DS7 from the time when the BD signal is input by the number of shifts designated by EN, the synchronization signal S0 finally synchronized with the BD signal is output.
You're getting. In addition, the wait clock for synchronizing with the BD signal is a maximum of seven clocks, and the distance l of the beam traveled during this period is sufficiently shorter than L shown in FIG. Signal S
0 '.

Next, another embodiment will be described.

FIG. 6 shows a second embodiment of the present invention.

This embodiment is different from the first embodiment in that the data holding unit 10, the bit operation unit 11, and the encoder 1
2. The shift enable generation circuit 13 is deleted, and a comparator 17 is added instead.

When a signal SL0 to SL7 indicating a new signal detection result is generated when the BD signal is input, the comparator 17 compares the signals R0 to R7 of the shift circuit 14 with the signals SL0 to SL7. R0 and SL0, R1 and SL1, and similarly R7 and SL7 are simultaneously compared, and a signal that enables the shift enable signal SFTEN is output until a match is found within a predetermined allowable range. Meanwhile, the shift circuit 14 outputs the signal R in accordance with the clock DS0.
By shifting the data of ₀ to R7, S ₀ ′ sequentially has different phases by one delay. Then, when the signal SL0~SL7 and R0~R7 matches, invalidates the shift enable signal SFTEN, by stopping the shift, it is possible to obtain the BD sync signal S ₀ '.

[0042]

As described above, according to the present invention, the selection is made based on the input of the synchronization signal.
From the clock signal that was synchronized
When switching the selection to the clock signal,
Shift the clock signal selected from the signals sequentially
By performing the shift operation,
So that the phase of the output clock signal changes stepwise
By controlling the selection means, the synchronized clock signal
Can be switched . Moreover, according to the present invention, the synchronization processing does not require an unnecessarily high frequency, so that even if the operation frequency of the apparatus becomes relatively high, signal synchronization can be performed without causing a significant increase in cost. .

Further, since the synchronization of the signals is not performed instantaneously, the system becomes concealed, so that unnecessary whiskers do not occur at the time of synchronization.

Further, the signal synchronizer according to the present invention
Since it can be configured on the IC of the chip, an effect that a large space is not required and the cost is eventually reduced can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a detailed diagram of the signal detection circuit shown in FIG.

FIG. 3 is a diagram showing a timing chart of the signal detection circuit shown in FIG. 1;

FIG. 4 is a detailed diagram of the output signal control circuit shown in FIG.

FIG. 5 is a diagram showing a timing chart of a BD synchronization signal S ₀ ′.

FIG. 6 is a diagram showing details of a signal detection circuit and an output signal control circuit as a second embodiment of the present invention.

FIG. 7 is a partial view of an image forming process using a laser beam.

FIG. 8 is a diagram showing a conventional example of BD signal synchronization.

[Explanation of symbols]

 XL crystal oscillator OSC oscillation circuit DLY delay control circuit DTC signal detection circuit SCON output signal control circuit 1 to 8 flip-flop circuit 9 logic circuit 10 data retainer 11 bit operation unit 12 encoder 13 shift enable signal generation circuit 14 shift circuit 15 signal Selection circuit 16 OR circuit 17 Comparator 18 Beam detector 19 Beam horizontal scanning 20 Photosensitive drum 21 Printing paper 22 Printing character 23 to 26 Flip-flop circuit

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N 1/04-1/207 H04N 1/23-1/31

Claims (3)

(57) [Claims] An input unit for inputting a basic clock signal; a delay unit for delaying the basic clock signal input by the input unit; a circuit for generating a plurality of clock signals having mutually shifted phases; Selecting means for selecting one clock signal from the plurality of clock signals having mutually shifted phases; selecting means based on the input of the synchronization signal ;
Synchronized with the synchronization signal from the clock signal
When switching the selection to a clock signal,
Clock signal selected from clock signals
The selecting means
The phase of the clock signal output from the device changes stepwise
The synchronous clock signal by controlling the selecting means as described above.
And a selection control means for switching to a signal. 2. The signal synchronizer according to claim 1, wherein the signal synchronizer is constituted by an integrated circuit. 3. An image recording apparatus which scans a photosensitive drum with a laser beam modulated with image data, comprising: a beam detector for detecting a laser beam to be scanned; and a clock signal synchronized with a detection signal of the beam detector. A signal synchronizer that generates a signal; the signal synchronizer has input means for inputting a basic clock signal; and delay means for delaying the basic clock signal input by the input means. A circuit for generating a plurality of clock signals shifted from each other, a selecting means for selecting one clock signal from the plurality of clock signals shifted from each other in phase, and Choice
Synchronized with the synchronization signal from the clock signal
When switching the selection to a clock signal,
Clock signal selected from clock signals
The selecting means
The phase of the clock signal output from the device changes stepwise
The synchronous clock signal by controlling the selecting means as described above.
An image recording apparatus, comprising: selection control means for switching to a signal.