JP3296588B2 - Inverter device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter device having at least one arm composed of first and second power switching elements connected in series between main power supply terminals, and more particularly to a high voltage side circuit. The present invention relates to an inverter device including a step-down level shift circuit having a high withstand voltage characteristic capable of transmitting a control signal to a low-voltage side circuit at a high speed.

[0002]

2. Description of the Related Art Conventionally, a first power switching element is provided on a high voltage side arm (hereinafter referred to as an upper arm) between main power supply terminals, and a low voltage side arm (hereinafter referred to as a lower arm).
And a second power switching element, respectively, and the first and second power switching elements
In the inverter device connected in series (serial connection), the first power switching element of the upper arm is driven in a state of floating with respect to a reference potential, and
A power supply insulated by a transformer is used for a drive circuit of the power switching element.

Recently, a photo-detector is provided between a low-voltage side circuit and a high-voltage side circuit, more specifically, between a low-voltage side first determination circuit and a high-voltage side driving circuit for the first power switching element. A boost level shift means comprising a coupler or the like;
A step-down level shift means comprising a photocoupler or the like is arranged between the monitor circuit of the first power switching element on the high voltage side and the second determination circuit on the low voltage side, and is provided by the step-up level shift means and the step-down level shift means. After performing electrical insulation between the low-voltage side circuit and the high-voltage side circuit, the first and second determination circuits confirm the switching state of the partner switching element between the first and second power switching elements. An inverter device for switching the switching element has been developed, and this type of inverter device is disclosed in, for example, JP-A-3-169273.

FIG. 11 is a block diagram showing an inverter device according to the above disclosure.

In FIG. 11, reference numeral 100 denotes a first power switching element, 101 denotes a second power switching element,
102 is a first drive circuit, 103 is a second drive circuit, 104
Are boost level shift circuits composed of photocouplers and the like, 10
5 is a step-down level shift circuit composed of a photocoupler and the like, 1
06 is a first determination circuit, 107 is a second determination circuit, 108 is a control device, 109 is a first monitor circuit, and 110 is a second monitor circuit.

The first power switching element 10
0 and the second power switching element 101 are the main power supply terminal 1
The first power switching element 100 belongs to the upper arm, and the second power switching element 101 belongs to the lower arm. The first power switching element 100 is switching-driven by a first drive circuit 102, and the second power switching element 10
1 is switching-driven by the second drive circuit 103. The first drive circuit 102 is a boost level shift circuit 1
The second drive circuit 103 is connected to the output of the second determination circuit 107 via the output circuit 04. A controller 108 is coupled to one input of the first and second decision circuits 106,107. The other input of the first determination circuit 106 is the second monitor circuit 1
The other input of the second determination circuit 107 is coupled to the output of the first monitor circuit 109 via the step-down level shift circuit 105. The first power switching element 100, the first drive circuit 102, the first monitor circuit 1
09 belong to the high voltage side circuit, and the rest belong to the low voltage side circuit.

The operation of the inverter device having the above configuration is as follows.
It is as described below.

The controller 108 supplies a command signal for alternately turning on / off the first power switching element 100 and the second power switching element 101 to one input of the first and second determination circuits 106 and 107, The first monitor circuit 109 and the second monitor circuit 110 monitor the ON / OFF state of the first and second power switching elements 100 and 101, respectively, and the monitor output of the second monitor circuit 110 is the other of the first determination circuit 106 Input to the first monitor circuit 1
The monitor output 09 is supplied to the other input of the second determination circuit 107 via the step-down level shift circuit 105. First
The determination circuit 106 receives a command signal for turning on the first power switching element 100 from the control device 108,
In addition, a drive signal is generated when a monitor output indicating that the second power switching element 101 is off is input from the second monitor circuit 110. This drive signal is boosted to an appropriate voltage level by the boost level shift circuit 104 and then supplied to the first power switching element 100 via the first drive circuit 102 to turn on the first power switching element 100. Let it. Also, the second determination circuit 107
From the control device 108 to the second power switching element 1
A drive signal is generated when a command signal for turning on 01 is input and a monitor output indicating that the first power switching element 100 is off from the first monitor circuit 109 is input. This drive signal is supplied to the second power switching element 101 via the second drive circuit 103, and turns on the second power switching element 101.

[0009]

In the inverter device, the high-voltage side circuit and the low-voltage side circuit are electrically insulated by the interposition of a step-up level shift circuit 104 and a step-down level shift circuit 105. Each of the boost level shift circuit 104 and the step-down level shift circuit 105 uses a photocoupler.

Although the photocoupler has a high withstand voltage characteristic, the signal response characteristic is relatively slow, so that the signal delay time is large, and the power consumption is large. There is a problem of giving. Although photocouplers having relatively fast signal response characteristics are commercially available, such a photocoupler has a problem that it is expensive.

On the other hand, it has already been proposed to use a level shift circuit composed of a high withstand voltage semiconductor element for a level shift circuit having a high withstand voltage characteristic even though it does not have a high insulation characteristic like a photocoupler. Since the level shift circuit according to the above proposal is constituted by a circuit composed of a semiconductor element, it can be integrated in one monolithic IC, and by this integration, a parasitic capacitance which causes a signal delay time is compared. Can be made smaller.
Further, in the level shift circuit according to the above proposal, if a MOSFET (field effect transistor) which consumes less current than a bipolar transistor is used as a switching element, power consumption can be considerably reduced. In the level shift circuit according to the above proposal, an N-channel MOSFET is used as a high withstand voltage switch as a high withstand voltage switch in view of driving means, in a boost level shift circuit for transmitting a signal from a low voltage side circuit to a high voltage side circuit. Conversely, a step-down level shift circuit that transmits a signal from a high-voltage side circuit to a low-voltage side circuit uses a P-channel MOSFET as a high withstand voltage switch.

However, also in the level shift circuit according to the above proposal, since a semiconductor element such as a high-voltage MOSFET is used as a high-voltage switch, the withstand voltage of the element is naturally limited. However, there is a problem that there is variation even in the same semiconductor element such as a high breakdown voltage MOSFET. In particular, when a P-channel MOSFET is used as a high breakdown voltage switch and it is integrated, a horizontal structure in which a current flows only near the surface of the MOSFET becomes difficult, and it is difficult to manufacture the MOSFET having high breakdown voltage characteristics. There is also a problem that it is difficult to realize a step-down level shift circuit for transmitting a signal from the high-voltage side circuit to the low-voltage side circuit.

An object of the present invention is to provide a step-down level shift circuit having a high withstand voltage characteristic, an excellent signal response characteristic, and a low power consumption characteristic. To provide an inverter device.

[0014]

In order to achieve the above object, the present invention provides an inverter having step-down level shift circuit means for transmitting a state detection signal detected by a high potential side control circuit to a low potential side control circuit. An apparatus, comprising first and second switch elements and a resistor in series between a high potential side control circuit and a low potential side control circuit, wherein the first switch element is a signal from the high potential side control circuit. On and off, the second switch element is turned on and off based on a change in the output voltage of the inverter device, and a voltage generated at the resistor when both the first and second switch elements are turned on. Means for transmitting the state detection signal to the low potential side control circuit.

[0015]

According to the above means, the step-down level shift means comprises:
It is constituted by a series circuit including first and second high withstand voltage switching elements. Preferably, the first high withstand voltage switching element is constituted by a P-channel MOSFET, and the second high withstand voltage switching element is constituted by an N-channel MOSFET. You. The first high withstand voltage switching element is turned on / off in response to a state detection signal to be transmitted, and the second high withstand voltage switching element is turned on only when the state detection signal is transmitted. The state detection signal is transmitted from the high voltage side circuit to the low voltage side circuit only when all of the second high withstand voltage switching elements are in the ON state. Further, since the first and second high-withstand-voltage switching elements are in the off state during a period in which the state detection signal is not transmitted, the high-withstand-voltage characteristics of one of the first and second high-withstand-voltage switching elements vary. There is, or even when the high withstand voltage characteristic is reduced due to fluctuations in temperature or the like, the high withstand voltage characteristic of the other high withstand voltage switching element can compensate for the variation or decrease in the high withstand voltage characteristic, No leakage current flows through the series circuit including the two first and second high-withstand-voltage switching elements.

As an example of transmitting the state detection signal, a case where an overcurrent state of a first power switching element is transmitted to a control apparatus as a state detection signal in a motor control inverter device will be described. When the state detection circuit on the high voltage circuit side detects an overcurrent state of the first power switching element, the state detection signal obtained by the detection immediately turns off the first power switching element and reduces the voltage level. Circuit first high-voltage switching element (N-channel type MOSFET)
Turn on T). At this time, when the first power switching element is turned off, the voltage at the output terminal of the inverter device suddenly decreases.
If a decrease in the voltage of the output terminal is detected and the second high withstand voltage switching element (P-channel MOSFET) of the step-down level shift circuit is turned on by the detected output, a state detection signal generated by the state detection circuit is generated. Accordingly, a detection current flows through the first and second high withstand voltage switching elements of the step-down level shift circuit, and a detection signal obtained by the detection current can be transmitted to the control device.

As described above, the step-down level shift circuit has a configuration in which the first and second high withstand voltage switching elements are connected in series, and the second high withstand voltage switching element is turned on only during the transmission of the state detection signal. As a result, the voltage applied to both ends of the first high withstand voltage switching element is reduced, and the load on the withstand voltage is reduced. Further, when the transmission of the state detection signal is not performed, since the first and second high-withstand-voltage switching elements are both off, for example, the high-withstand-voltage characteristic of one of the high-withstand-voltage switching elements deteriorates, Even when a leakage current starts to flow, the other high-voltage switching element blocks the leakage current, so that an increase in power loss due to the leakage current, breakage of a circuit, and the like do not occur, and high reliability is achieved. It is possible to obtain an inverter device having a characteristic.

Further, the operation state of the first power switching element in the upper arm can be grasped by the control device one by one by the state detection signal transmitted through the step-down level shift circuit. When the abnormality of the operation state of the first power switching element is detected, the operation mode of the second power switching element can be changed. Further, it is also possible to transmit the operating state of the first power switching element of the arm, which is grasped by the control device, to the outside.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the inverter device according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the inverter apparatus according to the present invention.

In FIG. 1, reference numeral 1 denotes a first power switching element, 2 denotes a second power switching element, 3 denotes a step-up level shift circuit, 4 denotes a step-down level shift circuit, 5 denotes a control device, and 6 denotes a high voltage of a main power supply. Side terminal, 7 is a low voltage side terminal of the main power supply, 8 is an output terminal, 9-1 is an upper arm side power supply, 9-2 is a lower arm side power supply, 10-1 and 10-2 are first power switching elements 1 Drive switches 10-3 and 10-4 are drive switches for the second power switching element 2, and 11-
Reference numeral 1 denotes an upper arm side driving device, 11-2 denotes a lower arm side driving device, 12-1 denotes an upper arm side state detecting device, 12-2 denotes a lower arm side state detecting device, and 13-1 denotes a first high withstand voltage switching element. , 13-2 are second high withstand voltage switching elements, 1
4-1 is the third high voltage switching element, 14-2 is the fourth high voltage switching element.
A high-withstand-voltage switching element 15; a driving device for the second and fourth high-withstand-voltage switching elements 13-2 and 14-2;
17 is an overvoltage protection Zener diode, 18 and 19 are output resistances of the step-up level shift circuit 3, 20 and 21 are gate circuits, 22 and 23 are switching elements, 24 and 25 are output resistances of the step-down level shift circuit 4, 26- 1 is a + or positive line of the upper arm side power supply 9-1, 26-2 is a-or negative line of the upper arm side power supply 9-1, 26-3
Is the + or positive line of the lower arm side power supply 9-2, 26
Reference numeral -4 denotes a negative or negative line of the lower arm side power supply 9-2.

The first and second power switching elements 1 and 2 are composed of, for example, insulated gate bipolar transistors (IGBTs), and are connected in a totem pole connection (series connection) between the main power supply terminals 6 and 7. Thus, one arm is formed. In the arm, the first power switching element 1 is arranged on the upper arm and the second power switching element 2 is arranged on the lower arm, and the connection point between the two power switching elements 1 and 2 constitutes an output terminal 8. I have. Driving switches 10-1 and 10-2 connected in series are connected to both ends of the upper arm side power supply 9-1.
The connection points -1, 10-2 are connected to the gate electrode G of the first power switching element 1. Lower arm side power supply 9-2
Are connected in series at both ends.
Are connected, and a connection point of these switches 10-3 and 10-4 is connected to the gate electrode G of the second power switching element 2. Both drive switches 10-1 and 10-2 are turned on / off by the output of the upper arm drive device 11-1, and both drive switches 10-3 and 10-4 are output by the output of the lower arm drive device 11-2. It is driven on / off. The-side line 26-2 of the upper arm side power supply 9-1 is connected to the output terminal 8
Is connected to the-side line 26-of the lower arm side power supply 9-2.
4 is connected to the low voltage side terminal 7 of the main power supply.

The boosting level shift circuit 3 includes two gate circuits 20 and 21 and two switching elements 22 and 2 made of, for example, a high breakdown voltage N-channel MOSFET.
3 and two output resistors 24 and 25, between the + side line 26-1 of the upper arm side power supply 9-1 and the − side line 26-4 of the lower arm side power supply 9-2. , A switching element 22 and an output resistor 24 and a series connection circuit of a switching element 23 and an output resistor 25 are arranged in parallel, and the outputs of the gate circuits 20 and 21 are connected to the gate electrodes G of the switching elements 22 and 23, respectively. . The inputs of the gate circuits 20 and 21 are connected to the control device 5, and the connection points of the switching element 22 and the output resistance 24 and the connection points of the switching element 23 and the output resistance 25 are connected to the upper arm side driving device 1.
1-1 is connected to the input.

Further, the step-down level shift circuit 4 includes a first
To the fourth high withstand voltage switching elements 13-1, 13-2,
14-1, 14-2, a driving device 15, two Zener diodes 16 and 17 for overvoltage protection, and two output resistors 18 and 19, and an upper arm side power supply 9-1.
The first high withstand voltage switching element 13 is provided between the + side line 26-1 and the − side line 26-4 of the lower arm side power supply 9-2.
-1, a second high-voltage switching element 13-2, an output resistor 18 in series with one series circuit, a third high-voltage switching element 14-1, a fourth high-voltage switching element 14-2, and an output resistor 19. And another series circuit consisting of a series connection of the above-mentioned is arranged, and Zener diodes 16 and 17 are connected in parallel to the first and third high withstand voltage switching elements 13-1 and 14-1, respectively. Drive circuit 1
5 is connected between the − side line 26-2 of the upper arm side power supply 9-1 and the − side line 26-4 of the lower arm side power supply 9-2, and its input is connected to the control device 5. The output of the drive circuit 15 is supplied to the second and fourth high withstand voltage switching elements 13.
-2, 14-2 are configured to be on / off controlled,
A second high withstand voltage switching element 13-2 and an output resistor 18,
Each connection point between the fourth high voltage switching element 14-2 and the output resistor 19 is connected to the input of the control device 5.

In addition, the upper arm side state detector 12-
Numeral 1 is connected to the upper arm side driving device 11-1 and configured to control on / off of the first high withstand voltage switching element 13-1 and the third high withstand voltage switching element 14-1. The detection device 12-2 is connected to the lower arm side drive device 11-2 and the control device 5.
Here, the upper arm side state detection device 12-1 has a function of separately detecting a plurality of detection factors in the operation state of the first power switching element 1, and the detection factors include an overcurrent state. , A gate voltage shortage state, a high temperature state, and the like. Then, the upper arm side state detection device 12-1
Has a predetermined judgment value for each of the detection factors, and when any one of the detection factors exceeds the judgment value, the logical state of the output signal of the upper arm side state detection device 12-1 changes. (For example, if the logical state in the normal state is at the high level, the signal goes to the low level if the judgment value is exceeded). Also, the upper arm side state detection device 12-1
Has a plurality of output terminals in order to distinguish a detection factor exceeding the determination value from other detection factors. In the illustrated example, two output terminals O ₁ and O ₂ are shown. . The state detection signals S ₁ , output from these output terminals O ₁ , O ₂ ,
S ₂ is the first high withstand voltage switching element 13-1 and the third high withstand voltage switching element 14 of the step-down level shift circuit 4.
-1, it is transmitted to the upper-arm driving apparatus 111, in the upper-arm drive device 11-1, that at least one among the output signals S _1, S ₂ exceeds the judgment value Is changed to the logical state representing the two drive switches 10 without waiting for the command signal from the control device 5.
-1, 10-2 so that the first power switching element 1 is immediately turned off. Similarly, the lower arm state detection device 12-2 has a function of individually detecting the plurality of detection factors in the operation state of the second power switching element 2, and the function thereof is the upper arm state. Although the function is exactly the same as that of the detection device 12-1, the state detection signals S ₁ and S ₂ from the lower arm side state detection device 12-2 are directly sent to the control device 5 without passing through the step-down level shift circuit 4. This is different from the upper arm side state detection device 12-1 in the point of transmission.

The inverter device having the above configuration performs the following operation.

The control device 5 converts a first on / off command signal for turning on / off the first power switching element 1 and a second on / off command signal for turning on / off the second power switching element 2. appear. The first ON and OFF command signals are supplied to the gate circuits 20 and 21 of the step-up level shift circuit 3, respectively, and the gate circuits 20 and 21 are switched in response to the supply of the first ON and OFF command signals. The elements 22 and 23 are selectively turned on and off, and the on current I
on, an off current Ioff is passed through the switching element 23 in a time-division manner. In this case, when the on-current Ion flows, an on-output voltage is generated across the output resistor 24, and this on-output voltage turns on the drive switch 10-1 via the upper arm drive circuit 11-1. (At this time, the drive switch 10-2 is in the off state.) Therefore, the first power switching element 1 is driven to the on state.
On the other hand, when the off current Ioff flows, the output resistance 2
5, an OFF output voltage is generated at both ends of the driving switch 10- via the upper arm driving circuit 11-1.
2 (at this time, the drive switch 10-1 is turned on).
Is in the off state), so that the first power switching element 1 is driven to the off state. In the above operation, it is desirable that the switching elements 22 and 23 be driven to the saturation region and that the values of the on-current Ion and the off-current Ioff be set as small as possible. The second ON and OFF command signals are directly supplied to the lower arm drive circuit 11-2. At this time, in response to the second ON command signal, the lower arm drive circuit 11-2 drives the lower arm drive circuit 11-2. 10-3 is turned on (at this time, the drive switch 10
-4 is in the off state) to drive the second power switching element 2 to the on state. On the other hand, in response to the second off command signal, the lower arm drive circuit 11-2 turns on the drive switch 10-4 this time (at this time, the drive switch 1
0-3 is in the off state), and the second power switching element 2 is driven to the off state.

By the way, the first power switching element 1
If the first and second power switching elements 1 and 2 are both in the off state before the power supply is turned on, the output terminal 8 in the off state is in the floating state and both ends of the main power supply If the voltage applied between the terminals 6 and 7 is E,
The voltage between the terminals 6 and 8 and the voltage between the terminals 8 and 7 are respectively E
/ 2, and the voltage applied to the switching elements 22 and 23 also becomes E / 2. At this time, when the first power switching element 1 is turned on, the voltage of the output terminal 8 becomes the same voltage E as the voltage E of the high voltage side terminal 6 of the main power supply, and the voltage applied to the switching elements 22 and 23 becomes E / 2 to E
However, if the switching elements 22 and 23 are operated in the saturation region, the values of the on current Ion and the off current Ioff do not depend on the increased voltage,
The constant value depends only on the gate voltage. Also,
In order to reduce the power consumption, the ON current Ion and the OFF current Ioff may be set as small as possible. As another means, a latch circuit is provided in the upper arm driving circuit 11-1, and the ON current Ion and the OFF current Ioff are provided. If the latch circuit is brought into a latched state by an output voltage obtained between both ends of the output resistors 24 and 25 based on the Ion and the off current Ioff, the on current Ion and the off current Ioff are cut off.
Power consumption can be further reduced.

Next, in the step-down level shift circuit 4, the state detection signals S ₁ and S ₂ obtained by the upper arm side state detection device 12-1 are converted into the first and third high withstand voltage switching elements 13-1, When the state detection signals S ₁ and S ₂ are in a normal logic state (for example, high level), the state detection signals S ₁ and S ₂ cause the first and third high withstand voltages. Switching elements 13-1, 14
-1 does not shift to the ON state, so that the ON / OFF states of the second and fourth high withstand voltage switching elements 13-2 and 14-2 are reduced.
Regardless of the off state, no detection signal is supplied from the output resistors 18 and 19 to the control device 5. Next, among the state detection signals S ₁ and S ₂ , for example, a detection factor (for example, an overcurrent detection output) corresponding to the state detection signal S ₁ exceeds the determination value, and the state detection signal If the logic state of S ₁ is being changed (changes to low level), the first high withstand voltage switching element 13-1 to the state detection signal S ₁ is supplied is turned on. Here, the first and third high-withstand-voltage switching elements 13-1 and 14-1 are driven by a P-channel MOSFET or a P-channel MOSFET such that the + side line 26-1 of the upper arm power supply 9-1 is driven with the reference potential. A PNP bipolar transistor is used. Further, the second and fourth high withstand voltage switching elements 13-2 and 14-2
Are simultaneously turned on or off by a drive signal from the drive device 15. The drive device 15 is supplied with the operation signal S 4 from the control circuit 5 and monitors between the two terminals 8 and 7. When the output voltage of the inverter device is in a predetermined state, a drive signal for turning on the second and fourth high withstand voltage switching elements 13-2 and 14-2 is output. If the first high withstand voltage switching element 13-1 is turned on as described above during the period in which the second high withstand voltage switching element 13-2 is in the on state, the first high withstand voltage switching element 13-1 and the second (2) A current flows through a series circuit including the high withstand voltage switching element 13-2 and the output resistor 18, and an output voltage generated across the output resistor 18 based on the current is transmitted to the control device 5 as a detection signal. The control device 5 can know that the above-described abnormality has occurred in the operation of the first power switching element 1 due to the supply of the power.

In the above case, the state detection signal S
The operation is performed when the detection factor corresponding to one of the state detection signals S ₁ exceeds the determination value in S ₁ and S ₂ .
Detection factors corresponding to the other state detection signal S ₂ (e.g.,
The operation when the gate voltage detection output) exceeds the determination value is exactly the same as the operation described above.

FIG. 2 is a block diagram showing a second embodiment of the inverter device according to the present invention. In particular, in this embodiment, the details of the driving device are shown.

In FIG. 2, 27-1 is an upper arm side main power supply, 27-2 is a lower arm side main power supply, 28-1 is an upper arm side reflux diode, 28-2 is a lower arm side reflux diode, 29-1 , 29-2 are switching elements, 30 is an output resistance, 31 is a bias resistance, 32 is a diode, 33
Is a load inductor such as a motor winding, etc.
Are denoted by the same reference numerals.

The upper arm-side main power supply 27-1 and the lower arm-side main power supply 27-2 are connected in series between the main power supply terminals 6 and 7, and the output terminal 8 and the two main power supplies 27-1 and 27-2 are connected. The load inductor 33 is connected to the connection point. First
The return diodes 28-1 and 28-2 are connected in parallel to the second power switching elements 1 and 2, respectively. The driving device 15 includes two switching elements 29-
1, 29-2, an output resistor 30, a bias resistor 31, and a diode 32.
Is, for example, a P-channel MOSFET, and the switching element 29-2 is, for example, an N-channel MOSFET. + Side line 26-3 and-of lower arm side power supply 9-2
Switching element 29-1, between side lines 26-4,
The output resistor 30 and the switching element 29-2 are connected in series, a bias resistor 31 is connected between the gate and the source of the switching element 29-1, and the gate of the switching element 29-1 and the-side line 26-4 are connected. The diode 32 is connected between them. Switching element 2
The connection point between 9-1 and the output resistor 30 is connected to the gate electrode of the second high withstand voltage switching element 13-2.

FIG. 3 is a signal waveform diagram showing signal waveforms of respective parts and supply timings in the second embodiment.

In FIG. 3, (a) shows an ON command signal (Son) waveform supplied to the boost level shift circuit 3,
(B) is the waveform of the state detection signal (S ₁ ) of the upper arm side state detection device 12-1, and (c) is the output signal (S
o) The waveform, (d) is the control signal (S ₄ ) waveform supplied to the gate of the switching element 29-2, and (e) is the drive signal (Sa) supplied to the gate of the second high withstand voltage switching element 13-2. (F) is a waveform of the detection signal (S _D1 ) obtained at both ends of the output resistor 18.

Here, the operation of this embodiment will be described with reference to the signal waveform diagram of FIG.

In this embodiment, as shown in FIGS. 3A and 3D, an ON command signal Son supplied from the control device 5 to the boosting level shift circuit 3 and a switching device 29 the control signal S ₄ which is supplied to the gate of -2 matched period, in the example of FIG. 3,
It is simultaneously supplied during the period from time t ₁ to time t _4.

First, at time t ₀ indicating the initial state,
On-command signal Son is not supplied (OFF command signal Soff is supplied), moreover, when the control signal S ₄ is not supplied in the same manner, since a first power switching element 1 is in the off state , The output signal So is in a low level state which is almost close to the ground potential. Moreover, since the state detection signal S ₁ is at a high level state, the first high withstand voltage switching element 13-1 is off, and,
Since the switching element 29-2 is in the off state, the drive signal Sa is at the high level of the voltage Va, and the second high withstand voltage switching element 13-2 is in the on state. Then, since the third switching element 13-1 is off,
No current flows through the output resistor 18, and the detection signal _SD1 is at a low level.

Next, at time t ₁ , the ON command signal S
If on and the control signal S ₄ are simultaneously supplied, the step-up level shift circuit 3 flows ON current Ion, the upper-arm driving circuit 11-1 drives the switch 10-1 based on the on-current Ion Since the first switching element 1 is turned on, the first power switching element 1 is turned on, and the output signal So of the voltage E is generated at the output terminal 8. When the switching element 29-2 is turned on, the drive signal Sa drops to a value lower than the voltage Va, and the second high voltage switching element 13-2 is turned off.
No current flows through 8 and the detection signal S _D1 maintains a low level.

Subsequently, the ON command signal Son and the control signal S
At time t ₂ in _{period 4} and is supplied at the same time, the upper-arm state detection circuit 12-1 detects the abnormal operation of the switching element 1 for the first power, the upper arm state detection circuit 12-1 converting the state detection signals S ₁ to low level. Next, this low-level state detection signal S ₁
Is being transmitted to the upper arm drive circuit 11-1 and the first high-voltage switching device 13-1, by the supply of the low level detection signal S _1, the upper arm drive circuit 4 of the ON command signal Son Despite the supply period, the first power switching element 1 is immediately switched to the off state, and the first high withstand voltage switching element 13-1 is switched to the on state. When the first power switching element 1 is turned off, the value of the output signal So becomes the first value.
Although swoop lower voltage from the voltage E at the time of the on-power switching element 1, after the dive, current I _L lower arm reflux diode which has been flowing to the load inductor 33 when the first on-power switching element 1 - Therefore, the voltage of the output signal So is higher than the voltage (ground potential) of the low voltage side terminal 7 of the main power supply by the voltage V _F (where V _F
Becomes a voltage (−V _F ) lower by the voltage between the terminals when the diode 28-2 is turned on. The diode 32 outputs the output signal S
The voltage o is reverse-biased during the period E and is in a cutoff state. However, when the voltage of the output signal So decreases to (−V _F ), the output signal So is turned on in a forward-biased state, and the voltage drops across the bias resistor 31. Occurs. Since this voltage drop forward biases the gate source of the switching element 29-1, the switching element 29-1 is turned on. At this time, since the switching element 29-2 is on, both the switching elements 29-1 and 29-2 are on, and the voltage Vcc of the lower arm side power supply 9-2 is applied to both ends of the output resistor 30. The voltage Vcc is supplied to the gate and the second high withstand voltage switching element 13-
2 turns on. When the second high withstand voltage switching element 13-2 is turned on, the first high withstand voltage switching element 13
-1 because already in the ON state by the supply of the output signals S ₁ of the low level, a current flows through both the high-voltage switching devices 13-1 and 13-2, the output resistance 18
Causes a voltage drop between both ends. Since this voltage drop changes the detection signal S _D1 from low level to high level,
By supplying the high-level detection signal S _D1 to the control device 5, the abnormal operation of the first power switching element 1 is notified from the upper arm side state detection circuit 12-1 via the step-down level shift circuit 4 to the control device 5. As a detection signal S _D1 .

The subsequent, at the time t _3, the state detection signal S ₁ output from the upper-arm state detection circuit 12-1 is changed to the high level, whereby the first high-voltage switching element 13-1 is turned off , The detection signal _SD1 also changes from the high level to the low level, but the first power switching element 1 is maintained in the off state, and the second high withstand voltage switching element 13-2 is maintained in the on state. ing.

Subsequently, at time t ₄ , the supply of the ON command signal Son and the control signal S ₄ is stopped at the same time.
3-2 is also turned off and returns to the initial state.

[0043] In the above operation, when the upper-arm state detection circuit 12-1 does not output a state detection signals S ₁ at the low level (outputs a high-level state detection signals S ₁₎ state , A series circuit composed of the first and second high withstand voltage switching elements 13-1 and 13-2 and the output resistor 18, a voltage (E + Vct) obtained by adding the voltage Vct of the upper arm power supply 9-1 to the output signal So voltage E. ) Is applied. At this time, since the first and second high-withstand-voltage switching elements 13-1 and 13-2 are both in the off state, the voltage (E + Vct) becomes the first and second high-withstand-voltage switching. This is applied to the elements 13-1 and 13-2 in a shared manner.
In this case, the first high withstand voltage switching element 13-1
Is lower than the high withstand voltage characteristic of the second high withstand voltage switching element 13-2, and the application of the voltage (E + Vct) causes the first high withstand voltage switching element 13-1 to be in a breakdown state (leakage current increases and current Even if the state shifts to a state where the interruption cannot be maintained), the first high withstand voltage switching element 1-2 is prevented from flowing due to the high withstand voltage characteristic of the second high withstand voltage switching element 13-2.
Since the voltage between terminals 3-1 can be maintained at a level lower than the breakdown voltage (applied voltage immediately before the leakage current increases), the applied voltage load on the first high withstand voltage switching element 13-1 can be reduced. In addition to the above, the loss caused by the leakage current and the applied high voltage (E + VCT) can be suppressed.

In each of the above-described embodiments, the detection factor of the operation state of the first power switching element 1 is one or two.
And the state detection signals S ₁ and S ₂ obtained from the upper arm side state detection device 12-1 are also one or two, but in each of the above examples, the operation state Is not limited to the number described above, but may be three or more. However, if the number of the detection factors of the operation state becomes three or more, the state detection signal S corresponds to the increase in the number.
Needless to say, it is necessary to increase the number of ₁ and S ₂ , and at the same time, increase the number of series circuits in the step-down level shift circuit 4.

In each of the embodiments described above, the example in which the IGBT is used for the first and second power switching elements 1 and 2 has been described. In each of the embodiments, the first and second power switching elements are used. 1 and 2 are not limited to the use of IGBTs, and other types of power switching elements can be used.

Further, in each of the above embodiments, the first
An example in which P-channel high-voltage MOSFETs are used for the third and third high-voltage switching elements 13-1 and 14-1, and N-channel high-voltage MOSFETs are used for the second and fourth high-voltage switching elements 13-2 and 14-2. As described above, in each of the above examples, each of the high withstand voltage switching elements 13
-1, 13-2, 14-1, and 14-2 are also the MOSFE
The invention is not limited to the use of T, and other types of high breakdown voltage switching elements can be used.

In each of the above embodiments, the structure of the step-down level shift circuit used in the single-phase inverter device is shown. If a step-down level shift circuit similar to the step-down level shift circuit is provided for each case, the same can be achieved.

By the way, in the multi-phase inverter device,
Providing a step-down level shift circuit for each phase not only complicates the configuration of the inverter device, but also increases the number of components used, so that a step-down level shift circuit suitable for a multi-phase inverter device can be provided. That is where it is sought.

FIG. 4 is a block diagram showing a third embodiment of the inverter device according to the present invention, which has a step-down level shift circuit suitable for a two-phase inverter device having both A and B phases. It is.

In FIG. 4, 1A is a first power switching element, 2A is a second power switching element, 3A is a boost level shift circuit, 8A is an output terminal, 9-1A is an upper arm side power supply, and 9-2A is Lower arm side power supply, 10-1
A, 10-2A is a drive switch of the first power switching element 1A, 10-3A, 10-4A is a drive switch of the second power switching element 2A, 11-1A is an upper arm side driving device, and 11-2A is Lower arm side drive device, 12
-1A is the upper arm side state detection device, 26-1A is the + or positive line of the upper arm side power supply 9-1A, 26-2A
Is the-or negative line of the upper arm side power supply 9-1A, 2
6-3A is a positive or positive line of the lower arm side power supply 9-2A, 28-1A is an upper arm side reflux diode, 28-A
2A is a lower arm side reflux diode, 35-1A, 35-
Reference numeral 2A denotes a control switch element, and each of the constituent elements indicates a constituent element of a circuit on the A-phase side.

1B is a first power switching element, 2B is a second power switching element, 3B is a boost level shift circuit, 8B is an output terminal, 9-1B is an upper arm side power supply, and 9-2B is a lower arm. Side power supply, 10-1B, 10
-2B is a drive switch of the first power switching element 1B, 10-3B, 10-4B is a drive switch of the second power switching element 2B, 11-1B is an upper arm side driving device, and 11-2B is a lower arm side. A driving device, 12-1B is an upper arm state detection device, 26-1B is a + or positive line of the upper arm power supply 9-1B, 26-2B is a-or negative line of the upper arm power supply 9-1B, 26-3B
Is the + or positive line of the lower arm side power supply 9-2B, 2
8-1B is an upper arm side freewheeling diode, 28-2B is a lower arm side freewheeling diode, 35-1B and 35-2B are control switch elements, and each of the above components is a component of a B-phase circuit. I have.

Further, 27 is a main power supply, 34 is an operation power supply of the step-down level shift circuit 4, 36-1, 36-2, 36-
Reference numerals 3 and 36-4 denote auxiliary switch elements, and 37-1 and 37-2.
Are inverter circuits, 38-1, 38-2, 38-3, 3
8-4 is a resistor, 39-1 and 39-2 are switching elements, 40 is a + side line of the power supply 34, and 41-1 is a main power supply 2
7 is a negative line of the high voltage side line and power supply 34, and 41-2 is a low voltage side line of the main power supply 27.
It is common to the phase side circuit and the B phase side circuit. In addition, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

The step-down level shift circuit 4 includes a + side line 40 of the power supply 34 and a low voltage side line 41 of the main power supply 27.
-2, the first high withstand voltage switching element 13-1, the second
One series circuit composed of a series connection of the high withstand voltage switching element 13-2 and the output resistor 18, a third high withstand voltage switching element 14-1, and a fourth high withstand voltage switching element 14-
2. Another series circuit comprising a series connection of the output resistor 19 is arranged, and the first and third high withstand voltage switching elements 13-1 and 14-1 comprising P-channel MOSFETs
, Switching elements 39-1 and 39-2 each formed of a P-channel MOSFET are also current mirror-connected. + Side line 40 and − side line 4 of power supply 34
1-1, a series circuit including the auxiliary switch elements 36-1 and 36-2 and the auxiliary switch elements 36-3 and 36-
4 is connected to the auxiliary switching element 3
6-1 and 36-2 are connected to both switching elements 13-.
Auxiliary switch element 36-3,
The connection point of 36-4 is connected to both switching elements 14-1, 39.
-2 gate. These auxiliary switch elements 36-1 to 36-4 are connected to the inverter circuits 37-1, 3-3.
It is configured to be turned on / off by the output of 7-2, and the inputs of the inverter circuits 37-1 and 37-2 are controlled switch elements 35-1A, 35-1B and 35-2, respectively.
A, 35-2B. The gate electrode of the second and fourth high-voltage switching devices 13-2,14-2 sampled signal S ₄ is supplied from the control unit 5, connected to the output resistor 18 and the second high withstand voltage switching element 13-2 A point and a connection point between the fourth high withstand voltage switching element 14-2 and the output resistor 19 are connected to the input of the control device 5.

The configuration of the circuit portion excluding the step-down level shift circuit 4 is the same in both the A-phase circuit and the B-phase circuit as in the first and second embodiments.

Here, the operation of the present embodiment will be described. The operation other than the operation related to the step-down level shift circuit 4, that is, the first operation of the A-phase side circuit is controlled by the control device 5.
And second power switching elements 1A, 2A and first and second power switching elements 1B, 2B of phase B side circuit
Is selectively switched on or off, and the operation of supplying the drive current to the load inductor 33 is almost the same as the operation of the above-described first or second embodiment. Is omitted.

Next, the step-down level shift circuit 4 of the present embodiment
The operation related to will be described.

Upper arm side state detectors 11-1A and 11-1B provided in the A-phase side circuit and the B-phase side circuit, respectively.
In the same manner as in the first or second embodiment, a plurality of detection factors in the operation state of the first power switching elements 1A and 1B, for example, abnormalities such as an overcurrent state, a gate voltage shortage state, and a high temperature state are detected. It has a function to detect each,
When the upper arm side state detectors 11-1A and 11-1B detect an abnormal value in any of the detection factors, they generate state detection signals S ₁ and S ₂ for each of the detection factors, and these state detection signals S ₁ , and supplies a common step-down level shift circuit 4 to S ₂ to the a-phase side circuit and the B-phase side circuit. In this embodiment, the reason why the common step-down level shift circuit 4 is provided for the A-phase side circuit and the B-phase side circuit is that the A-phase side first power switching element 1A and the B-phase side first power switching element This is because the possibility that the element 1B enters the abnormal operation state at the same time is extremely low. Thus, in the multi-phase inverter device, the step-down level shift circuit 4 common to each phase
Is provided, the circuit configuration of the inverter device is simplified, and the cost can be reduced.

Now, the upper arm side state detecting device 1 on the A-phase side
1-1A is an abnormal operation state of the first power switching element 1A, or an upper arm side state detection device 11-B side
1B detects an abnormal operation state of the first power switching element 1B, the state detection signals S ₁ , S
Either ₂ changes from high level to low level.
Here, for example, the upper arm side state detection device 11-
If the state detection signals S ₁ of 1A is changed to the low level, the state detection signals S ₁ of the low level is supplied to the arm drive unit 11-1A on the A-phase side, were it to the on state Change the drive switch 10-1A to the off state,
The first power switching element 1A is immediately turned off. The state detection signals S ₁ of the low level is also supplied to the control switch elements 35-1a, turning it. When the control switch element 35-1A is turned on, the input of the inverter circuit 37-1 goes low and the output of the inverter circuit 37-1 goes high at the same time.
-1 and 36-2 are both turned on, and the first high-voltage switching element 13-1 and the switching element 39-1 connected to the current mirror are both turned on. During this operation, the first high withstand voltage switching element 13-1 functions as a constant current switch.

[0059] At this time, the gate electrode of the second high-voltage switching element 13-2, a sampling signal S ₄ is supplied from the controller 5, a second high-voltage switching element 13-2 periodically turned on / Because it is turned off, the second
When the high breakdown voltage switching element 13-2 is turned on, the first high breakdown voltage switching element 13-1 and the second high breakdown voltage switching element 13-2 are simultaneously turned on. At this time, the first and second high breakdown voltage switching elements 13-1, 13-
2. Since a current flows through a series circuit including the output resistor 18 and a voltage drop occurs at both ends of the output resistor 18, a detection signal S _D1 due to the voltage drop is supplied to the control device 5.

As described above, also in the present embodiment, the state detection signal S obtained by the upper arm side state detection device 11-1A.
₁ is transmitted to the control device 5 as the detection signal S _D1 via the step-down level shift circuit 4. This operation is performed when another state detection signal S ₂ of the upper arm side state detection device 11-1A is set to the low level. The same applies to the case in which the state detection signal is obtained in another upper arm side state detection device 11-1B.

In this embodiment, the input of the inverter circuit 37-1 is connected to the A-phase control switch 35-1A.
And the B-phase control switch 35-1B, and the input of the inverter circuit 37-2 is also connected to the A-phase control switch 35-B.
2A and the phase B side control switch 35-2B, the step-down level in both the phase A upper arm side state detector 11-1A and the phase B upper arm side state detector 11-1B. The shift circuit 4 can be shared. In the present embodiment, the second and fourth high-voltage switching element 13-2,14-2 become selectively turned on by the application of the sampling signal S _4, respectively the first or third high-voltage switching element 13-1, 14
Since the current path through which -1 is to flow is interrupted, the power consumption is lower than that in the case where the second and fourth high withstand voltage switching elements 13-2 and 14-2 are always on. Can be reduced. Further, in the present embodiment, similarly to the above-described first and second embodiments, in the step-down level shift circuit 4, the first and second high withstand voltage switching elements 13-1, 13-2, and the third And fourth high withstand voltage switching elements 14-1 and 14-2
Respectively form a series circuit, so that the switching elements 13-1, 13-2, 14-1, and 14-2 can share the ratio of the applied voltage and reduce the high voltage burden.

FIG. 5 is a block diagram showing a fourth embodiment of the inverter device according to the present invention. In this embodiment, a charging device is used instead of the power supply 34 of the third embodiment. Things.

In FIG. 5, 42-1A and 42-2A are diodes, 43A is an auxiliary capacitor, and these components are those of the A-phase side circuit. Also, 42-1B and 42-2B are diodes, 43B is an auxiliary capacitor, and these components indicate components of the B-phase side circuit. Further, reference numeral 44 denotes a power supply charging capacitor, 45 denotes a positive or positive line of the power supply charging capacitor 44, and these components are components common to the A-phase side circuit and the B-phase side circuit. The same components as those shown in FIG. 4 are denoted by the same reference numerals.

In the A-phase side circuit, the + side line 45 of the power supply charging capacitor 44 and the lower arm side power supply 9-
A diode 42 is connected between the + A line 26-3A of 2A.
-1A and 42-2A are connected in series, and the upper arm side power supply 9
-1A-side line 26-3A and both diodes 42
An auxiliary capacitor 43A is connected between the connection points of -1A and 42-2A. In the B-phase side circuit,
+ Or negative line 45 of power supply charging capacitor 44
Diodes 42-1B and 42-2B are connected in series between the lower arm side power supply 9-2B and the + side line 26-3B, and the-side line 26-3B of the upper arm side power supply 9-1B and the both sides are connected. An auxiliary capacitor 43B is connected between the connection point of the diodes 42-1B and 42-2B. Further, as a common circuit between the A-phase side circuit and the B-phase side circuit, the + side line 45 of the power supply charging capacitor 44 and the main power supply 27 are connected.
Power supply charging capacitor 4 between the high voltage side line 41-1
4 are connected.

The operation of the present embodiment is substantially the same as the operation of the third embodiment except for the operation process in which the power supply charging capacitor 44 is charged. Therefore, the power supply charging capacitor 44 is charged here. Only the operation process will be described, and redundant description of other operations will be omitted.

First, in the A-phase side circuit, the first power switching element 1A and the second power switching element 2A
Are switched on / off complementarily to each other. When the first power switching element 1A is in the on state, the second power switching element 2A is in the off state, and conversely, the second power switching element 2A is in the off state. When the element 2A is on, the first power switching element 1A is on. However, in the switching operation, it is prohibited that the first power switching element 1A and the second power switching element 2A are turned on at the same time, but the first power switching element 1A and the second power switching The element 2A and the element 2A may be simultaneously turned off. Also in the B-phase side circuit, the first power switching element 1B and the second power switching element 2B
Is exactly the same as the switching operation of the first power switching element 1A and the second power switching element 2A on the A-phase side.

In this switching operation, when the second power switching element 2A is turned on in the A-phase side circuit, the lower arm side power supply 9-2A, the diode 4
A closed circuit including the 2-2A, the auxiliary capacitor 43A, and the second power switching element 2A is formed. The auxiliary capacitor 43A is supplied with the voltage Vcc of the lower arm side power supply 9-2A and charged to the polarity shown in the figure. Next, when the second power switching element 2A is turned off and the first power switching element 1A is turned on, the auxiliary capacitor 43A, the diode 42-1A, the power supply charging capacitor 44, the first power A closed circuit composed of the switching element 1A is formed, and the charge stored in the auxiliary capacitor 43A is supplied to the power supply charging capacitor 44 to be charged to the illustrated polarity.

On the other hand, also in the B-phase side circuit, when the second power switching element 2B is turned on, the lower arm side power supply 9-2B (not shown), the diode 42-2B, the auxiliary capacitor 43B, the second power supply Switching element 2B
Is formed, and the voltage Vcc of the lower arm side power supply 9-2B is supplied to the auxiliary capacitor 43B, and the auxiliary capacitor 43B is similarly charged to the illustrated polarity. Next, when the second power switching element 2B is turned off and the first power switching element 1B is turned on, the auxiliary capacitor 43 is turned off.
B, diode 42-1B, power supply charging capacitor 4
4. A closed circuit composed of the first power switching element 1B is formed, and the charge stored in the auxiliary capacitor 43B is supplied to the power supply charging capacitor 44 and charged in the illustrated polarity.

By repeating such a charging operation in the A-phase side circuit and the B-phase side circuit, two auxiliary capacitors 43A and 43B
Are supplied in a superposed manner with the same polarity. As a result, the charging voltage of the power supply charging capacitor 44 is reduced by two diodes 42 from the voltage Vcc of the lower arm side power supply 9-2A.
-1A, 42-2A and the voltage obtained by subtracting the ON voltages of the two power switching elements (IGBT) 1A, 2A,
Alternatively, the voltage is balanced by a voltage obtained by subtracting the on voltages of the two diodes 42-1B and 42-2B and the two power switching elements (IGBT) 1B and 2B from the voltage Vcc of the lower arm side power supply 9-2B. become.

This embodiment is slightly more complicated in circuit configuration than the third embodiment, but does not require an independent power supply 34, and is therefore advantageous for integration. The other effects of the present embodiment are the same as those of the third embodiment.

Also in the third and fourth embodiments, there are two factors for detecting the operating state of the first power switching elements 1A and 1B on the A-phase side and the B-phase side. -1A and 12-1B, the number of state detection signals is also two. However, the detection factors of the operation state are not limited to the above-mentioned number, but may be three or more. You can also. However, also in this case, if the number of the detection factors of the operation state becomes three or more, the number of the state detection signals also increases in accordance with the increase of the number, and at the same time, the number of It goes without saying that the number of series circuits and the like also need to be increased.

In the third and fourth embodiments, A
Although the example in which the IGBT is used for the first and second power switching elements 1A, 1B, 2A, and 2B on the phase side and the B phase has been described, the first and second power switching elements 1A are also used in the above-described example. , 1B, 2A, 2B are IGB
The use of T is not limited and other types of power switching elements can be used.

FIG. 6 is a layout diagram showing an example of an integrated circuit of the inverter device according to the present invention. In this example, a three-phase inverter comprising a U-phase, a V-phase, and a W-phase is shown. An apparatus is configured, and a step-down level shift circuit is provided for each phase.

In FIG. 6, 3U is a U-phase boost level shift circuit, and 3V is a V-phase boost level shift circuit.
W is a step-up level shift circuit on the W-phase side, 4U is a step-down level shift circuit on the U-phase side, 4V is a step-down level shift circuit on the V-phase side, 4W is a step-down level shift circuit on the W-phase side, 11-1.
U is a U-phase upper arm drive circuit, 11-1V is a V-phase upper arm drive circuit, 11-1W is a W-phase upper arm drive circuit, and 11-2U is a U-phase lower arm. Side drive circuit, 11-2V is the V-phase lower arm side drive circuit, 11-V
2W is a lower arm side drive circuit on the W phase side, 12-1U is an upper arm side state detector on the U phase side, 12-1V is an upper arm side state detector on the V phase side, and 12-1W is a W phase side upper side arm detector. Upper arm side state detector, 12-2U is U phase lower arm side state detector, 12-2V is V phase lower arm side state detector, 12-2W is W phase lower arm side state detector Device, 4
Reference numeral 6 denotes a semiconductor substrate, 47 denotes an insulator region, and other components that are the same as those shown in FIG.

The semiconductor substrate 46 includes the boost level shift circuits 3U to 3W and the step-down level shift circuits 4 of each phase.
U to 4W are alternately arranged via the insulator region 47, and the upper arm side drive circuit 11-
1U to 11-1W and upper arm side state detector 12-1
The combination with U to 12-1W is the insulator region 47, respectively.
And the combination of the lower arm side drive circuits 11-2U to 11-2W of each phase and the lower arm side state detectors 12-2U to 12-2W are respectively provided in the insulator regions 47. , And a portion where a common control circuit 5 is arranged for each phase. These portions are separated from each other by an insulator region 47 on the semiconductor substrate 46. It is formed as a monolithic power integrated circuit (IC).

In the above configuration, each of the step-down level shift circuits 4U to 4W is mainly constituted by a switching element composed of a semiconductor element, so that the upper arm side drive circuits 11-1U to 11-1W of each phase and the lower arm side With the drive circuits 11-2U to 11-2W, the boosting level shift circuits 3U to 3W for each phase, the control circuit 5, and the like, it becomes possible to form an integrated circuit on one semiconductor substrate 46.

FIG. 7 is a sectional view showing a part of a boundary region of each part in the arrangement diagram shown in FIG.

In FIG. 7, 48-1 is one part 49.
-1 is one semiconductor element, and 48-2 is another one semiconductor element formed in another part 49-2, and is otherwise the same as the constituent elements shown in FIG. Elements have the same reference numerals.

One portion 49-1 and another portion 49-2 are separated in an island shape by a dielectric region 47, and the semiconductor device 48 is connected to the one portion 49-1.
-1 is the semiconductor element 48 in the other portion 49-2.
-2 is formed.

Generally speaking, island-shaped portions 49-1, 4-4 separated by a dielectric region 47 are formed in a semiconductor substrate 46.
Although it is already known to provide 9-2,
In this example, a circuit having a high withstand voltage characteristic and operating in a floating potential state is integrated by using this known means. Specifically, in the case of this example, the above-mentioned step-down level shift circuits 4U to 4W are replaced by state detection circuits 12-1U to 12-1W for generating a state detection signal and a control circuit to which the state detection signal is transmitted. 5, the parasitic capacitance of each element formed in each circuit can be reduced, and the delay time for transmitting the state detection signal can be greatly reduced. .

FIG. 8 is a schematic diagram showing a three-phase inverter device using the monolithic power IC shown in FIG.

In FIG. 8, reference numeral 50 denotes a monolithic power IC, reference numeral 51 denotes a microcomputer, reference numerals 52U, 52V, and 52W denote current detection devices, and other components which are the same as those shown in FIG.

Then, the monolithic power IC 50 is
Step-up level shift circuits 3U to 3W of each phase, step-down level shift circuits 4U to 4W, upper arm side drive circuits 11-1U to 11-1W of each phase, and lower arm side drive circuits 11-2U to 11-2U of each phase 11-2W, upper-arm state detectors 12-1U to 12-1W for each phase, lower-arm state detectors 12-2U to 12-2W for each phase, and a control circuit 5 common to each phase. And is connected to an external microcomputer 51 via various connection terminals. In this case, the current detection devices 52U, 52V, and 52W correspond to the state detection circuits 12-1U, 12-1V, 1
It has a configuration corresponding to 2-1W.

In the above configuration, the output current of each phase of the inverter device is detected by the current detecting devices 48U, 48V, 48W, and the detected output is supplied to the microcomputer 51. Next, the microcomputer 51 supplies a control signal corresponding to the detection output to the monolithic power IC 50, and the monolithic power IC 50 sets the operation mode of the inverter device in each arm in accordance with the control signal. It is.

Next, FIG. 9 is a system diagram showing an operation sequence when the operation mode of the monolithic power IC is changed in the three-phase inverter device of FIG.
In FIG. 7, the same components as those shown in FIGS. 6 and 8 are denoted by the same reference numerals. Then, the step-down level shift circuits 4U, 4V, and 4W of each phase provide two state detection signals S for each phase as described in the first embodiment.
₁ , S ₂ and correspondingly two detection signals S _D1 ,
S _D2 is transmitted to the control device 5.

In the above configuration, for each phase circuit in the step-down level shift circuits 4U, 4V and 4W, for example, the step-down level shift circuit 4U controls four operating states as a combination of two detected states. It can be transmitted to the device 5. That is, when the detection signal S _D1 is at a high level and the detection signal S _D2 is at a low level, the detection signal S _D1 is at a low level, and when the detection signal S _D2 is at a high level, the detection signals S _D1 and S _D2 are at a high level. Is the case where the detection signals S _D1 and S _D2 are at the low level. In these cases, the case of indicates that there is no abnormal operation, so in the remaining cases, three detection factors (the cause of the abnormal operation of the first power switching element 1U,
For example, if an overcurrent state, a gate drive voltage shortage state, a high temperature state, and the like are sorted, the detection factors can be detected individually.

First, the control circuit 5 checks which one of the above four cases or not based on the level state of the detection signals S _D1 and S _D2 transmitted from the step-down level shift circuit 4U. After identifying which of the three detection factors corresponds, and after identifying the detection factors, one of the two systems is processed as described below.

One process of the above system is to set a pause period for an arm in which an operation abnormality has occurred or another arm in accordance with the content of the operation abnormality that has occurred. For example, if the identified detection factor is an overcurrent state during the suspension period, only the arm in which the operation abnormality has occurred is turned off, and the other arms are connected to the external microcomputer 51.
The operation is performed according to the operation mode instructed from. On the other hand, if the detection factor is a high temperature state, all the arms are turned off and the off state is continued during the pause period.

The other processing of the system is to convert the signal into a detection factor identification signal that can be identified by the microcomputer 51 in accordance with the identified detection factor, and to transmit the signal to the microcomputer 51. In this case, there are various types of detection factor identification signals that can be identified by the microcomputer 51, and among the types of signals that require only one input port of the microcomputer 51, the detection factor identification signal corresponds to the detection factor. In this case, the pulse width of the detection factor identification signal is changed, or the number of pulses of the detection factor identification signal is changed.

FIGS. 10A and 10B are signal waveform diagrams showing an example of the relationship between the detection factor and the detection factor identification signal. FIG. 10A is a diagram in which the pulse width is changed, and FIG. 10B is a diagram in which the number of pulses is changed. It is.

That is, as shown in FIG. 10A, when the detection factor is in the overcurrent state, the width is equal to the cycle of the clock signal, and when the detection factor is in the high temperature state, the width is twice the cycle of the clock signal. When the detection factor is a gate drive voltage shortage state, a detection factor identification signal having a width three times as long as the cycle of the clock signal is generated, or as shown in FIG. One pulse equal to the clock signal when in the overcurrent state, two pulses equal to the clock signal when the detection factor is in the high temperature state, and four pulses equal to the clock signal when the detection factor is in the gate drive voltage shortage state. The microcomputer 51 generates a detection factor identification signal. When the detection factor identification signal is supplied, the microcomputer 51 uses an internal counter to perform the detection. Determining the difference in factors identification signal with, so that easily perform identification of the detected factors.

Next, the microcomputer 51 sets the operation mode of the inverter device after the suspension period according to the detection factor by identifying the detection factor identification signal. In this case, as described above, the operation state during the suspension period is different depending on the detection factor. For example, if all the arms are in the off state, the load becomes the load. The motor 33 continues to rotate in a free running state. When the suspension period ends, it is necessary to select whether to continue the operation of the motor 33 or to stop and restart the motor 33 once.
When the selection is made, the operation is restarted in accordance with an appropriate operation mode in consideration of the content of the detected detection factor or the length of the suspension period.

By detecting an operation abnormality occurring in the inverter device and transmitting a detection signal corresponding to the detection to an external microcomputer, the microcomputer stops or operates the inverter device. The control means for making such a determination is known, and in this known control means, all of the control relating to the inverter device is performed by the microcomputer.

On the other hand, in the inverter device according to the present embodiment, the control device 5 built in the inverter device independently performs processing such as setting of a suspension period corresponding to the content of the generated operation abnormality. That is, the processing at the time of an abnormal operation is performed locally on the inverter device side.

[0095] Also, coupling means for coupling between the inverter device and the microcomputer using a photocoupler is known. In this case, the purpose of using the photocoupler in the known coupling means is to transmit a signal between the high-voltage circuit and the low-voltage circuit as in the case of the present embodiment, and to connect the signal circuit unit and the high-power unit. Electrical insulation between them. Here, in the inverter device including the boosting level shift circuit 3 and the step-down level shift circuit 4 according to the present embodiment, a photocoupler is not required for the signal transmission only, but a photocoupler is required for electrical insulation. become. Therefore, if a photocoupler is provided in this embodiment, the terminals U, V, and W shown in FIG. 9 and the terminals of the microcomputer 51, and the output terminal of the detection factor identification signal and the terminal of the microcomputer 51 shown in FIG. According to this embodiment, the control device 5 on the inverter device side performs a process at the time of an abnormal operation and adopts only the content of the abnormal operation as a detection factor identification signal through the photocoupler. To be transmitted.

On the other hand, the photocoupler has a delay in signal transmission, and if all the processing at the time of an abnormal operation is performed via the microcomputer 51 as in the known control means, it takes a long time for the processing. Will be too long. However, in the present embodiment, since the processing at the time of the abnormal operation is performed in the control device 5 on the inverter device side, the time required for the processing at the time of the abnormal operation is reduced.

In this embodiment, when the detection factor identified by the control device 5 is transmitted to the microcomputer 51 as a detection factor identification signal, a detection factor identification signal that requires only one input port of the microcomputer 51 is used. For example, the number of photocouplers used can be reduced, and cost reduction can be realized by reducing the number of parts.

[0098]

As described above, according to the present invention,
Step-down level shift circuit 4 provided in inverter device
Are the first and second high withstand voltage switching elements 13-1, 1
3-2. The first high-voltage switching element 13-1 responds to the output signal of the state detection means 12-1 and controls the state detection signal _SD1 from the series circuit. 5 is supplied.

In this case, the step-down level shift circuit 4
Does not include a photocoupler for delaying a signal inside, and therefore has an effect that the output signal of the state detecting means 12-1 can be transmitted to the control device 5 without delay.

The step-down level shift circuit 4 includes a first and a second high withstand voltage switching element 13-1,
13-2. In this case, even if the high withstand voltage characteristics of the first and second high withstand voltage switching elements 13-1 and 13-2 vary, the reduction of the high withstand voltage characteristic of one of the switching elements decreases. Is compensated by the high withstand voltage characteristic of the other switching element, so that the applied voltage burden on both switching elements is reduced, so that the occurrence of leakage current is suppressed and the power loss generated by the applied high voltage is reduced. There is an effect that it can be suppressed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of an inverter device according to the present invention.

FIG. 2 is a configuration diagram showing a second embodiment of the inverter device according to the present invention.

FIG. 3 is a signal waveform diagram for explaining the operation of the second embodiment.

FIG. 4 is a configuration diagram showing a third embodiment of the inverter device according to the present invention.

FIG. 5 is a configuration diagram showing a fourth embodiment of the inverter device according to the present invention.

FIG. 6 is a layout diagram illustrating an example of a case where an inverter device according to the present invention is configured by an integrated circuit.

7 is a cross-sectional configuration diagram showing a part of a boundary region of each part in the arrangement configuration diagram of FIG. 6;

FIG. 8 is a diagram showing a configuration 3 using the monolithic power IC of FIG. 6;
It is a schematic block diagram which shows a phase inverter device.

FIG. 9 is a system diagram showing an operation sequence when the monolithic power IC changes its operation mode in the three-phase inverter device of FIG. 8;

FIG. 10 is a signal waveform diagram illustrating an example of a relationship between a detection factor and a detection factor identification signal.

FIG. 11 is a block diagram showing an example of a conventional inverter device.

[Explanation of symbols]

1 (A, B, U) First power switching element 2 (A, B, U) Second power switching element 3 (A, B, U, V, W) Step-up level shift circuit 4 (U, V, W) Step-down level shift circuit 5 Control device 6 High voltage side terminal of main power supply 7 Low voltage side terminal of main power supply 8 Output terminal 9-1 (A, B, U) Upper arm side power supply 9-2 (A, B, U) Lower arm side power supply 10-1 (A, B), 10-2 (A, B), 10-3
(A, B), 10-4 (A, B) Drive switch 11-1 (A, B, U, V, W) Upper arm side drive circuit 11-2 (A, B, U, V, W) Lower Arm side drive circuit 12-1 (A, B, U, V, W) Upper arm side state detection circuit 12-2 (U, V, W) Lower arm side state detection circuit 13-1 First high withstand voltage switching element 13 -2 Second high voltage switching element 14-1 Third high voltage switching element 14-2 Fourth high voltage switching element 15 Driving device 16, 17 Overvoltage protection Zener diode 18, 19, 24, 25, 30 Output resistance 20, 21 Gate Circuit 22, 23, 29-1, 29-2 Switching Element 26-1 + or Positive Line of Upper Arm Power Supply 9-1 26-2-or Negative Line of Upper Arm Power Supply 9-1 26- 3 Lower arm side + Or positive line of source 9-2 26-4-or negative line of lower arm side power supply 9-2 27 main power supply 27-1 upper arm side main power supply 27-2 lower arm side main power supply 28-1 (A , B, U) Upper arm side reflux diode 28-2 (A, B, U) Lower arm side reflux diode 29-1, 29-2, 39-1, 39-2 Switching element 31 Bias resistor 32 Diode 33 Motor winding Load inductors such as wires 34 Operating power supply for step-down level shift circuit 4 35-1 (A, B), 35-2 (A, B) Control switch elements 36-1, 36-2, 36-3, 36-4 Auxiliary Switch element 37-1, 37-2 Inverter circuit 38-1, 38-2, 38-3, 38-4 Resistance 40 Positive or positive line 41-1 of main power supply 27 − Alternatively, the negative side line 41-2 The low voltage side line 42-1 (A, B), 42-2 (A, B) of the main power supply 27 Diode 43 (A, B) Auxiliary capacitor 44 Power supply charging capacitor 45 Power supply charging capacitor 44 hot side line return diode 46 semiconductor substrate 47 dielectric region 48-1, 48-2 semiconductor element 49-1, 49-2 part of semiconductor substrate 46 50 monolithic power integrated circuit (IC) 51 microcomputer 52 (U, V , W) Current detection device

──────────────────────────────────────────────────の Continuation of the front page (72) Inventor Koichi Suda 3-1-1 Sachimachi, Hitachi-shi, Ibaraki Pref. Hitachi, Ltd. Inside the Hitachi Plant (56) References JP-A-2-164267 (JP, A) Kaihei 3-169273 (JP, A) Japanese Utility Model Hei 2-49389 (JP, U) (58) Field surveyed (Int. Cl. ⁷ , DB name) H02M 7/538

Claims (3)

(57) [Claims] 1. An inverter device comprising a step-down level shift circuit means for transmitting a state detection signal detected by a high potential side control circuit to a low potential side control circuit, wherein the high potential side control circuit and the low potential side control circuit are provided. Between the first and second
The first switch element is turned on and off by a signal from the high-potential side control circuit, and the second switch element is turned on and off based on a change in the output voltage of the inverter device. An inverter device which turns off and transmits the state detection signal to the low potential side control circuit with a voltage generated at the resistor when both the first and second switch elements are turned on. 2. An inverter device comprising step-down level shift circuit means for transmitting a state detection signal detected by a high potential side control circuit to a low potential side control circuit, wherein the high potential side control circuit and the low potential side control circuit are provided. Between the first and second
The first switch element is turned on and off by a signal from the high potential side control circuit, and the second switch element is based on a sampling signal given from the low potential side control circuit. An inverter device that turns on and off and transmits the state detection signal to the low-potential side control circuit with a voltage generated at the resistor when both the first and second switch elements are turned on. 3. The step-down level shift circuit means according to claim 1, wherein a withstand voltage of said first switch element is lower than a DC power supply voltage of said inverter device, and a voltage clamp is provided in parallel with said first switch element. Means, and a withstand voltage of the second switch element is higher than a DC power supply voltage of the inverter apparatus.