JP3296229B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method suitably applied to a MOS transistor.

[0002]

2. Description of the Related Art Hitherto, in order to ensure the performance and reliability of LSI elements, there has been a demand for improving the breakdown voltage and life of a gate oxide film constituting a MOS transistor. As one method for this, thermal oxidation called sacrificial oxidation (temporary oxidation) is performed on the surface of the silicon substrate before forming the gate oxide film, and a residual stress layer on the surface of the silicon substrate is formed.
Removal of a contaminated layer, a defective layer, and the like has been performed (for example, JP-A-56-103425, JP-A-59-1).
No. 94473).

[0003]

However, this sacrificial oxidation has a direct effect on the contaminant layer and the defect layer existing on the surface of the silicon substrate. The effect is not sufficient for metal contaminants that sometimes diffuse heat in silicon to near the surface. That is, for example, in the case of Fe,
By raising the temperature during the gate oxidation, the silicon is dissolved in the silicon up to the saturation concentration at that temperature, and the Fe dissolved in the silicon diffuses into the gate oxide film.

Accordingly, an object of the present invention is to reduce the concentration of contaminants in a silicon substrate, which generally causes a reduction in the breakdown voltage of an oxide film, and to reduce the concentration of contaminants eluted in the oxide film when the oxide film is subsequently formed. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be used.

[0005]

Means for Solving the Problems It is possible to suck out Fe and the like in silicon by capturing metal contaminants (Fe and the like) in the sacrificial oxide film at the time of the sacrificial oxidation. Considering the saturation temperature, in the sacrificial oxidation at a temperature significantly lower than the oxidation temperature (eg, gate oxidation) for forming the insulating film, Fe present in silicon is sufficiently contained in the sacrificial oxide film. When oxidation for forming an insulating film (for example, gate oxidation) is performed after removing the sacrificial oxide film, contaminants remaining without being removed at the time of sacrificial oxidation remain in silicon and the oxide film. A large amount of the oxide film is dissolved and the quality of the oxide film is deteriorated. For this reason, in sacrificial oxidation at a temperature significantly lower than the insulating film formation temperature (for example, gate oxidation temperature), metal contaminants (Fe
Etc.), a sufficient removal effect cannot be obtained.

[0006]

[0007]

Therefore, in the first aspect of the present invention, prior to forming a thin oxide film as an insulating film on a silicon substrate, a field oxide film is formed on the silicon substrate. After a film forming step, a sacrificial oxide film is formed by thermal oxidation at a temperature lower than the formation temperature of the oxide film in the formation region of the oxide film of the thin film, and the temperature is equal to or higher than the formation temperature of the thin oxide film as the insulating film. Is performed at a high temperature. Then, the sacrificial oxide film after the annealing is removed.

Therefore, by forming the sacrificial oxide film, the residual stress layer and the residual foreign matter on the surface of the silicon substrate can be taken in, and can be eliminated by removing the sacrificial oxide film. Further, by performing annealing at a high temperature equal to or higher than the formation temperature of the thin oxide film as the insulating film, contaminants existing deep in the silicon surface can be sucked into the sacrificial oxide film. As a result, the concentration of a contaminant in the silicon substrate that causes a decrease in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film when the oxide film is subsequently formed can be reduced.

According to the second aspect of the present invention, prior to forming a thin oxide film as an insulating film on a silicon substrate, the oxide film is formed in a region where the oxide film is formed at a temperature lower than the formation temperature of the oxide film. A first sacrificial oxide film is formed by thermal oxidation of the silicon substrate, and contaminants left in the silicon substrate are deposited near the silicon interface. Annealing is performed. Then, the sacrificial oxide film after the annealing is removed to expose the silicon substrate. Further, in order to take in the contaminants deposited near the silicon interface, a second sacrificial oxide film is formed by thermal oxidation at a temperature lower than the temperature at which the oxide film is formed in the region where the thin oxide film as the insulating film is formed. Then, the second sacrificial oxide film is removed.

Therefore, by forming the first sacrificial oxide film,
The residual stress layer and residual foreign matter on the surface of the silicon substrate can be taken in and removed by removing the first sacrificial oxide film.
Further, by performing annealing at a high temperature equal to or higher than the formation temperature of the thin oxide film as the insulating film, contaminants existing deep in the silicon surface can be sucked into the sacrificial oxide film.
As a result, the concentration of a contaminant in the silicon substrate that causes a decrease in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film when the oxide film is subsequently formed can be reduced.

Further, by forming a second sacrificial oxide film,
By taking in residual contaminants on the surface of the silicon substrate, the second
This can be eliminated by removing the sacrificial oxide film. That is,
Contaminants that do not dissolve in the oxide film tend to precipitate at the SiO ₂ / Si interface by annealing, but according to the present invention, the contaminants can be reliably removed.

According to the third aspect of the present invention, prior to forming a thin oxide film as an insulating film on a silicon substrate, the oxide film is formed in a region where the oxide film is formed at a temperature lower than the formation temperature of the oxide film. A first sacrificial oxide film is formed by thermal oxidation, and the first sacrificial oxide film is removed to expose the silicon substrate. Then, a second sacrificial oxide film is formed by thermal oxidation at a high temperature equal to or higher than the formation temperature of the oxide film in a region where the thin oxide film serving as the insulating film is formed, and the second sacrificial oxide film is further removed. .

Therefore, by forming the first sacrificial oxide film,
The residual stress layer and residual foreign matter on the surface of the silicon substrate can be taken in and removed by removing the first sacrificial oxide film.
Further, by forming the second sacrificial oxide film at a high temperature equal to or higher than the formation temperature of the thin oxide film as the insulating film, the contaminants existing deep in the silicon surface can be absorbed into the second sacrificial oxide film. it can. As a result, the concentration of a contaminant in the silicon substrate that causes a decrease in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film when the oxide film is subsequently formed can be reduced.

[0015] In the invention of claim 4, prior to forming the oxide film of the thin film as an insulating film on a silicon substrate, at a temperature lower than the formation temperature of the oxide film in the formation region of the oxide film A first sacrificial oxide film is formed by thermal oxidation of the first sacrificial oxide film, and the second sacrificial oxide film is grown by the thermal oxidation at a high temperature equal to or higher than the formation temperature of the thin oxide film as an insulating film.
Is formed, and then the second sacrificial oxide film is removed.

Therefore, by forming the first sacrificial oxide film,
The residual stress layer and residual foreign matter on the surface of the silicon substrate can be taken in and removed by removing the second sacrificial oxide film.
Further, by forming the sacrificial oxide film at a high temperature equal to or higher than the formation temperature of the thin oxide film as the insulating film, contaminants existing deep in the silicon surface can be absorbed into the sacrificial oxide film. As a result, the concentration of a contaminant in the silicon substrate that causes a decrease in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film when the oxide film is subsequently formed can be reduced.

[0017] As in the embodiment described in claim 5, when to perform sacrificial oxidation at a temperature lower than the impurity diffusion temperature in the well region is formed before the formation of the sacrificial oxide film, well region sacrificial oxide Can be prevented from spreading.

According to a sixth aspect of the present invention, when the sacrificial oxidation is performed at a temperature near the impurity diffusion temperature in the channel stopper layer formed before the formation of the sacrificial oxide film,
Excessive expansion of the channel stopper layer due to sacrificial oxidation can be suppressed.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Reference Example) will be described below with reference to the drawings reference examples embodying the present invention.

In this embodiment , a CMOS transistor is embodied. FIG. 1 is a cross-sectional view of an N-channel MOS transistor in a CMOS transistor in the gate length direction.

In FIG. 1, a well region 1a having a predetermined depth is formed in a surface layer on the upper surface of a silicon substrate 1, and a source region 2 and a drain region 3 are formed in the well region 1a with a space therebetween. . Source region 2 and drain region 3
A gate oxide film 4 on the silicon substrate 1 between
, The gate electrode 5 is arranged. Here, the gate oxide film 4 has a thickness of about 80 to 200 °,
It is formed by thermal oxidation at 50 ° C. This gate oxide film 4 corresponds to a thin oxide film as an insulating film.

An active impurity diffusion region 6 is formed between the source region 2 and the drain region 3, that is, in the well region 1a below the gate electrode 5. This active impurity diffusion region 6 becomes a channel region.

A silicon oxide film 7 is formed on the surfaces of source region 2 and drain region 3. A field oxide film (LOCOS oxide film) 8 is formed on the silicon substrate 1 around the element formation region, and a channel stopper layer 9 is formed in the well region 1a thereunder. With this channel stopper layer 9, a sufficient withstand voltage with respect to an adjacent element can be ensured.

On the other hand, a gate protection film 10 is formed around the gate electrode 5. An interlayer insulating film 11 is formed on gate protection film 10, silicon oxide film 7 and field oxide film 8, and contact holes 12 and 13 are formed in interlayer insulating film 11 and silicon oxide film 7.
A source electrode 14 and a drain electrode 15 are arranged in the contact holes 12 and 13. A protective film 16 is formed on the electrodes 14 and 15.

Next, a method of manufacturing a CMOS transistor will be described with reference to FIGS. First, as shown in FIG. 2, a silicon substrate 1 doped with a P-type or N-type impurity is prepared. Then, on this silicon substrate 1, P
A type impurity (N-type in the case of a P-channel) is ion-implanted, and heat treatment is performed at 1100 to 1200 ° C. to form a well region 1a. Subsequently, a pad oxide film 20 is formed on the upper surface of the silicon substrate 1 and a silicon nitride film 21 is formed thereon as a non-oxidation mask for selective oxidation, and is patterned by a photoetching process.
As a result, the silicon nitride film 2
1 is arranged. At this time, a P-type impurity is ion-implanted into an element isolation region (a portion where a field oxide film is to be formed) of the N-channel transistor, that is, an ion implantation region 22 for forming a channel stopper layer.

Thereafter, as shown in FIG. 3, a field oxide film 8 is formed on the well region 1a in the element isolation region by a selective oxidation method. At the same time, a channel stopper layer 9 is formed. The atmosphere temperature at this time is 950 to 1050
It is about ° C.

Then, the silicon nitride film 21 and the pad oxide film 20 thereunder are removed. As a result, the result is as shown in FIG. Subsequently, as shown in FIG.
In the transistor formation region on the upper surface of
400Å to several thousand thickness by thermal oxidation at 100 ° C
A sacrificial oxide film 23 is formed. That is, a high temperature of 1050 ° C. or more (1050 to
The sacrificial oxide film 23 is formed by thermal oxidation at 1100 ° C.).

Subsequently, as shown in FIG. 6, the sacrificial oxide film 23 is completely removed by wet etching. Thereafter, as shown in FIG. 7, a gate oxide film 4 of about 80 to 200 ° is formed in the transistor formation region on the upper surface of the silicon substrate 1 by thermal oxidation at 1050 ° C. Further, an impurity for adjusting the threshold voltage of the transistor is implanted into the silicon substrate 1 by ion implantation (forming an active impurity diffusion region 6).

Then, as shown in FIG. 8, polycrystalline silicon is deposited and a gate electrode 5 is formed by patterning. Subsequently, as shown in FIG. 9, the gate protective film 10 and the silicon oxide film 7 are
An N-type impurity (P-type impurity in the case of a P-channel transistor) is ion-implanted into the source ion-implanted region 24 and the drain ion-implanted region 25 by using the self-alignment action of the gate electrode 5.

Thereafter, as shown in FIG. 10, a source region 2 and a drain region 3 are formed by heat treatment. Further, after an interlayer insulating film (BPSG film) 11 is deposited,
Wiring contact holes 12 and 13 are formed by photoetching, and source and drain electrodes 14 and 15 are connected as shown in FIG. After that, an element protection film 16 is deposited and patterned for external electrodes to complete a CMOS transistor.

Next, various experiments regarding the characteristic evaluation of the gate oxide film 4 were performed, and the results will be described. The characteristics of the gate oxide film 4 were evaluated using a parallel plate type capacitor shown in FIG. 11 manufactured through the above-described steps. In this case, the gate electrode 5 including the end of the field oxide film 8 is used as a first counter electrode with the gate oxide film 4 interposed therebetween, and the silicon substrate (element region) 1 is used as a second counter electrode.
The thickness of the gate oxide film 4 is set to 150 °.

The breakdown voltage is measured by applying a negative bias (positive bias in the case of a P-channel transistor) to the gate electrode 5 in an element having the structure shown in FIG. With a withstand voltage of 8 MV
/ Cm or more was judged as good.

FIG. 12 shows the measurement results of the breakdown voltage. FIG.
In FIG. 2, the abscissa indicates the sacrificial oxidation temperature, and the ordinate indicates the withstand voltage non-defective rate. FIG. 12 shows a case where the gate oxidation temperature is 1050 ° C. on the characteristic line L1.
2 shows a case where the gate oxidation temperature is 850 ° C.

In the evaluation of the life, in the device waiting for the structure shown in FIG. 11, a negative bias (positive bias for a P-channel transistor) is applied to the gate electrode 5 and a constant current density of 10 to 100 mA / cm is applied to the gate oxide film 4. ^A constant current is passed so as to be ² , and the amount of charge that has passed through the gate oxide film 4 until the gate oxide film 4 is destroyed is evaluated. The amount of charge when the cumulative failure rate when the Weibull plot is 50% becomes 50% (5
0% Qbd) was estimated as the life.

FIG. 13 shows the life evaluation results. FIG.
In FIG. 3, the horizontal axis represents the sacrificial oxidation temperature, and the vertical axis represents the oxide film life (50% Qbd). In FIG. 13, the characteristic line L3 shows the case where the gate oxidation temperature is 1050 ° C., and the characteristic line L4 shows the case where the gate oxidation temperature is 850 ° C.

FIGS. 12 and 13 show that when the gate oxidation temperature indicated by the characteristic lines L2 and L4 is 850 ° C., all of the sacrificial oxidation at 875 ° C. or more is saturated with respect to the withstand voltage non-defective rate and the life. Have been obtained. On the other hand, in the case where the gate oxidation temperature indicated by the characteristic lines L1 and L3 is 1050 ° C., if the sacrificial oxidation temperature is lower than about 1050 ° C., the yield rate is low and the life is short, but the sacrificial oxidation temperature is 1050 ° C.
It can be seen that if the temperature is higher than around ℃, the yield rate of non-defective products and the life can be improved.

This is presumed to be due to the following contamination mechanism into the gate oxide film 4. As shown in FIG. 15, when forming the field oxide film 8, crystal defects 30, contaminants 31, residual stress layers, and residual foreign substances (such as white ribbons) 32 remain in the silicon substrate 1. From this state, as shown in FIG. 16, the silicon nitride film and the pad oxide film 20 are removed, and further, as shown in FIG. Pollutants 31 in
The residual stress layer and the residual foreign matter 32 enter the sacrificial oxide film 23. Then, as shown in FIG. 18, the sacrificial oxide film 23 is removed, and as shown in FIG. 19, the gate oxide film 4 is formed. This gate oxide film 4 has a contaminant 31
And the residual stress layer and the residual foreign matter 32 do not enter.

In this manner, when the sacrificial oxidation at a temperature equal to or higher than the gate oxidation temperature is performed after the LOCOS oxidation and before the gate oxidation, the contaminants 31 such as Fe present in silicon can be sufficiently contained in the sacrificial oxide film 23. Thus, the film quality of the gate oxide film 4 formed thereafter can be improved.

FIG. 14 is a graph showing the dependence of the yield rate of the gate oxide film on the sacrificial oxide film thickness. The horizontal axis represents the sacrificial oxide film thickness, and the vertical axis represents the breakdown voltage failure rate. This FIG.
From this it can be seen that the yield rate is low when the sacrificial oxide film thickness is less than 400 °, but the yield rate is extremely high when the thickness is greater than 400 °. Therefore, the sacrificial oxide film 23
By setting the thickness of the film to 400 ° or more, the yield can be extremely improved.

As described above, this embodiment has the following features. (A) Prior to forming the gate oxide film 4, as shown in FIG. 5, the region where the gate oxide film 4 is formed on the silicon substrate 1 is sacrificed by thermal oxidation at a temperature higher than the temperature at which the gate oxide film 4 is formed. Since the oxide film 23 is formed and the film 23 is removed as shown in FIG. 6, contaminants such as Fe existing deep in the silicon surface when forming the sacrificial oxide film 23 are removed. 23. As a result, the concentration of a contaminant in the silicon substrate that causes a reduction in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film during the subsequent formation of the oxide film can be reduced.

Since the sacrificial oxide film 23 was formed and removed immediately before the gate oxide film 4 was formed, a better silicon surface was obtained when the gate oxide film 4 was formed. That is, the ion implantation for forming the channel stopper layer and the etching process for forming the LOCOS oxide may cause contamination of the silicon substrate 1.
Since the formation and removal of the sacrificial oxide film 23 are performed after the COS oxidation, a better silicon surface can be obtained as compared with the case where the formation and removal of the sacrificial oxide film 23 are performed before the LOCOS oxidation. (B) 1100 to 12 which is the diffusion temperature of the well region 1a
At a temperature of 1050 ° C. lower than 00 ° C., the sacrificial oxide film 23
Is formed, the well region 1a does not expand when the sacrificial oxide film 23 is formed, and a predetermined depth can be secured.

Further, the formation temperature of the LOCOS oxide film, that is, the diffusion temperature of the channel stopper layer 9 is 950 to 950.
At a temperature close to 1050 ° C., 1050 ° C., the sacrificial oxide film 23
Is formed, the channel stopper layer 9 can be disposed in a predetermined region (only around the transistor forming region) without forming the channel stopper layer 9 excessively when the sacrificial oxide film 23 is formed. (First Embodiment) Next, a first embodiment embodying the present invention, reference
The following description focuses on the differences from the example .

In this embodiment, FIGS.
(The mechanism is also used to explain the mechanism). First, as shown in FIG. 20, a field oxide film 8 is formed. At this time, crystal defects 30, contaminants 31, residual stress layers, and residual foreign substances 32 remain in the silicon substrate 1. From this state, as shown in FIG. 21, the silicon nitride film 21 and the pad oxide film 20 are removed, and then, as shown in FIG.
A sacrificial oxide film 40 of 0 to several thousand degrees is formed. That is, the sacrificial oxide film 40 is formed by thermal oxidation at a low temperature (875 ° C.) lower than 1050 ° C., which is the formation temperature of the gate oxide film 4.
To form

Then, as shown in FIG.
For 30 to several hundred minutes. That is, annealing is performed at a temperature equal to or higher than the temperature at which the gate oxide film 4 is formed. The atmosphere at this time is a non-oxidizing atmosphere, and specifically refers to an inert gas atmosphere such as a nitrogen gas or an argon gas. By this annealing, the contaminants 31 are sucked up by the sacrificial oxide film 40 and melted in the sacrificial oxide film 40. And FIG.
As shown in FIG. 7, the sacrificial oxide film 40 is removed to expose the silicon substrate 1.

Here, when annealing is performed in a non-oxidizing atmosphere, as shown in FIG. 23, a contaminant 39 (a substance that precipitates at the oxide film interface) that does not dissolve in the oxide film deposits near the oxide film-silicon interface. Then, as shown in FIG. 24, the contaminants 39 remain.

For this reason, as shown in FIG. 25, a second sacrificial oxide film 41 having a thickness of about several hundred degrees is formed by thermal oxidation at a temperature lower than the temperature at which the gate oxide film 4 is formed (for example, 875 ° C.). Form and take up contaminants 39. Thereafter, as shown in FIG. 26, after removing the sacrificial oxide film 41 to expose the silicon substrate 1, a gate oxide film 4 is formed as shown in FIG.

Next, the experimental results will be described. In FIG. 28,
The sacrificial oxide film 40 in FIGS.
Å Form and anneal at 1050 ° C in nitrogen atmosphere for 240
min (min), and a sacrificial oxide film 4 is formed by wet etching.
0 is completely removed, the second sacrificial oxide film 4 is formed at 850 ° C.
1 shows the results of life evaluation of a sample in which the gate oxide film 42 was formed at 150 ° in an O ₂ atmosphere at 1050 ° C. by forming and removing 250 ° and a sample in which annealing was not performed in the middle.

From FIG. 28, it was confirmed that the lifetime was improved by performing the annealing at 1050 ° C. in the same manner as in the case of performing the sacrificial oxidation at 1050 ° C. in the reference example . As described above, this embodiment has the following features. (A) As shown in FIGS. 22 to 24, prior to forming the gate oxide film 4 on the silicon substrate 1, the formation region of the gate oxide film 4 is formed at a temperature lower than the formation temperature of the gate oxide film 4. The sacrificial oxide film 40 is formed by thermal oxidation, and the sacrificial oxide film 40 is removed after annealing at a high temperature equal to or higher than the formation temperature of the gate oxide film 4. The residual stress layer and foreign particles on the surface can be taken in and removed by removing the sacrificial oxide film 40, and the contaminants existing deep in the silicon surface can be sucked into the sacrificial oxide film 40 by annealing. As a result, the concentration of a contaminant in the silicon substrate that causes a reduction in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film during the subsequent formation of the oxide film can be reduced. (B) Further, after the sacrificial oxide film 40 is removed after annealing, as shown in FIG. 25, the second region is formed by thermal oxidation at a temperature lower than the formation temperature of the gate oxide film 4 in the formation region of the gate oxide film 4. Since the sacrificial oxide film 41 is formed and the sacrificial oxide film 41 is removed, the residual contaminants 39 on the surface of the silicon substrate 1 are taken in, and this can be eliminated by removing the second sacrificial oxide film 41. In other words, the contaminants which do not dissolve in the oxide film tend to precipitate at the SiO2 / Si interface by annealing, but the contaminants can be reliably removed.

As an application example of the present embodiment, the gate oxidation may be performed after removing the sacrificial oxide film 40 without forming the second sacrificial oxide film 41. That is, when the amount of generation of the contaminant 39 in FIG. 24 is small or there is no problem in element performance, the formation and removal of the second sacrificial oxide film 41 can be unnecessary. Second Embodiment Next, a second embodiment will be described, focusing on differences from the first embodiment.

In this embodiment, FIGS.
(A mechanism is also used).
First, as shown in FIG. 29, a field oxide film 8 is formed. At this time, the crystal defects 30 in the silicon substrate 1
, Contaminants 31, residual stress layers, and residual foreign substances 32 remain. From this state, as shown in FIG. 30, the silicon nitride film 21 and the pad oxide film 20 are removed.
As shown in FIG. 5, the surface residual stress layer and the sacrificial oxide film 50 for removing foreign matter are subjected to thermal oxidation at a low temperature of about 850 ° C. to 400 ° C.
To several thousand degrees. That is, the first sacrificial oxide film 50 is formed by thermal oxidation at a temperature lower than the formation temperature of the gate oxide film. At this time, in order to increase the oxidation rate, H
_It is preferable to use a ₂ O atmosphere, HCl, or the like.

Further, as shown in FIG. 32, the sacrificial oxide film 50 is completely removed by wet etching to expose the silicon substrate 1. Thereafter, as shown in FIG. 33, a second sacrificial oxide film 51 is formed again at a high temperature (for example, 1050 ° C.) higher than the gate oxidation temperature by several hundreds of degrees. At this time, the oxidizing atmosphere is preferably an O ₂ atmosphere, whereby the oxidizing rate can be reduced, and the time for the contaminants to diffuse to the surface can be increased.

After removing the second sacrificial oxide film 51 as shown in FIG. 34, a gate oxide film 4 is formed as shown in FIG. Next, experimental results will be described.

FIG. 36 shows the results of life evaluation (50% Qbd) for three prototypes (samples). That is, the first
Of the sacrificial oxide film 50 at 875 ° C. in an H ₂ O atmosphere at 850 ° C.
After it is formed and completely removed by wet etching, a second sacrificial oxide film 51 is formed at 875 ° C. and 100 ° C.
0 ° C., to form a 300Å thermal oxidation at a temperature of 1050 ° C., to remove this, 150 Å in O ₂ atmosphere at 1050 ° C.
The gate oxide film formed above is used as a sample.

As can be seen from FIG. 36, it can be confirmed that the life of the sample subjected to the sacrificial oxidation at 1050 ° C. is remarkably improved. As described above, this embodiment has the following features. (A) As shown in FIGS. 31 to 33, prior to forming the gate oxide film 4 on the silicon substrate 1, the region where the gate oxide film 4 is formed at a temperature lower than the temperature at which the gate oxide film 4 is formed. Since the first sacrificial oxide film 50 is formed and removed by thermal oxidation, and the second sacrificial oxide film 51 is formed and removed by thermal oxidation at a temperature higher than the formation temperature of the gate oxide film 4, the first sacrificial oxidation is performed. The silicon substrate 1 is formed by forming the film 50.
The first sacrificial oxide film 50 can be removed by taking in the residual stress layer and the residual foreign matter on the surface of the semiconductor device, and furthermore, by forming the second sacrificial oxide film 51, the contaminant existing deep in the silicon surface can be removed. Can be absorbed into the sacrificial oxide film. As a result, the concentration of a contaminant in the silicon substrate that causes a decrease in the breakdown voltage of the oxide film can be reduced, and the concentration of the contaminant eluted in the oxide film when the oxide film is subsequently formed can be reduced.

An application example of the present embodiment will be described below.
In the second embodiment described so far, as shown in FIG. 32, after removing the sacrificial oxide film 50 by wet etching, as shown in FIG.
Although the sacrificial oxide film 51 is formed at 50 ° C., the sacrificial oxide film 51 is formed at a high temperature (for example, 1050 ° C.) without removing the sacrificial oxide film 50 and leaving the sacrificial oxide film 50. Is also good. That is, the second sacrificial oxide film 51 may be formed by growing the first sacrificial oxide film 50.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view in the gate length direction of an N-channel MOS transistor in a CMOS transistor according to a reference example and an embodiment;

FIG. 2 is a cross-sectional view for explaining a manufacturing process of an N-channel MOS transistor in a reference example .

FIG. 3 is a cross-sectional view for explaining a manufacturing process.

FIG. 4 is a cross-sectional view for explaining the manufacturing process.

FIG. 5 is a cross-sectional view for explaining the manufacturing process.

FIG. 6 is a cross-sectional view for explaining the manufacturing process.

FIG. 7 is a cross-sectional view for explaining the manufacturing process.

FIG. 8 is a cross-sectional view for explaining the manufacturing process.

FIG. 9 is a cross-sectional view for explaining the manufacturing process.

FIG. 10 is a cross-sectional view for explaining the manufacturing process.

FIG. 11 is a sectional view of a pattern for evaluating a gate oxide film.

FIG. 12 is a graph showing the sacrificial oxidation temperature dependency of the yield rate of a gate oxide film withstand voltage.

FIG. 13 is a diagram showing the sacrificial oxidation temperature dependence of the gate oxide film life.

FIG. 14 is a graph showing the dependency of a gate oxide film withstand voltage ratio on a sacrificial oxide film thickness.

FIG. 15 is an explanatory view showing a mechanism of contamination contamination in a gate oxide film.

FIG. 16 is an explanatory diagram of the same mechanism.

FIG. 17 is an explanatory view of the mechanism.

FIG. 18 is an explanatory view of the mechanism.

FIG. 19 is an explanatory view of the same mechanism.

FIG. 20 shows an N-channel MO according to the first embodiment.
Sectional drawing for demonstrating the manufacturing process of S transistor.

FIG. 21 is a cross-sectional view for explaining the manufacturing process.

FIG. 22 is a cross-sectional view for explaining the manufacturing process.

FIG. 23 is a cross-sectional view for explaining the manufacturing process.

FIG. 24 is a cross-sectional view for explaining the manufacturing process.

FIG. 25 is a cross-sectional view for explaining the manufacturing process.

FIG. 26 is a cross-sectional view for explaining the manufacturing process.

FIG. 27 is a cross-sectional view for explaining the manufacturing process.

FIG. 28 is a view showing the influence of the presence or absence of annealing on the life of a gate oxide film.

FIG. 29 shows an N-channel MO according to the second embodiment.
Sectional drawing for demonstrating the manufacturing process of S transistor.

FIG. 30 is a cross-sectional view for explaining the manufacturing process.

FIG. 31 is a cross-sectional view for explaining the manufacturing process.

FIG. 32 is a cross-sectional view for explaining the manufacturing process.

FIG. 33 is a sectional view for explaining the manufacturing process;

FIG. 34 is a cross-sectional view for explaining the manufacturing process.

FIG. 35 is a cross-sectional view for explaining the manufacturing process.

FIG. 36 shows an evaluation result of a gate oxide film life.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 4 ... Gate oxide film (a thin oxide film as an insulating film), 5 ... Gate electrode, 23 ... Sacrificial oxide film,
40: sacrificial oxide film (first sacrificial oxide film), 41: sacrificial oxide film (first sacrificial oxide film), 50: sacrificial oxide film (first sacrificial oxide film), 51: sacrificial oxide film (second) Sacrificial oxide film)

Continuation of front page (56) References JP-A-8-236639 (JP, A) JP-A-61-193459 (JP, A) JP-A-56-103425 (JP, A) JP-A-57-199227 (JP) JP-A-1-244621 (JP, A) JP-A-8-107205 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/316 H01L 21/8234 H01L 27/088

Claims (6)

(57) [Claims] A thin film as an insulating film is provided on a silicon substrate.
Of semiconductor device in which electrodes are arranged via oxide film
A method, prior to forming the oxide film on the silicon substrate, a field oxide film on the silicon substrate Engineering
And degree, after a field oxide film forming step, an acid of the thin film
Temperature lower than the oxide film formation temperature in the oxide film formation region
Forming a sacrificial oxide film by thermal oxidation at a temperature higher than the formation temperature of the thin oxide film as the insulating film.
And a step of removing a sacrificial oxide film after annealing . 2. A thin film as an insulating film on a silicon substrate.
Of semiconductor device in which electrodes are arranged via oxide film
Prior to forming the oxide film on a silicon substrate.
Lower than the temperature at which the oxide film is formed in the region where the oxide film is formed
Forming a first sacrificial oxide film by thermal oxidation at a temperature
And contaminants left in the silicon substrate at the silicon interface.
In order to deposit in the vicinity, the acid of the thin film as the insulating film is used.
Annealing at a high temperature equal to or higher than the formation temperature of the oxide film, and removing the sacrificial oxide film after the annealing to remove the silicon substrate.
Exposing and capturing the contaminants deposited near the silicon interface.
In this case, the area where the thin oxide film as the insulating film is formed is
Thermal oxidation at a temperature lower than the temperature at which the oxide film is formed.
2) forming a sacrificial oxide film, and removing the second sacrificial oxide film.
A method for manufacturing a semiconductor device. 3. A thin film as an insulating film is formed on a silicon substrate.
Of semiconductor device in which electrodes are arranged via oxide film
Prior to forming the oxide film on a silicon substrate.
Lower than the temperature at which the oxide film is formed in the region where the oxide film is formed
Forming a first sacrificial oxide film by thermal oxidation at a temperature
If, dew said silicon substrate by removing the first sacrificial oxide film
And forming the oxide film in the region where the thin oxide film as the insulating film is formed.
The second sacrificial acid is formed by thermal oxidation at a temperature higher than the film formation temperature.
A method of manufacturing a semiconductor device , comprising: forming a passivation film; and removing the second sacrificial oxide film . 4. A thin film as an insulating film is formed on a silicon substrate.
Of semiconductor device in which electrodes are arranged via oxide film
Prior to forming the oxide film on a silicon substrate.
Lower than the temperature at which the oxide film is formed in the region where the oxide film is formed
Forming a first sacrificial oxide film by thermal oxidation at a temperature
And a high temperature equal to or higher than the formation temperature of the thin oxide film as the insulating film.
The first sacrificial oxide film is grown by thermal oxidation
2. A method for manufacturing a semiconductor device , comprising: forming a second sacrificial oxide film; and removing the second sacrificial oxide film . 5. The method according to claim 5, wherein said sacrificial oxide film is formed.
The impurity diffusion temperature in the well region formed before film formation
5. The method according to claim 1, wherein the heat treatment is performed at a lower temperature.
9. The method for manufacturing a semiconductor device according to claim 1 . 6. The method according to claim 6, wherein said sacrificial oxide film is formed.
Impurities in channel stopper layer formed before film formation
5. The method according to claim 1, wherein the heat treatment is performed at a temperature near the diffusion temperature.
A method for manufacturing a semiconductor device according to claim 1 .