JP3296139B2 - FSK detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FS in which binary data is expressed by a combination of signals having two different frequencies.
The present invention relates to an FSK detection circuit for detecting a K (frequency shift keying) signal.

[0002]

2. Description of the Related Art Conventionally, for FSK detection, a stable oscillator as a frequency reference or a cycle reference or a phase circuit such as a tuning circuit has been required. For example, when an FM detection circuit is used for FSK detection, a ratio detection circuit,
In the Foster Seely detection circuit, double tuning detection circuit, quadrature detection circuit, and peak detection circuit, a tuning coil and a phase circuit were required. When a PLL circuit or a beat detection circuit is used, a stable oscillator is required. When a pulse count detection circuit is used, the detection circuit itself does not require a tuning coil or a stable oscillator.
If the change width of the frequency in K modulation is small, the change width of the detection output becomes small. Therefore, the input signal is frequency-converted to increase the apparent change ratio, or an analog circuit that can handle a signal with a small amplitude. Was needed.

FIG. 8 shows a conventional example disclosed in JP-A-63-200652. FIG. 8 shows an example of a beat detection circuit. In FIG. 8, a signal applied from an input terminal S is frequency-converted by _first and _second mixer circuits MIX ₁ and MIX ₂ . The oscillation frequency f OSC of the oscillator _OSC is
The frequency is set to approximately the middle between the high frequency f _HIGH and the low frequency f _LOW of the FSK-modulated input signal. The output of the oscillator OSC is directly applied to the first mixer circuit MIX ₁ , and is also phase-shifted by 90 degrees by the phase shift circuit PH and applied to the second mixer MIX ₂ . Outputs of the _first and _second mixer circuits MIX ₁ and MIX ₂ are applied to _first and _second low-pass filters LP ₁ and LP ₂ , respectively. First and second low-pass filters LP ₁ and LP ₂
Are the _first and second waveform shaping circuits AMP ₁ , A
Zohaba at MP _2, are waveform shaping. The outputs of the _first and _second waveform shaping circuits AMP ₁ and AMP ₂ are output from the _second waveform shaping circuit AMP when the output of the first waveform shaping circuit AMP ₁ rises and falls at the judgment circuit D _OUT .
₂ and the second waveform shaping circuit AMP ₂
When the output rises and falls, the frequency f _HIGH on the side where the frequency of the input signal is higher than the positive or negative polarity of the output of the first waveform shaping circuit AMP ₁ or the frequency f on the lower side
Judgment was made whether it was _LOW or not and output. The example of the beat detection circuit shown in FIG. 8 is suitable for integration into an integrated circuit because an input signal is first frequency-converted into a low-frequency signal.

[0004]

On the other hand, in the conventional FSK detection circuit, the oscillation frequency f _OSC of the oscillator OSC must be approximately halfway between the high frequency f _HIGH and the low frequency f _LOW of the FSK-modulated input signal. Therefore, a stable oscillator using a solid-state vibrating element such as a crystal, an oscillation coil, or the like is required, and furthermore, the oscillation frequency needs to be adjusted.

In addition, an analog circuit such as a phase shifter, a mixer, and a low-pass filter is required, and there has been a problem that it is difficult to make a CMOS process suitable for a logic circuit in an integrated circuit. Therefore, an object of the present invention is to provide an FSK detection circuit that is low in cost and stable in operation by eliminating the need for external components and making no adjustment in the integration of an integrated circuit. Another object of the present invention is to provide an FSK detection circuit which can be easily formed by a CMOS process.

[0006]

According to the present invention, there is provided an FSK detection circuit for detecting an input signal in which binary data is expressed by a combination of two different frequencies. in the detection circuit, before
The number of cycles of the input signal where the higher frequency of the input signal is sent during successive modulation cycles, and the lower frequency of the input signal is sent between successive modulation cycles.
An input signal having the same number of cycles, an oscillator, a gate circuit for selectively supplying an output of the oscillator to a count input terminal of a counter circuit according to a gate signal, and the gate having a width corresponding to an integral number of cycles of the input signal; A gate signal detection circuit for outputting a signal; and a counter for the counter circuit.
A memory circuit that stores the input signal, and comparing the current count value of the counter circuit with the count value one modulation cycle before stored in the memory circuit to determine whether the frequency of the input signal is higher. Alternatively, it has a determining means for determining whether the signal is on the lower side.

[0007]

According to the FSK detection circuit of the present invention, the counter circuit counts the output of the oscillator taken in at intervals of an integral number of cycles of the input signal in accordance with the gate signal, and the counting result differs depending on the frequency of the input signal. Use that thing. Alternatively, the input signal is counted by the counter circuit for an integer number of cycles of the output of the oscillator, and the fact that the count result differs depending on the frequency of the input signal is used. Then, by comparing successively based on the newly obtained count result group among a large number of continuously obtained count results, it is determined which signal of the frequency has been input, so that the oscillator has a long-term stability. It is not necessary to adjust the oscillator, and the oscillator is not adjusted. Further, it is possible to eliminate the need for external components, thereby facilitating the integration of an integrated circuit.

[0008]

FIG. 1 shows an example of an FSK detection circuit according to the present invention. The FSK detection circuit includes an oscillator (OSC) 1, a gate signal detection circuit (G-DET) 2, and a gate circuit (G).
3, a counter circuit (C) 4, a memory 5, and a determination circuit 6. In FIG. 1, an input signal which is a signal to be detected applied from an input terminal S is applied to a gate signal detection circuit 2. The output of the oscillator 1 is input to the count input terminal of the counter circuit 4 via the gate circuit 3. The output of the gate signal detection circuit 2 is connected to the control terminal of the gate circuit 3.

The output of the counter circuit 4 is connected to a memory 5 and a first input terminal of a decision circuit 6, and the output of the memory 5 is connected to a second input terminal of the decision circuit. The detection signal applied from the input terminal S is FSK-modulated, and the modulation cycle is 16 cycles of the carrier signal. Therefore, the interval at which the digital data to be transmitted is logically inverted is 16 cycles of the carrier signal.

FIG. 2 is a diagram for explaining the operation of the FSK detection circuit shown in FIG. 2A shows an input signal waveform, FIG. 2B shows a gate signal detected by the gate signal detection circuit G-DET, FIG. 2C shows an output of the oscillator OSC,
(D) shows the output of the gate circuit. As shown in FIG. 2, the gate signal detection circuit 2 takes out gate signals having a time width of four cycles of the input signal at intervals of one or two cycles. This corresponds to the fact that the FSK modulation cycle of the input signal is 16 carrier signal cycles in the example shown in FIG. That is, the interval of the gate signal is set to twice the interval (t1) for one cycle, once to the interval (t2) for two cycles, and further to three times of the gate signal (t3) for four cycles. Therefore, it is set so as to operate repeatedly in 16 cycles of the input signal. This is one modulation cycle (period H1 in FIG. 2).

The counter circuit 4 counts the output of the oscillator 1 only during the period of the gate signal shown in FIG. The memory 5 stores the respective count value C of the three gate signal period over one modulation cycle _{'1, C' 2, C} '3. The determination circuit 6 compares the count values supplied from the counter circuit 4 in the next modulation cycle period for each corresponding gate signal period. That is, the count values C ′ ₁ ,
C ′ ₂ and C ′ ₃ are compared with the count values C ′ ₁ , C ′ ₂ and C ′ ₃ before one modulation cycle period. Input signal is FSK
Since the count value differs by 4 or more between the frequency f _{HIGH of the} modulated carrier frequency and the frequency f _LOW of the low carrier frequency, the input signal is subjected to FSK modulation by comparing the difference between the count values. It is possible to determine whether the frequency f _HIGH on the higher carrier frequency or the frequency f _LOW on the lower carrier frequency.

Hereinafter, this frequency will be described in detail. In the example shown in FIG. 1, assuming that the input signal has been subjected to FSK modulation and its carrier frequency has been switched to f _HIGH and f _LOW and modulated, the oscillation frequency f _OSC of the oscillator OSC satisfies the following equation. It is set as follows. N × (f _OSC / f _LOW −f _OSC / f _HIGH ) ≧ 6 (1) where N is the number of cycles of the input signal corresponding to the width of the gate signal, and in this example, 4 f _OSC is the oscillator OSC. The oscillation frequency f _HIGH is the higher frequency of the carrier frequency where the input signal has been subjected to the FSK modulation. F _LOW is the frequency of the lower carrier frequency where the input signal has been subjected to the FSK modulation. In the example shown in FIG. Since the input signal is asynchronous, a count error occurs within ± 1 of each count result. Therefore, even if the input frequency is constant, there may be a maximum difference of 2 in the count result. Therefore, when the frequency of the input signal changes, it is necessary to set the count result so that at least a difference of 3 or more is obtained. That is, it is necessary to satisfy the condition that a significant difference can be obtained even when the occurrence of an error is worst for the determination, and that the value on the right side in the equation (1) is 5 or more. Further, the value on the right side in the equation (1) is set to 6 so that a difference of 4 or more is obtained in the count result at least with a margin for the drift of the oscillator OSC.

Here, the example shown in FIG. 1 will be further described with numerical examples. f _HIGH = 120 kHz f _LOW = 100 kHz N = 4 By setting f _OSC = 900 kHz, the condition of equation (1) can be satisfied. In this case f
The count value of the counter circuit 4 when _HIGH is input is 30 ± 1, and the count value of the counter circuit 4 when f _LOW is input is 36 ± 1 because there is a difference of 4 or more (3 or more). ) Judgment is possible. Furthermore, there is a margin of one count (1/36 = 2.8% in terms of oscillation frequency) as a count value even for a short-term drift of the oscillation frequency f _OSC of the oscillator OSC.

[0014] Specifically, (in this example 133～160Myusec) modulation period of the FSK-modulated input signal is a tolerance drift among the twice the time of a short term oscillating frequency f _OSC 1 / It is very easy to suppress the drift to 36 = 2.8% or less. Even if the oscillation frequency f _OSC is greatly increased and increases to 10 times, the ratio is
The demands for short-term drift are becoming more stringent, but still achievable. There is no problem with the long-term drift because the comparison is sequentially determined based on the new count results. Therefore, the oscillator OSC has almost no restriction on the stability of the oscillation frequency f _OSC with respect to the FSK detection operation. Therefore, an oscillation circuit that can be easily formed in an integrated circuit and does not particularly require external components, for example, a ring oscillator or a multivibrator can be used.

As described above, the FSK according to the present invention is
The detection circuit sequentially compares the count results counted by the counter circuit 4 during the four periods of the input signal, and if there is no significant difference (4 or more) from the count result at the same phase in the immediately preceding modulation cycle, the input is performed. It is detected that there is no change in the frequency, and if there is a change greater than or equal to the significant difference in the count result, it can be detected that there has been a change in the input frequency according to the change. Here, each count result is not compared with the immediately preceding count result, but is compared with the value one modulation cycle ago. The reason is that the count result for the input signal in the transient state immediately after the frequency switching in the modulation cycle converges. This is because the count values in later states are not compared.

The FSK detection operation can be performed simply by sequentially comparing each count value with the immediately preceding count value. In this case, the response of the determination when the input signal in the transient state is counted is delayed, but can be detected without fail because the determination is performed three times within the modulation period.

FIG. 3 shows another embodiment of the FSK detection circuit according to the present invention. When detecting the detected defect in the determination circuit 6 to the example shown in FIG. 1, controls the operation timing of the gate signal detecting circuit 2 feeds back the detected failure signal to the operation timing control terminal T ₁ of the gate signal detecting circuit 2 In addition, the interval between the gate signals having a time width of four periods can be forcibly expanded temporarily. For example, in FIG. 2, t ₂ has a width of two clocks, but by extending this to 3 to 4 clocks, the operation timing can be shifted. In the embodiment shown in FIG. 3, the FSK modulation cycle of the input signal is the same as that of the carrier signal for 16 cycles, but the operation is not clear because the transient portion of the FSK modulation is detected. The synchronization relationship is shifted. In the example of FIG. 1, the detection is performed three times during one modulation cycle to cope with this problem. In this way, if the operation point is positively shifted to select the optimum point, one modulation cycle is performed. Since the number of operations during the period can be reduced, there is an effect of reducing current consumption.

FIG. 4 shows still another embodiment of the FSK detection circuit according to the present invention. The oscillator OS shown in FIG.
The oscillation frequency f _{OSC of} C can be roughly adjusted. This is because the oscillation frequency f _OSC of the oscillator OSC should satisfy the equation (1) from the point of view of the FSK detection operation, but if it is too high, the current consumption is simply increased, which is disadvantageous. However, this is an example of automatic control. The count value of the counter circuit 4 is supplied to the memory 5 and the determination circuit 6 in the same manner as in the previous embodiment, but is also supplied to the other input terminal of the comparison circuit 7 in which the set value is input to one input. .
As the count result by feeding back the output of the comparator circuit 7 to the oscillation frequency control terminal T ₂ of the oscillator 1 is in the range of approximately settings are roughly controlling the oscillation frequency f _OSC of the oscillator OSC.

The method of roughly controlling the oscillation frequency f _OSC of the oscillator OSC can be achieved, for example, by controlling the operating current of a current-controlled ring oscillator. Also,
The output of the counter circuit 4 is observed by the comparison circuit 7 and the oscillator OSC
When making a correction to roughly adjust the oscillation frequency f _OSC of the oscillator, if the range of the set value is widened, the step of adjusting the oscillator OSC may be coarse, but the adjustment is also rough. Conversely, if the range of the set value is narrowed, the step of adjusting the oscillator OSC must be made finer accordingly. However, fine adjustment is possible. In the present invention, there is no particular effect even if the adjustment is made finely, so there is no problem even if the setting range is widened. Also, the design and manufacture of the oscillator 1 become easier.

FIG. 5 shows an example of a current control type ring oscillator. FIG. 5 shows an example of a current-controlled ring oscillator.
In FIG. 5, the oscillation frequency is controlled by a control voltage applied to the _first and _second current control terminals X ₁ and X ₂ . that's all,
As described, the example of FIG. 4 shows the oscillation frequency f of the oscillator OSC.
_In this example, the current consumption is suppressed by roughly controlling the _OSC .

FIG. 6 shows still another embodiment of the FSK detection circuit according to the present invention. The oscillator shown in FIG.
This is an example in which the oscillation operation of the SC is controlled by the gate signal from the gate signal detection circuit 2. The gate signal of the gate signal detection circuit 2 is input to a trigger terminal for controlling the start of oscillation of the oscillator 1, and the oscillator 1 outputs a clock only during the gate signal period. In this example, since the oscillation operation of the oscillator OSC can be forcibly synchronized with the input signal, the deviation of the count value in the counter circuit 4 is changed from ± 1 to +0.
/ -1. As a result, the condition given by the equation (1) is relaxed, and the value on the right side is reduced from 6 to 4. In the case of this embodiment, the oscillator 1 outputs a clock only during the gate signal period, so that the gate circuit 3 can be omitted.

When the operation of the example shown in FIG. 1 is applied to the example described above, there is an effect that the oscillation frequency f _OSC of the oscillator OSC can be reduced from 900 kHz to 600 kHz. As described above, the oscillation frequency f _OSC of the oscillator OSC can be reduced, so that there is an effect of reducing current consumption.

FIG. 7 shows another example of the FSK detection circuit according to the present invention. The example shown in FIG. 7 is optimal for the detection of an FSK modulated signal in which one of the input signal frequencies f _HIGH or f _LOW does not continue beyond the set value, and the generation probability is almost equal when viewed over the set modulation cycle. This is an example. FIG.
1, an input signal is applied from an input terminal S to first and second gate signal detection circuits 11 and 13, and an output of the oscillator 1 is supplied to the first and second gate circuits 10 and 12 via a first and second gate circuits 10 and 12. 1 and are applied to the count input terminals of the second counter circuits 14 and 15. The first and second gate signal detection circuits 11,
13 are output from the first and second gate circuits 10, 1 respectively.
2 and the first and second counter circuits 1
The count outputs 4 and 15 are both applied to the determination circuit 16. Here, the first gate signal detection circuit 11 repeatedly detects the gate signal G1 having a time width of four cycles of the input signal at intervals of one or two cycles. This is because the operation is repeated in 16 cycles of the input signal, corresponding to the fact that the FSK modulation cycle of the input signal is 16 cycles of the carrier signal, as in the example shown in FIG. is there.

On the other hand, the second gate signal detection circuit 13 repeatedly detects a gate signal having a time width of 64 cycles of the input signal. Since the example shown in FIG. 7 corresponds to the case where the same frequency is modulated so that the same frequency does not continue three or more times in the FSK modulation, the modulation frequency is four times, that is, 64 cycles in the input signal. This is because the gate signal G2 is generated at a timing shifted by 16 × 4 = 64 with respect to the gate signal G1 since the signals of f _HIGH and f _LOW are always input once if the minute is taken out. The first and second counter circuits 14 and 15 receiving the gate signals G1 and G2 shifted by 64 cycles count the clock supplied from the oscillator 1 during each gate signal period, and determine the count value by the determination circuit 16. To supply. The determination circuit 16 compares the count values of the first and second counter circuits 14 and 15 and determines whether the signal input at that point in time is the higher frequency f _HIGH or the lower frequency f _{LOW of the} carrier frequency. Is determined.

To enable the above determination, the oscillator OSC
The oscillation frequency f _OSC is set so as to satisfy the expression (2). 16 (f _OSC / f _LOW −f _OSC / f _HIGH ) ≧ 33 (2) where f _OSC is the oscillation frequency of the oscillator OSC, and f _HIGH is the higher frequency of the carrier frequency at which the input signal has been subjected to the FSK modulation. f _LOW is the lower frequency of the carrier frequency at which the input signal has been subjected to the FSK modulation. Here, the example shown in FIG. 7 will be described using a numerical example. f _HIGH = 120 kHz f _LOW = 100 kHz When N = 4 By setting f _OSC = 1.5 MHz, the condition of equation (2) can be satisfied.

In this case, the count value of the first counter circuit 14 when f _HIGH is input becomes 50 ± 1 and f
The count value of the first counter circuit 14 when _LOW is input is 60 ± 1, and the second counter circuit 15 when f _HIGH is input three times and f _LOW is input once in the modulation cycle.
Is 840 ± 1 (3). The count value of the second counter circuit 15 when f _HIGH is input once and f _LOW is input three times in the modulation period is 920 ± 1. (4) Here, when the count result of the counter circuit 14 is read by shifting the digit by four digits, the count value of the first counter circuit 14 when f _HIGH is input in the modulation period is 800 ± 16 (5), and the modulation is performed. The count value of the first counter circuit 14 when f _LOW is input in a cycle is 960 ± 16 (6). Therefore, the count value (5) of the first counter circuit 14 and the count value (3) of the second counter circuit 15 have a difference of 23 or more in the count value, and the count value (6 ) And the count value (4) of the second counter circuit 15 can be determined because there is a difference of 23 or more in the count value.

The count value (5) of the first counter circuit 14 and the count value (4) of the second counter circuit 15
Since the count value (6) of the first counter circuit 14 and the count value (3) of the second counter circuit 15 are further open between the count values, the determination can be made more easily.

Further, the oscillation frequency f _OSC of the oscillator _OSC
(1/60 = 1.7 as the oscillation frequency)
%). Specifically, FSK of the input signal
This is an allowable value of the drift within twice the modulation period (560 to 613 μsec in this example), and it is extremely easy to suppress the oscillation frequency f _OSC to a drift of 1/60 = 1.7% or less in a short term. It is.

Even if the oscillation frequency f _OSC varies, the count value also varies by the ratio, so that no problem occurs as long as the condition (2) is satisfied. Long-term drift is not a problem because it is sequentially determined based on new count results. Therefore, there is almost no restriction on the stability of the transmission frequency f _OSC with respect to the oscillator OSC detection operation. For this reason, a transmission circuit which can be easily formed in an integrated circuit and does not particularly require external components, such as a ring oscillator or a multivibrator, can be used. According to the present embodiment, since it is possible to configure a circuit that can be easily configured by a CMOS process in the integrated circuit, it is easy to integrate the logic circuit and the memory circuit into one chip at the same time.

[0030]

Since the FSK detection circuit according to the present invention has the above-described configuration and operation, it can be formed by a circuit which can be easily formed by a CMOS process in the case of an integrated circuit. At the same time, it is easy to make one chip, and since there is no adjustment portion, the operation is stable and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of an FSK detection circuit according to the present invention.

FIG. 2 is a diagram illustrating the operation of the FSK detection circuit according to the present invention.

FIG. 3 is a diagram showing another embodiment of the FSK detection circuit according to the present invention.

FIG. 4 is a diagram showing still another embodiment of the FSK detection circuit according to the present invention.

FIG. 5 is a circuit diagram illustrating an example of an oscillator.

FIG. 6 is a diagram showing still another embodiment of the FSK detection circuit according to the present invention.

FIG. 7 is a diagram showing still another embodiment of the FSK detection circuit according to the present invention.

FIG. 8 is a diagram showing a conventional example.

[Explanation of symbols]

S input terminal OSC, 1 oscillator 2 gate circuit 3 gate signal detection circuit 4 counter circuit 5 memory D _OUT , 6 determination circuit MIX ₁ , MIX ₂ mixer circuit PH phase shift circuit LP ₁ , LP ₂ low-pass filter AMP ₁ , AMP ₂ waveform Shaping circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/14

Claims (10)

(57) [Claims] 1. An F-detector for detecting an input signal in which binary data is represented by a combination of signals having two different frequencies.
In the SK detection circuit, the number of cycles of the input signal where the higher frequency of the input signal is sent during successive modulation cycles, and the number of lower frequencies of the input signal that are sent between successive modulation cycles.
An input signal having the same number of cycles, and an oscillator; a gate circuit for selectively supplying an output of the oscillator to a count input terminal of a counter circuit in accordance with a gate signal; A gate signal detection circuit for outputting a gate signal, and a memory circuit for storing a count value of the counter circuit
By comparing the current count value of the counter circuit with the count value one modulation cycle before stored in the memory circuit, it is determined whether the frequency of the input signal is higher or lower. An FSK detection circuit, comprising: a determination unit. 2. The transmission frequency of the oscillator according to claim 1, wherein the oscillation frequency of the oscillator is at least twice as high as two frequencies of the input signal, and the gate signal detection circuit performs an integral number of cycles of the input signal. Output a gate signal having a width of
SK detection circuit. 3. The FSK detection circuit according to claim 1, wherein the oscillator is ON / OFF controlled in synchronization with an output of the gate signal detection circuit. 4. The method of claim 1, feed between the higher side or lower side frequency of the input signal you continuous modulation cycles
Gate signal detection from the number of input signal cycles
An FSK detection circuit comprising means for shifting the timing of an integer number of detection operations taken out by an output circuit. 5. An oscillator, first and second counter circuits connected to the oscillator via first and second gate circuits, respectively, and a width corresponding to N (N is an integer) cycles of an input signal. A first gate signal detection circuit for outputting the gate signal of the above to the first counter circuit; and a gate signal having a width of M times (M is an integer different from N) cycles of the input signal to the second counter circuit. Output second
An FSK detection circuit, comprising: a gate signal detection circuit of (1), and comparison means for comparing outputs of the first and second counter circuits. 6. The FSK detection circuit according to claim 5, wherein a predetermined offset value is set in the first or second counter circuit, and counting is started from the offset value. 7. The FSK detection circuit according to claim 5, wherein the first and second gate signal detection circuits include means for changing a pulse width of the gate signal for a set time. 8. The FS according to claim 1, further comprising a function of adjusting the oscillation frequency of the oscillator according to the count result of the counter circuit.
K detection circuit. 9. The gate signal detection circuit according to claim 1, 2, 3, 4, 5, 6, or 7,
An FSK detection method, wherein the number of cycles of the input signal corresponding to the operation cycle of repeating OFF is equal to or equal to an integral number of the number of cycles of the carrier signal with respect to the modulation cycle of the input signal subjected to FSK modulation. circuit. 10. The carrier signal according to claim 5, wherein the number of cycles of the input signal with respect to the gate signal detected by the first gate signal detection circuit is one cycle of the modulation cycle of the input signal subjected to FSK modulation. The number of cycles of the input signal with respect to the gate signal detected by the second gate signal detection circuit is set to one integral number of the cycle number, and is equal to one of the modulation periods of the input signal that has been subjected to the FSK modulation.
An FSK detection circuit characterized by being set to an integral multiple of the number of cycles of a carrier signal with respect to a cycle.