JP3294998B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a BGA (Ball Grid Array).
The present invention relates to improvement of a package of a semiconductor device of the type. BG
A is a semiconductor device package in which pins and lead frames, which are input / output terminals of the semiconductor device, are formed by an array of solder balls (solder bumps) and ball-shaped conductors.

[0002]

2. Description of the Related Art In recent years, there has been a demand for miniaturization of electronic devices and high-density mounting of semiconductor devices on printed circuit boards.
As the functions and performance of the semiconductor devices increase, the number of pins of the semiconductor device package is also required. Conventionally, QFP (Quart Flat Package) has been used as a package that supports multiple pins.
However, there is a limit to the enlargement and fine pitch of the package and body. At present, it is considered that the BGA is effective as a package corresponding to the increase in the number of pins / fine pitch.

However, the conventional plastic body B
In the GA, since the number of pins is realized by using a relatively high-cost multilayer printed wiring layer, the average cost of the conventional QFP cannot be suppressed below. Also, realizing multi-pins using a low-cost single-layer printed wiring layer requires fine wiring, and there is a limit in the current printed wiring layer manufacturing technology. The BGA using tape carrier bonding TAB (Tape automated bonding) is a promising package in terms of multi-pin and low cost, since fine wiring can be realized and the cost of the intermediate substrate can be suppressed.

As a conventional semiconductor device having a BGA type package structure, Japanese Patent Laid-Open No. 6-112354, US Pat. No. 5,241,133, US Pat.
No. 462 is known.

FIG. 12 is an explanatory view showing the structure of a conventional BGA type 1 semiconductor device. The BGA type 1 semiconductor device shown in FIG. 12 is disclosed in US Pat. No. 5,241,133.
1 shows a semiconductor device of a leadless pad array chip carrier described in the above publication. In FIG. 12, a semiconductor chip 102a having a BGA type package structure having two wiring pattern layers and mainly having an electrode 114a is shown.
And the resin substrate 125 provided with the through hole 109a
a based on a wiring component 101a and a semiconductor chip 1
It is composed of a wire 104a connecting the electrode 114 of 02a and the wiring component 101a, and a resin sealing portion 105a.
An upper wiring pattern layer 124a is formed on the surface of the wiring component 101a on the semiconductor chip 102a side, and an internal connection region 115a is provided in the upper wiring pattern layer 124a.

The semiconductor chip 102a of the wiring component 101a
A lower wiring pattern layer 126a is formed on the entire surface on the side opposite to the above, and an external connection region 111a is provided in the lower wiring pattern layer 126a.
An external connection terminal 110a (solder bump) for mounting is formed on the (solder pad). One of the wires 104a is connected to the electrode 114a of the semiconductor chip 102a,
The other is the internal connection region 11 of the upper wiring pattern layer 124a.
5a. The through hole 109a is formed at the outermost periphery of the wiring component 101a, and the two wiring pattern layers of the upper wiring pattern layer 124a and the lower wiring pattern layer 126a are electrically connected through the through hole 109a. ing.

FIG. 13 is an explanatory view showing the structure of a conventional BGA type 2 semiconductor device. The BGA type 2 semiconductor device shown in FIG. 13 is a thin overmolded pad array described in Japanese Patent Application Laid-Open No. H06-112354.
3 shows a semiconductor device of a carrier. In FIG. 13, a wiring pattern layer 108b of a wiring component 101b is a single-layer BGA, and mainly includes a semiconductor chip 1 having an electrode 114b.
02b and the wiring component 1 in which the wiring pattern layer 108b is a single layer
01b, a wire 104b for connecting the electrode 114b of the semiconductor chip 102b and the wiring component 101b, and a resin sealing portion 105b.

The semiconductor chip 102b of the wiring component 101b
A wiring pattern layer 108b is formed on the side surface, and the internal connection region 115b is formed on the upper wiring pattern layer 108b.
And an external connection region 111b (solder pad) is provided in the wiring pattern layer 108b (conductive metal trace), and an external connection terminal 110b (solder ball) for mounting is formed in the external connection region 111b. Structure.

FIG. 14 is an explanatory view showing the structure of a conventional BGA type 3 semiconductor device. The BGA type 3 semiconductor device shown in FIG. 14 is disclosed in US Pat. No. 5,134,462.
1 shows a semiconductor device of a flexible film chip carrier. In FIG. 14, the wiring component 101
c is a single-layer BGA, and mainly includes a semiconductor chip 102c having an electrode 114c.
, A wiring component 101c, a metal ring 126c, and a resin sealing portion 105c. Semiconductor chip 102
The electrode 114c of c and the wiring component 101c are connected by inner lead bonding. Metal ring 126
“c” is joined to the outer periphery of the package for handling during mounting and for preventing warpage of the package.

[0010]

However, such a conventional BGA type semiconductor device has the following problems. The BGA type 1 semiconductor device shown in FIG. 12 has a wiring pattern layer 108a on both sides of the wiring component 101a.
Are formed, and the printed wiring layer is used as the wiring layer 101a.
a electrically the wiring pattern layers 124a, 126a on both sides
Connect. For this reason, the manufacturing cost itself of the wiring component 101a increases. In addition, the parts of the wiring component 101a which are not sealed with the resin also require strength as a package, so that a printed wiring layer having a certain thickness must be used, and the package becomes thick.

Furthermore, since only one surface of the wiring component 101a, which is the semiconductor chip mounting surface, is sealed with resin, the wiring component 101a, the semiconductor chip 102a, and the resin sealing portion 105a are sealed.
The warpage of the package occurs due to the difference in the coefficient of linear expansion from the resin. In order to reduce the influence of the resin sealing portion 105a,
When the area of the resin sealing portion 105a on the wiring component 101a is reduced, the difference between the portion with the sealing resin and the portion without the sealing resin is
As a result, the wiring layer is distorted, and the external connection terminals 110a
The flatness of the film becomes poor.

In the BGA type 2 semiconductor device shown in FIG. 13, a wiring pattern layer 108b is formed only on a semiconductor chip mounting surface of a flexible wiring component 101b, and an external connection terminal 110b is formed in a through hole 109b immediately below the wiring pattern layer 108b. Form. Flexible wiring component 101
Since no resist layer is formed on the wiring pattern layer 108b of b, the entire surface of the semiconductor chip mounting surface of the flexible wiring component 101b is sealed with resin. For this reason, the warpage of the package increases due to the difference in linear expansion coefficient between the flexible wiring component 101b and the sealing resin, and the external connection terminals 110b
The flatness of the film becomes poor.

In the BGA type 3 semiconductor device shown in FIG. 14, the wiring pattern layer 108c of the flexible wiring component 101c is a single-layer BGA. In order to prevent the package from warping, a metal reinforcing ring 126c is attached to the outer peripheral portion of the external connection terminal 110c of the package. However, the metallic reinforcing ring 126c is not connected to the external connection terminal 110.
The metal reinforcing ring 126c is set to have a small width so as not to increase the external dimensions of the package, although not joined to the top of the metal ring. For this reason, the flexible wiring component 101c has a small reinforcing area by the metallic reinforcing ring 126c, and the external connection terminal 110c is not reinforced by the metallic reinforcing ring 126c, so that the correction for the warpage of the package is sufficiently effective. It can not be said.

In the semiconductor devices of BGA types 1 to 3 shown in FIGS. 12 to 14, the external connection terminals are resin-sealed or insulated. It cannot be done directly. In the case of a BGA having such an overmolding structure, it is not possible to provide external connection terminals for vertically stacking a plurality of packages and wiring them in a leadless manner. In addition, a decrease in the reliability of the semiconductor device due to intrusion of moisture from a resin sealing portion or the like still remains.

The present invention has been made in consideration of the above circumstances. For example, in a BGA type semiconductor device, a thin conductive material is provided between a thinned first insulating material layer and a thinned second insulating material layer. The cost is reduced by using a flexible wiring layer having a three-layer structure in which the wiring pattern layer is sandwiched, and a rigid and flat frame component is joined immediately above the wiring pattern layer to which the external connection terminals are connected, and integrated to join the external connection terminals Maintaining the flatness of the area,
Furthermore, by resin-sealing the opening of the frame component, the frame component and the resin-sealed opening are integrated to suppress deformation of the package, thereby suppressing defects in the semiconductor device manufacturing process. Another object of the present invention is to provide a semiconductor device capable of reducing mounting defects at the time of mounting the semiconductor device and a method of manufacturing the same.

Further, the present invention provides a configuration in which a frame component is provided with conductive through holes to enable the same BGA type semiconductor device package and stacking to be realized.
Provided are a semiconductor device capable of high-density mounting and a method of manufacturing the same. Furthermore, the present invention reduces the difference in linear expansion coefficient between the package members, thereby reducing the warpage of the package due to the difference in linear expansion coefficient, and the adhesive for joining the frame component to the wiring layer is formed of an adhesive with the frame component. Provided are a semiconductor device that absorbs the stress of a wiring layer to absorb the warpage of a package, and a method of manufacturing the same.

[0017]

According to the present invention, there is provided a semiconductor chip having electrodes and the like, a flexible wiring layer comprising a conductive wiring pattern layer and first and second insulating layers sandwiching the conductive wiring pattern layer. A frame component having an opening having a size capable of accommodating the semiconductor chip and joined to the wiring layer to impart rigidity to the wiring layer, and electrically connecting the electrode of the semiconductor chip via the wiring pattern layer of the wiring layer. And a plurality of external connection terminals formed immediately below a wiring layer connected to the frame component, wherein the wiring pattern layer of the wiring layer comprises an external connection terminal.
Connection having an external connection pad electrically connected to the external connection
Further comprising a region, wherein the external connection region is bonded to a wiring layer.
The external connection pad is wound around the outer periphery of the
And the semiconductor chip is sealed with a sealing resin when the semiconductor chip is housed in the opening of the frame component and joined to the wiring layer.

That is, according to the present invention, the external connection terminals of the BGA type semiconductor device maintain the flatness as follows. The wiring pattern for thinning and cost reduction is a single layer, and the single layer wiring pattern has a sandwich structure in which c is sandwiched between a first insulating material layer and a second insulating material layer. By providing a flexible wiring layer and mounting a rigid and flat frame component at least immediately above the wiring pattern layer to which the external connection terminals are connected, the flatness of the mounting region of the external connection terminals is maintained. Also, the wiring layer
Electrically connected to external connection terminals on the wiring pattern layer
Further forming an external connection region having an external connection pad,
The external connection area is on the top of the frame component so as to wrap the frame component
Because it is configured to be joined so that it is located,
Therefore, the electrical characteristics test of the semiconductor device after mounting on another substrate
Test can be performed. Also, connect the external connection pads
It can also be used as a connection portion for lamination of a semiconductor device.

In the present invention, the semiconductor chip is
For example, LSIs such as MPU, ROM, RAM, ASIC, etc. composed of MOS transistors or TTL transistors
It is. The wiring layer includes a conductive wiring pattern layer and first and second insulating material layers sandwiching the conductive wiring pattern layer, and is configured to be flexible as a whole. The wiring pattern layer is about 1
It has a thickness of 0 to 50 μm and is made of a metal material, for example, gold, silver, copper or the like, but is generally made of copper in terms of cost and heat resistance. Further, the wiring pattern layer forms a region to be bonded to an electrode of the semiconductor chip with a wire and a region to be connected to an external connection terminal (BGA).

In order to form a flexible wiring layer, a flexible thermoplastic resin having a thickness of about 5 to 100 μm is preferably used as the first insulating material layer. Any thermoplastic resin may be used as long as it has heat resistance and insulation properties. For example, an epoxy resin and a polyimide resin are mentioned, and it is preferable to use a polyimide resin from the viewpoint of heat resistance. By utilizing the adhesiveness of the thermoplastic resin, the semiconductor chip and the wiring layer can be joined by heating the thermoplastic resin.

On the other hand, as the second insulating material layer, the same material and the same thickness as the first insulating material layer may be used, but a thick resin sheet or film is used. As the second insulating material layer, for example, any material may be used as long as it is excellent in heat resistance, insulation, strength, and dimensional stability. For example, polyimide resin, polyamide resin, BT
(Bismaleide / triazine) resin, epoxy resin, polyester resin, glass epoxy resin, glass polyimide resin and the like can be mentioned, but from the viewpoint of flexibility, cost and workability, it is preferable to use polyimide resin.

As the frame component, an opening having a size capable of accommodating a semiconductor chip can be formed, and can be formed so as to be joined to the wiring layer to impart rigidity to the wiring layer. The external size is determined by the semiconductor size and the number of external connection terminals. Further, the thickness of the frame component is also determined by the thickness of the semiconductor chip. As a material for frame parts, dimensional stability,
What is necessary is just to be excellent in rigidity, strength, heat resistance and workability. When a conductive material is used, for example, a metal material such as 42 alloy (Ni42%, Fe58%) and copper is used. When the material of the wiring layer (first and second insulating material layers) is polyimide resin Copper having a linear expansion coefficient is preferable.

On the other hand, an insulating material can be used as the frame component. For example, BT (bismaleide triazine) resin, epoxy resin, glass epoxy resin, ceramic mixed epoxy resin and the like can be mentioned. When the frame component is formed of such an insulating material, by providing a through hole vertically penetrating the frame component, the connection between the wiring pattern layer of the wiring layer and the external connection pad through this through hole allows other components to be formed. After the semiconductor device is mounted on the circuit board, an electrical characteristic test can be performed. Further, by filling the through hole with a metal material, it is possible to prevent a decrease in the reliability of the semiconductor device due to an increase in the heat of the opening, and to use the external connection pad at this time as a connection portion for lamination of the semiconductor device. .

Further, the frame component has a groove having a predetermined width / depth (for example, 0.5 to 2 mm / 0.2 mm) around the upper surface near the opening.
(1 to 1 mm), and it is preferable that the synthetic resin enter the groove to improve the adhesion between the frame component and the sealing resin and to prevent peeling. Further, the frame component has a predetermined width / length (for example, 0.5 to
A plurality of slits (0.2 mm / 5 to 10 mm) are provided symmetrically, and these slits are used for absorbing stress caused by curing shrinkage of the sealing resin, flatness of the wiring layer, and use as injection grooves for resin sealing. Is preferred.

As the resin for sealing the opening of the frame component,
Any resin may be used as long as it has storage stability, moldability, moisture resistance, heat resistance, and the like.For example, a mixture based on an epoxy resin, a silicone resin, a phenol resin, or the like is generally used. However, it is preferable to use an epoxy resin from the viewpoint of reliability.

The materials of the frame component, the resin for sealing the opening, and the wiring layer are selected so that their linear expansion coefficients are close to each other, and further, an adhesive material between the wiring layer and the frame component is selected. It is preferable to suppress the deformation of the semiconductor device by using a material capable of absorbing stress. For example, when the wiring pattern layer of the wiring layer is made of copper and the first and second insulating material layers are made of polyimide resin, it is preferable that the frame component is made of copper and the sealing resin is made of epoxy resin. By making the thickness of the frame component approximately equal to that of the resin sealing, the deformation of the semiconductor device is suppressed by integrating the frame component on the wiring layer and the sealing resin.

The external connection terminal connected to the wiring pattern layer of the wiring layer is preferably formed as a solder bump. As this solder bump, a ball-shaped one made entirely of solder or a copper ball having a surface plated with solder can be used, but from the viewpoint of cost, a solder ball-shaped whole should be used. Is preferred. The diameter of the external connection terminal depends on the number of pins of the solder bump and the package size, but is preferably 300 to 1000 μm. The external connection terminal is joined directly below the wiring layer to which the frame component is joined, and is electrically connected to the electrode of the semiconductor chip via the wiring pattern layer, so that the flatness of the region of the external connection terminal is maintained. .

As the wire connecting the electrode of the semiconductor chip and the wiring pattern layer, various materials can be used as long as they have good electrical conductivity. For example, gold, silver, copper, and the like can be used. Aluminum or the like can be used, but gold or silver is preferably used from the viewpoint of electrical conductivity. The semiconductor chip and the frame component may be attached to the wiring layer using a silver paste, a silver-free paste, or a sheet-like die bonding material.

[0029]

A frame component provided with a groove or a slit in advance from the opening to the outside and a sealing component for sealing the opening for accommodating the semiconductor chip after the semiconductor chip is mounted on the wiring layer are provided on the frame component. The resin sealing through the groove or the slit makes it possible to improve the reliability by reducing the absorption of moisture from the opening and to improve the heat dissipation.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings. Note that the present invention is not limited by this.

FIG. 1 is an explanatory diagram showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. The semiconductor device according to the first embodiment shown in FIG. 1 includes a wiring layer (wiring component) 1, a semiconductor chip 2 bonded to the wiring layer 1, a frame component 3 bonded to the wiring layer 1,
It comprises a wire 4 for connecting the semiconductor chip 2 and the wiring layer 1 and a resin sealing portion 5 for sealing the semiconductor chip 2 and the wire 4 with resin.

The wiring layer 1 includes a film or sheet-like first insulating material layer 6, a second insulating material layer 7, and a metal (copper) wiring pattern formed between these two insulating material layers. It is formed from layer 8. The wiring layer 1 has a through hole 9a
Is formed by forming a metal wiring pattern 8 on the upper surface of a second insulating material layer 7 provided with a first insulating material layer 6 on the wiring pattern layer 8. It has a sandwich structure in which the pattern layer 8 is sandwiched between the first insulating material layer 6 and the second insulating material layer 7.

An external connection terminal 10 of the BGA type is formed on the lower surface of the second insulating material layer 7, and the wiring pattern layer 8 is formed in the wiring pattern layer 8 through a through hole 9a.
Connection area 1 for connecting the external connection terminal 10 to the
1 is provided. The external connection terminal 10 is formed by bonding a solder bump to the external connection region 11.

The frame component 3 is attached to at least a region immediately above the external connection region 11 on the first insulating material layer 6 side of the wiring layer 1. The frame part 3 has a first surface 12 and a second surface 13,
The second surface 13 of the frame component 3 is joined to the first insulating material layer 6 of the wiring layer 1. The semiconductor chip 2 has an electrode 14 on the front surface.

The back surface of the semiconductor chip 2 is joined to the first insulating material layer 6 of the wiring layer 1. An internal connection region 15 is provided around the semiconductor chip 2 in the first insulating material layer 6.
Are formed. The internal connection region 15 on the wiring pattern layer 8 and the electrode 14 of the semiconductor chip 2 are connected by the wire 4. Since the electrode 4 of the semiconductor chip 2 and the internal connection region 15 of the frame component 3 are joined by the wire 4, the semiconductor chip 2 in which the position of the electrode 14 is different to some extent can be handled.

The resin sealing portion 5 is formed by forming the semiconductor chip 2 and the wire 4 in the cavity of the package on the wiring layer 1. The sealing resin is a thermosetting resin such as an epoxy resin. After injecting the sealing resin, the resin sealing portion 5 is heated to cure the resin. According to the above configuration, the rigid and flat frame component 3 is joined and integrated just above the flexible wiring layer 1 to maintain the flatness of the joint region of the external connection terminal 10, and the opening of the frame component 3 is further improved. By resin sealing, the deformation of the package can be suppressed by integrating the frame component 3 and the resin sealing portion 5.

FIG. 2 is an explanatory diagram showing a configuration of a semiconductor device according to Embodiment 2 of the present invention. 2, the same components as those in FIG. 1 are denoted by the same reference numerals. The semiconductor device of the second embodiment has a structure in which a part of the wiring pattern layer 8 of the wiring layer 1 is exposed from the first insulating material layer 6 to form a die pad 27.
The semiconductor chip 2 is bonded onto the die pad 22.

FIG. 3 is an explanatory view showing a method for manufacturing a semiconductor device according to the present invention. A method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. Electrode 14 of semiconductor chip 2
An internal connection region 15 connected to the wiring pattern layer 8 is formed on the wiring pattern layer 8 (see FIG. 3A). The frame 17 including the frame component 3 (see FIG. 3B) is joined to a predetermined position of the wiring layer 1 (see FIG. 3C). Frame 17
Are formed continuously as a pair of regions composed of a plurality of frame components 3 and connecting portions 17a which connect them separably.

The wiring layer 1 and the frame 17 are joined via an adhesive made of a thermosetting resin. In the joining method, the wiring layer 1 and the frame 17 are bonded via a thermosetting resin, and the thermosetting resin is cured by heating to complete the joining. In this example, the plurality of frame parts 3 are in an integrated frame state, but may be individual frame parts 3.

Next, the semiconductor chip 2 is bonded to a predetermined position of the wiring layer 1 (see FIG. 3D). The wiring layer 1 and the semiconductor chip 2 are joined via an adhesive made of a thermosetting resin. Next, the electrodes 14 of the semiconductor chip 2 and the internal connection regions 15 of the wiring layer 1 are connected by wires 4 made of a metal such as gold, silver, or copper (see FIG. 3E).

Next, resin sealing is performed to form a resin sealing portion 5 (see FIG. 3F). This resin sealing portion 5
After the potting resin is injected into the cavity of the package, the resin is cured by heating. In this example, a resin sealing method using no mold (dedicated injection machine) is used, but a resin sealing method using a mold may be used. The sealing resin used is a thermosetting resin such as an epoxy resin.

Next, the external connection terminals 10 are formed by bonding the solder bumps (see FIG. 3G). The place where the external connection terminal 10 of the wiring layer 1 is formed is where the through hole 9 of the second insulating material layer 7 is opened, and the external connection region 11 is exposed from the through hole 9a. After applying flux to the external connection area 11, solder balls are attached thereto, and the solder balls are joined by heating.
0 is formed.

As another method of forming the external connection terminal 10,
The external connection terminal 10 may be formed by placing a paste-like or sheet-like solder on the external connection area 11, heating and melting the solder to form a bump.

Next, an unnecessary portion of the frame 17 including the wiring layer 1 and the frame component 3 is cut (see FIG. 3H). What is shown in FIG. 3H is a single product. The cutting is performed along the outer periphery of a member corresponding to the frame component 3 in the frame 17.

In the manufacturing process after resin sealing, the connection portion 17a (outer frame portion) excluding the wiring layer 1 and the frame component 3 of the frame 17 is formed.
May be cut (see (i) of FIG. 3), and then the external connection terminals 10 may be formed (see (j) of FIG. 3).

FIG. 4 is an explanatory diagram showing a configuration of a semiconductor device according to Embodiment 3 of the present invention. 4, the same components as those in FIG. 1 are denoted by the same reference numerals. The semiconductor device of the third embodiment has a structure in which a groove 16a is provided around an opening at the center of the first surface of the frame component 3. When the resin enters the groove, the adhesion between the frame component 3 and the sealing resin is improved, and peeling is prevented.

FIG. 5 is an explanatory view showing a configuration of a semiconductor device according to Embodiment 4 of the present invention. 5, the same components as those in FIG. 1 are denoted by the same reference numerals. In the semiconductor device of the fourth embodiment, the external connection pads 18 connected to the metal wiring pattern layer 8 are formed on the lower surface of the first insulating material layer 6 provided with the through holes 9a.
Is formed, and in the frame component 3 joined on the wiring layer 1,
This is a structure in which a through hole 9c is provided so that the external connection pad 18 of the wiring layer 1 is exposed. The frame component 3 uses an insulating material. The through hole 9b is provided in the second insulating material layer 7, and the external connection terminal (solder bump) 10 is joined to the external connection region 11 formed in the wiring pattern layer 8.

FIG. 6 is an explanatory diagram showing a configuration of a semiconductor device according to Embodiment 5 of the present invention. 6, the same components as those in FIG. 1 are denoted by the same reference numerals. The semiconductor device of the fifth embodiment has a structure in which a conductive filling material 19 such as a solder paste is filled so as to be electrically connected to the external connection pads 18 of the wiring layer 1. According to the above configuration, by providing a through hole in the frame component 3, conduction between the upper and lower portions of the semiconductor device can be achieved. By connecting to the external connection pad 18 exposed by the through hole, an electrical test or the like after mounting becomes possible.

FIG. 7 is an explanatory diagram showing a configuration of a semiconductor device according to Embodiment 6 of the present invention. 7, the same components as those in FIG. 1 are denoted by the same reference numerals. The semiconductor device of the sixth embodiment has a structure in which a thin tape-shaped sealing component 20 is attached to an opening at the center of the first surface 12 of the frame component 3 in the semiconductor device so as not to increase the size of the package.

In order to manufacture the semiconductor device of the present invention using a mold (automatic assembling machine), the semiconductor device is manufactured in the same manner up to the step before resin sealing in the first embodiment, and the sealing component 20 is bonded to a predetermined position. Next, it is clamped by a mold, and is sealed with a resin through a groove 16b or a slit 21 provided in the frame component, thereby forming a resin sealing portion 5. The sealing resin used is a thermosetting resin such as an epoxy resin. Subsequent steps are the same as in the first embodiment. Further, the sealing member 20 may be joined to a predetermined position after resin sealing.

For example, by attaching the moisture-resistant sealing component 20, the absorption of moisture from the resin sealing portion 5 is reduced, so that the reliability of the semiconductor device is improved and the heat dissipation is improved. Also, by making the opening for resin sealing smaller, the contacting part of the injector can be made smaller,
Control of resin sealing is ensured.

FIG. 8 is an explanatory diagram showing a configuration of a semiconductor device according to Embodiment 7 of the present invention. 8, the same components as those in FIG. 1 are denoted by the same reference numerals. In the semiconductor device according to the seventh embodiment, in the wiring member 1 according to the first embodiment, the external connection pads 18 are provided on the second insulating material layer 7 side together with the external connection terminals 10 connected to the external connection regions 11 where the wiring pattern layer 8 is exposed. Is provided, and the area of the wiring member 1 where the external connection pads 18 are provided is folded back toward the first surface 12 of the frame component 3 at the outer peripheral portion of the frame component 3, and the external connection pads 18 of the wiring layer 1 are This is a structure in which the region of the first insulating material layer 6 corresponding to the provided region and the first surface 12 of the frame component 3 are joined.

According to the above configuration, since the external connection pads 18 are provided on the first surface 12 of the frame component 3, it is possible to connect to the external connection terminals of another semiconductor device. Therefore, it is possible to perform an electrical characteristic test after mounting the semiconductor device, and the external connection pad at this time can be used as a connection portion for lamination of the semiconductor device.

FIG. 9 is a plan view showing the appearance of the frame part according to the eighth embodiment of the present invention. The semiconductor device of the eighth embodiment shown in FIG. 9 has a structure in which a slit 21 is provided around an opening at the center of the frame component 3 of the first embodiment. According to the above configuration, the stress generated by the curing shrinkage or the like of the sealing resin is absorbed, and the flatness of the wiring layer 1 is maintained. It can also be used as an injection groove for resin sealing.

FIG. 10 is an explanatory view showing a test of the semiconductor device according to the ninth embodiment of the present invention. In the test of the semiconductor device of the ninth embodiment, for example, in the semiconductor devices of the fourth, fifth, and seventh embodiments, the external connection pad 18 or the conductive filling material 19 (not shown) is connected to the test tool 23. This makes it possible to test the semiconductor device after mounting the semiconductor device.

FIG. 11 is an explanatory view showing a laminated structure of a semiconductor device according to Embodiment 10 of the present invention. The stacked configuration of the semiconductor device of the tenth embodiment is the same as that of the semiconductor device of the fifth and seventh embodiments except that the external connection pad 18 or the conductive filler 1
By using 9 as a connection pad for stacking with another semiconductor device, it becomes possible to stack with another semiconductor device. Therefore, high-density mounting of the semiconductor device on the printed wiring layer becomes possible.

[0058]

According to the present invention, in a BGA type semiconductor device, a thin conductive wiring pattern layer is sandwiched between a thinned first insulating material layer and a thinned second insulating material layer.
The cost is reduced by using a flexible wiring layer with a layer structure, rigid and flat frame parts are joined and integrated just above the wiring pattern layer to which the external connection terminals are connected, and the flatness of the joint area of the external connection terminals is maintained. Furthermore, by resin-sealing the opening of the frame component, the frame component and the resin-sealed opening are integrated to suppress deformation of the package, thereby suppressing defects in the semiconductor device manufacturing process. In addition, it is possible to reduce mounting defects at the time of mounting the semiconductor device.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is an explanatory view illustrating a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is an explanatory diagram illustrating a configuration of a conductor device according to a third embodiment of the present invention.

FIG. 5 is an explanatory diagram illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is an explanatory diagram illustrating a configuration of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating a configuration of a semiconductor device according to a sixth embodiment of the present invention.

FIG. 8 is an explanatory diagram illustrating a configuration of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 9 is a plan view illustrating an appearance of a frame part according to an eighth embodiment of the present invention.

FIG. 10 is an explanatory diagram illustrating a test of a semiconductor device according to a ninth embodiment of the present invention.

FIG. 11 is an explanatory diagram illustrating a stacked configuration of a semiconductor device according to a tenth embodiment of the present invention.

FIG. 12 is an explanatory diagram showing a configuration of a conventional BGA type 1 semiconductor device.

FIG. 13 is an explanatory diagram showing a configuration of a conventional BGA type 2 semiconductor device.

FIG. 14 is an explanatory diagram showing a configuration of a conventional BGA type 3 semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wiring layer 2 Semiconductor chip 3 Frame part 4 Wire 5 Resin sealing part 6 First insulating material layer 7 Second insulating material layer 8 Wiring pattern layer 9a Through hole 9b Through hole 9c Through hole 10 External connection terminal 11 External connection Area 12 First surface of frame part 13 Second surface of frame part 14 Electrode 15 Internal connection area 16a Groove 16b Groove 17 Frame 17a Connection part 18 External connection pad 19 Conductive filling material 20 Seal part 21 Slit 22 Die pad 23 Test tool

Claims (6)

(57) [Claims] 1. A semiconductor chip having electrodes and the like, a flexible wiring layer including a conductive wiring pattern layer and first and second insulating material layers sandwiching the conductive wiring pattern layer, and the semiconductor chip can be housed. A frame component having an opening of a size and joined to the wiring layer to provide rigidity to the wiring layer; and a frame component electrically connected to an electrode of a semiconductor chip via a wiring pattern layer of the wiring layer to join the frame component. A plurality of external connection terminals formed immediately below the formed wiring layer, and the wiring pattern layer of the wiring layer is electrically connected to the external connection terminals.
External connection area having external connection pads connected to
Wherein the external connection region is a frame component bonded to a wiring layer.
External connection pad on the top of the frame component
A semiconductor device which is connected so as to be positioned, and when the semiconductor chip is housed in an opening of a frame component and joined to a wiring layer, the opening is sealed with a sealing resin. 2. The semiconductor device according to claim 1, wherein the frame component is provided with a groove having a predetermined width / depth around a shape near an opening. 3. The semiconductor device according to claim 1, wherein the frame component is provided with a plurality of slits having a predetermined width / depth symmetrically outward from an opening. 4. The semiconductor device according to claim 1, wherein said frame component has a through hole for electrically connecting said wiring pattern layer and a plurality of external connection terminals. 5. The semiconductor device according to claim 4, wherein the through-hole provided in said frame component is emphasized by a conductive material. 6. The semiconductor device according to claim 1, wherein an opening of the frame component is sealed with a sealing resin and a sealing component is attached.