JP3293959B2 - Synchronous processing device for digital modulated wave - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a demodulation device for digitally modulated waves used in satellite broadcasting, satellite communication, and the like, and to a synchronous processing device therefor.

[0002]

2. Description of the Related Art In a system for transmitting digital data, there is a digital modulation technique that is effective for high-quality transmission and improvement of frequency use efficiency. This digital modulation technique has been conventionally used in the fields of microwave terrestrial communication and satellite communication. As a digital modulation method, a quadrature amplitude modulation (QAM), a phase modulation (PSK) method, and the like are employed.

[0003] In recent years, with regard to such error correction technology that is indispensable for digital transmission technology, it has become possible to employ extremely powerful error correction codes with the development of IC technology. That is, the transmission bit error characteristic of the digital modulation method is theoretically determined by the carrier power-to-noise ratio (C / N) of the received signal. However, by correcting the transmission bit error on the receiving side by an error correction technique, Even with a very low C / N ratio, digital data can be transmitted with an error rate that is practically within a problem. For this reason, the demodulation circuit of the receiver is required to operate normally up to a very low C / N.

In recent digital demodulation wave demodulation systems, a synchronous detection system has been adopted to improve demodulation performance. In this synchronous detection method, a carrier component is extracted from a modulated wave itself (carrier wave reproduction), and the modulated wave is demodulated using this as a reference phase. When the C / N of the input modulated wave signal becomes low, the carrier recovery operation naturally deteriorates, and the C / N
Eventually, it becomes impossible to achieve phase synchronization between the input modulated wave signal and the reproduced carrier. So very low C
If the demodulation operation at / N is required and the carrier recovery operation has not been achieved, the demodulated data appearing in the demodulated output will necessarily be incorrect and exceed the error-correctable range, and error correction will not be possible. Becomes Therefore, correct data cannot be received.

In satellite broadcasting and satellite communication, frequency detuning generally occurs in a transmission system, especially in a frequency converter of a satellite repeater and a receiver. Synchronization must be achieved to achieve carrier recovery.

FIG. 14 shows a digital modulation wave demodulation device equipped with a carrier recovery circuit having a frequency pull-in function. The input modulation signal (intermediate frequency (IF) signal)
After the out-of-band noise is removed by the band-pass filter (BPF) 2, the signal is detected by the detector 3. The detector 3 is a multiplier in principle, and the other input is supplied with the output of the local oscillator 9. The local oscillator 9 is controlled by a carrier recovery phase locked loop (PLL) described later, and the output of the oscillator is a recovery carrier. The output of the detector 3 is inter-symbol interference removed by a low-pass filter (LPF) 4 and supplied to a clock recovery circuit 5 and an analog / digital (A / D) conversion circuit 6. The clock recovery circuit 5 is a circuit that extracts data timing from the detection output itself, and supplies a sampling timing signal to the A / D conversion circuit 6. The A / D conversion circuit 6 performs sampling and quantization at the center timing of an eye pattern that is sufficiently open after intersymbol interference is removed. In quantization, the number of bits is determined according to the digital modulation method. The output of the A / D converter 6 is distributed to a carrier recovery circuit 7 and an error correction circuit 11. The carrier recovery circuit 7
It forms a part of a phase locked loop (PLL), obtains a phase error from demodulated data, smoothes this, and outputs it. This output is supplied to the above-described local oscillator 9 via an adder 8.
To form a feedback loop.

Here, the sweep signal generation circuit 10 achieves the above-described frequency pull-in, and its operation will be described below. The output of the sweep signal generation circuit 10 is input to an adder 8 in a PLL provided between the carrier recovery circuit 7 and the local oscillator 9. That is, the output of the sweep signal generation circuit 10 can give an offset to the oscillation frequency control input of the local oscillator 9. Therefore, when the sweep signal is given to the adder 8, the frequency of the local oscillation output (reproduced carrier) is also swept. If the frequency of the input modulated wave is shifted, the frequency lock-in range of the PLL is generally limited, so that phase synchronization may not be achieved. However, if the local oscillation output can be swept as described above, the PLL can be synchronized when the sweep signal generates a signal that suppresses the frequency shift of the input modulated wave, and the phase locked state of the reproduced carrier wave is achieved. You.

The sweep signal generation circuit 10 must stop its operation instantaneously when the phase synchronization is achieved as described above during the sweep (during the AFC operation). In this example, a control signal for stopping the sweep operation is supplied from the error correction circuit 11. Since the error correction circuit 11 corrects an error in the demodulated data, the error correction circuit 11 can detect how much error has occurred. If it is determined that the error is very small, the control line 14 is flagged. This flag is given to the sweep signal generation circuit 10, and the circuit stops the sweep operation. At this time, phase synchronization has already been achieved. According to the above-mentioned system, the low C / C signal with uncertain carrier recovery including the frequency pull-in operation when the frequency detuning occurs.
The demodulation operation in N is realized.

[0009]

In the system described above, the sweep operation control signal supplied from the error correction circuit 11 is indispensable. The error correction circuit 11 also has a built-in synchronization determination function, and the erroneous synchronization determination output is also used for removing the phase uncertainty of the reproduced carrier (in QPSK modulation, four uncertainties occur). Therefore, it is necessary to sequentially check whether or not the carrier recovery PLL is synchronized and whether or not the phase uncertainty has been removed by using this false synchronization determination, and this determination takes time. That is, there is a problem that it takes time to start the demodulation operation.

Further, the sweep operation control signal is generated as a stop signal when the carrier wave recovery PLL is synchronized. That is, the frequency sweep operation and the PLL operation are performed simultaneously. Here, if the speed of the frequency sweep is high, P
The operation of the LL cannot follow this frequency pull-in (frequency change), so that normal phase synchronization cannot be achieved, and carrier wave recovery may not be normally obtained. For this reason, it is necessary to take measures to make the operation speed of the frequency sweep sufficiently lower than the operation speed of the PLL. As a result of this measure, there is a problem that the carrier recovery operation of the entire demodulator is delayed.

Further, since there is a signal returning from the error correction circuit 11 to a block (demodulation circuit 15) surrounded by a dotted line, there is a problem that an interface between them is complicated. If the demodulation circuit 15 and the error correction circuit 11 are integrated circuits, and these are configured in an independent form and combined to form a receiver, it is more convenient if these interfaces are as simple as possible.

In view of the above, the present invention provides a digital modulation system synchronous processing device capable of recovering a carrier wave at a high speed in a demodulator of a digital transmission system operating in a reception state having a low C / N and having frequency detuning. The purpose is to provide.

Further, the present invention provides a demodulator for a digital transmission system which operates in a reception state where a low C / N ratio and frequency detuning exist, so that a demodulator alone can detect a malfunction of a carrier recovery circuit. It is an object of the present invention to provide a synchronous wave synchronization processing device.

[0014]

According to the present invention, there is provided a synchronous detection means for obtaining a synchronous detection output by multiplying a digital modulation wave by a local oscillation output from a local oscillator, and a synchronous detection output of the synchronous detection means which is centered on an eye pattern. And a carrier recovery means for providing a phase error signal detected from the data output from the sampling means to the local oscillator as a phase error signal. Then, the amplitude of the output of the sampling means is detected, and this amplitude detection is performed.
Synchronization judgment is performed from the deviation of the amplitude distribution represented by the output and output.
If not, the amplitude detection output is divided by a plurality of thresholds.
The frequency of each region is calculated, and the magnitude
Numericalize the width distribution, and use this numerical output to
Calculate and obtain the synchronous / asynchronous judgment output from this calculation result
It is like that.

[0015]

According to the above-mentioned means, since there is a dedicated synchronization establishment determination and an AFC control circuit related thereto, it is possible to determine at high speed whether or not the reproduction PLL is synchronized. Time. Furthermore, carrier recovery PLL
Without being controlled by other circuits whether or not
The demodulator can be configured to be able to make a high-speed determination by itself. In this way, the interface with other circuits can be made very simple. As a result, the time required for carrier recovery of the receiver can be shortened, the configuration of the receiver system can be simplified, and the performance and cost of the digital modulation receiver can be reduced.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The basic concept of this embodiment will be described.

In this embodiment, a carrier wave can be reproduced at a high speed. Basically, a synchronous detecting means and a sampling means for sampling the synchronous detection output of the synchronous detecting means at a timing including the center of the eye pattern. A carrier recovery unit that detects a phase error using data output from the sampling unit and provides a phase control signal to the local oscillator, and a phase of the data using output data from the sampling unit. A phase synchronization state with the reference phase is determined exclusively, and if the synchronization state is asynchronous, a frequency control signal is created and supplied to the control terminal of the local oscillator, and if synchronized, the frequency control signal at that time is held. Dedicated synchronization determination and frequency control signal output means.

Generally, the demodulated output of a digitally modulated wave has a form called an eye pattern if the demodulation operation is normal. This eye pattern is a waveform in which the sample data value converges at the center timing. If the digital modulation is binary modulation, it converges to binary, and if it is quaternary, it converges to quaternary. In the case of quadrature modulation, convergence occurs at the in-phase axis and quadrature axis outputs. Here, if noise is superimposed on the input signal, noise is also superimposed on this eye pattern, but the amplitude distribution of the noise is generally a normal distribution.

Therefore, in this embodiment, the amplitude distribution at the center of the eye pattern of the signal on which noise is superimposed is obtained by the amplitude distribution detecting means, and a normal distribution is detected. For example, in the case of binary modulation, this distribution is a combination of two normal distributions having different average values, and the amplitude distribution is not uniform. When the phase synchronization of the demodulator is not achieved, a frequency beat of the difference between the input modulated wave having a different frequency and the output of the local oscillator appears in the output of the synchronous detector, and the amplitude distribution is closer to a uniform distribution. It will be.

The means for determining synchronization from the deviation of the amplitude distribution detects a difference between the amplitude distributions and identifies which state. That is, when it is determined that the amplitude distribution is not uniform and is close to a distribution obtained by combining a plurality of normal distributions, a synchronization determination signal is output.

A specific configuration will be described. The input modulation signal (intermediate frequency (IF) signal) is detected by a detector 3 after out-of-band noise is removed by a band limiting filter (BPF) 2. The detector 3 is a multiplier in principle, and the other input is supplied with the output of the local oscillator 9. The local oscillator 9 has a carrier recovery phase locked loop (PL
L), and the output of the oscillator is a recovered carrier. The output of the detector 3 is inter-symbol interference removed by a low-pass filter (LPF) 4 and supplied to a clock recovery circuit 5 and an analog / digital (A / D) conversion circuit 6. The clock recovery circuit 5 is a circuit that extracts data timing from the detection output itself, and supplies a sampling timing signal to the A / D conversion circuit 6. The A / D conversion circuit 6 samples and quantizes the input signal at the center timing of the eye pattern that is sufficiently open after intersymbol interference is removed. The quantization is
The number of bits is determined according to the digital modulation method.
The output of the A / D converter 6 is distributed to a carrier recovery circuit 7, an amplitude distribution detection circuit 102, and an error correction circuit 11. The carrier recovery circuit 7 forms a part of a phase locked loop (PLL), obtains a phase error from demodulated data, smoothes the phase error, and outputs it. This output is supplied to the control terminal of the local oscillator 9 via the adder 8 to form a feedback loop.

Here, the amplitude distribution detection circuit 102 is a circuit for detecting the amplitude distribution of the eye pattern, and the detection signal is input to the synchronization determination circuit 101. The synchronization determination circuit 101 determines the deviation of the amplitude from the amplitude information supplied from the amplitude distribution detection circuit 102, and determines whether the carrier recovery circuit 7 is in a synchronized state. When it is determined that the state is the synchronized state, the sweep operation of the sweep signal generation circuit 10 is stopped. The output of the sweep signal generation circuit 10 can give an offset to the oscillation frequency control input of the local oscillator 9. Therefore, if the sweep signal is given to the adder 8, the local oscillation output (regenerated carrier)
Is also swept. If the frequency of the input modulated wave is shifted, the frequency lock-in range of the PLL is generally limited, so that phase synchronization may not be achieved. However, if the local oscillation output can be swept as described above, the PLL can be synchronized when the sweep signal generates a signal that suppresses the frequency shift of the input modulated wave, and the phase locked state of the reproduced carrier wave is achieved. You.

Next, the principle of the above system will be described.
FIG. 2A shows a general binary eye pattern. This state is when the carrier recovery circuit 7 is synchronized and the C / N is sufficiently high. At the center timing of the eye pattern, the waveform converges to two points (± A amplitude).

FIG. 2B is a diagram for explaining the amplitude distribution when noise is superimposed on the eye pattern.
The vertical axis indicates the amplitude, and the horizontal axis indicates the probability of the amplitude at the center of the eye pattern. The convergence amplitude at the center of the eye pattern expands according to the C / N of the input modulation signal, and each convergence point ±
A has a normal distribution. The distribution curve indicated by the broken line in the figure is obtained by adding two normal distribution curves. The following equation represents this combined distribution curve.

[0025]

(Equation 1) In the above equation, σ is the standard deviation of the normal distribution, x is the amplitude variable, and A is the eye pattern amplitude. Σ is obtained by the following equation. Here, CN is C / N [dB].

[0026]

(Equation 2)

Now, assuming that C / N = infinity and 0 dB,
FIG. 3 shows the obtained composite distribution. As can be seen from the figure, even at C / N = 0, the distribution curve has a bias such that the eye pattern amplitude has a large value.

In normal digital modulation, C / N = 0 dB
In the following, the error rate approaches 0.5 and cannot be used, so that this method is practically sufficient. The above-described amplitude distribution detection circuit 102 obtains an amplitude distribution. Then, the synchronization determination circuit 101 determines the synchronization state of the carrier recovery circuit 7 from the deviation of the amplitude distribution.

FIG. 4 shows the amplitude distribution detecting circuit 102 in detail. The input signal supplied to the input terminal 501 is
This is an output signal from the A / D conversion circuit 6. The input terminal 501 is provided to the magnitude comparison circuits 502 to 506.
Each of the magnitude comparison circuits 502 to 506 detects a signal having a specific range of amplitude. Each of the comparison circuits 502 to 506
The connected counters 507 to 511 perform counting when the corresponding comparison circuit obtains the detection output, that is, obtain the frequency. Therefore, the signals y1 to y5 of the output terminals 512 to 516 of the respective counters 507 to 511 are obtained by approximating the amplitude distribution curve. Note that the magnitude comparison circuits 502 to 5
06 is arbitrary, but the eye pattern amplitude ± A
Are set to be included in some thresholds. In the figure, five magnitude comparison circuits are used, but this is not particularly limited. Since a signal that has already been digitized is input, it is also possible to obtain a distribution for each bit. In this case, the size comparison circuit becomes unnecessary. Counter clear terminal 51
7, a clear signal is given, which is given by a system controller (not shown) at an appropriate timing, for example, for a certain period from the start of reception.

FIG. 5 shows the synchronization determination circuit 101 in detail. Signal y2 at terminal 513 and signal y4 at terminal 515
Is input to the adder 601, and the signal y1 of the terminal 512
And the signal y3 at the terminal 514 and the signal y5 at the terminal 516 are
It is input to the adder 602. The output of the adder 601 (y2
+ Y4) and the output of the adder 602 (y1 + y3 + y5)
Is input to the division circuit 603. The output of the division circuit 602 is latched by a latch circuit 604. The output of this latch circuit 604 [(y1 + y3 + y5) / (y2 + y
4)] indicates a bias in the distribution characteristic, and the smaller the value is, the higher the possibility of phase synchronization is determined. That is, the output of the latch circuit 604 is input to the magnitude comparison circuit 606, and the reference value from the terminal 608 is compared. Then, the comparison result is output from the output terminal 14 as a synchronization determination result. When the output of the latch circuit 604 is smaller than the reference value, a synchronization output is obtained.

Here, the configuration for obtaining the ratio by the division operation has been described. However, the threshold value of the amplitude distribution detection circuit 102 is set so that the distribution becomes almost equal in an asynchronous state.
The division circuit 603 can be omitted. In the above description, the synchronization determination is performed periodically or intermittently using the latch circuit 604. However, the operation of the counter may be continuously operated as an up-down operation, and the synchronization determination may be performed continuously. It is.

The result of the above determination is a control signal for the sweep signal generation circuit 10 shown in FIG. When the synchronization state, that is, when the carrier recovery is achieved, the sweep signal is stopped.

In the above description, the digital modulation in which the input modulation signal is binary has been described, but this can be easily applied even in the case of multi-level or quadrature modulation. Next, QPSK is taken as the simplest example of quadrature modulation, and an embodiment in this case will be described.

FIG. 6A is a phase vector diagram (constellation) at the center of an ideal eye pattern of QPSK modulation. In a state with little noise, the constellation has converged to four points on the complex plane. FIG. 6 (B)
Is a construction when C / N is reduced to some extent. It can be seen that energy is concentrated around the convergence point as in the case of binary. In the case of the quadrature modulation method, the synchronization state can be determined from the one-dimensional amplitude distribution as in the previous embodiment. Here, the principle of determining the synchronization state two-dimensionally on the complex plane will be described. I do.

FIG. 7 shows that in the constellation, 2
An example in which two-dimensional amplitude distribution is obtained by performing two-dimensional area division is shown. The four black circles are symbol positions (convergence points), the surrounding area B is an area including the convergence point, and the other areas are indicated by area A. In the state where the carrier wave reproduction is asynchronous, the convergence point rotates, and almost all regions are almost established. However, when the phase synchronization is achieved, the probability of being included in the region B increases. Therefore, it suffices to detect the difference in the probability and perform the synchronization determination.

It should be noted that the present invention is not limited to the above-described area dividing method and the magnitude comparing / deciding method, and it is needless to say that other methods of detecting the amplitude distribution and detecting the bias of the amplitude distribution may be employed.

[0037] According to the actual施例described above, by the circuit for AFC controls associated only synchronization establishment determination and thereto is present, it can be determined whether fast reproduction PLL is synchronized, the demodulator operation It takes a short time to start. Furthermore,
The demodulator alone can determine at high speed whether or not the carrier recovery PLL is synchronized without being controlled by another circuit. Also, the interface with other circuits can be made very simple. As a result, the time required for carrier recovery of the receiver can be shortened, the configuration of the receiver system can be simplified, and the performance and cost of the digital modulation receiver can be reduced.

The present invention is not limited to the above embodiment. In the above embodiment, the sweep operation (AF
This is an embodiment in which the C operation) and the PLL operation proceed simultaneously. However, this operation may be performed in a time-division manner so as to gradually converge to a synchronized state.

FIG. 8 shows still another embodiment of the present invention. 1 are given the same reference numerals. In this embodiment, the demodulated data output of the A / D converter 6 is supplied to a synchronization determination and control circuit 211, a carrier recovery circuit 204, and a frequency shift detection circuit 202 as dedicated means for bringing the system into a synchronized state. I have.

The synchronization determination and control section 211 determines the establishment of carrier synchronization using the demodulated data, and controls the operation / non-operation of the carrier recovery circuit 204 and the frequency shift correction circuit 203 using the determination result. Is what you do. The frequency shift correction circuit 203 includes a frequency shift detection circuit 202.
This is a circuit for smoothing the frequency deviation detection output obtained from, and supplying this to the local oscillator 9 through the adder 8. In other words, this embodiment has a frequency deviation correction loop in addition to the phase locked loop for carrier recovery, and the operation of these loops is controlled by the synchronization determination and control circuit 211.

FIG. 9 shows the procedure of the carrier recovery operation of this embodiment. First, when the operation is started (step S
1) A predetermined period T in which the frequency pull-in operation is determined in advance
Only F is performed (step S2). Next, a phase pull-in operation is also performed for a predetermined period TP which is also determined in advance (step S3). At the same time as the phase synchronization operation (in the flowchart, the operations are sequentially performed for simplicity of description), or thereafter, carrier synchronization determination (phase synchronization between the input modulated wave and the reproduced carrier) is performed. If it is determined that the phase synchronization has not been achieved, the process returns to the frequency pull-in operation and the process is repeated (S4). Conversely, if it is determined that the phase synchronization has been achieved, it is determined that a synchronization has been established (step S5), and then the synchronization determination state is monitored. In this state, if the state becomes asynchronous again, the processing is repeated from the frequency pull-in operation again.

As described above, the frequency pull-in and the phase synchronization operation are sequentially performed, and the processing time is a predetermined fixed period. Note that, here, it has been described that the process of returning to the frequency pull-in operation is always performed at the time of the asynchronous determination. However, once the synchronization establishment determination is obtained, and immediately after the asynchronous determination is made, the process returns to the frequency pull-in operation. Without
It is also possible to configure so as to return to the phase pull-in operation. This is a case where a so-called cycle slip of the reproduced carrier circuit 202 is considered. At the time of the cycle slip, there is almost no frequency shift, so there is no need to re-pull the frequency shift, and the synchronization recovery time can be shortened by such a processing procedure.

FIG. 10 shows a process in which the frequency shift is suppressed until the synchronization is established when the carrier recovery operation is performed. In FIG. 10A, the horizontal axis represents time, and the vertical axis represents frequency shift. In the example of the solid line, time t = 0
, There is an initial frequency shift ΔF0, which is drawn in with time and becomes smaller, and finally the shift disappears, thereby achieving a phase synchronization. First, at time t = 0, the initial frequency deviation ΔF0 is gradually reduced, but the deviation is gradually reduced. After a predetermined frequency pull-in time, that is, at t = TF, the frequency pull-in is stopped, and the output of the frequency shift correction circuit 203 shown in FIG. 8 is held as it is. Next, a phase synchronization operation is performed. In this example, the frequency shift is too large to perform synchronization. After the predetermined phase synchronization operation period TP, the frequency pull-in operation is continued again. These operations are repeated in the same manner as above, and there is almost no frequency shift at t = 4TF. Thereafter, the phase synchronization is achieved and the carrier recovery operation is established.

Similarly, a broken line in FIG. 10B shows an operation example when the initial frequency shift is small. That is, FIG.
0 (B) shows an example in which the initial frequency shift is the same, but the slope of the frequency pull-in characteristic is different. This difference in characteristics is not a difference in circuit but a difference in the amount of noise included in the input signal. That is, when the carrier-to-noise ratio (C / N) of the digitally modulated wave is small, the slope of the characteristic is small and it takes time to pull in. However, as the C / N increases, the slope becomes large and the pull-in time becomes short.

Here, comparison will be made with the frequency pull-in by the conventional sweep method. In the conventional method, the pull-in time depends only on the initial frequency shift, and as described above, the sweep speed must be sufficiently low in order not to affect the phase synchronization. (Several to one-tenth of the band of the carrier recovery PLL)
You can only sweep frequencies at about the speed. For example, 1
If the bandwidth of the PLL is set to 10 KHz as / 10, sweeping of only about 1 KHz can be performed per second, and if it is attempted to pull in a frequency in the range of several MHz, it takes several thousand seconds.) Further, in this embodiment, when the C / N is increased, high-speed carrier wave regeneration is achieved as shown in FIG. 10B, but in the conventional system, it always takes a long time regardless of the C / N.

Next, the structure of each block in the above embodiment will be described. FIG. 11 shows a specific configuration example of the carrier recovery circuit 204. A / D input terminal 401
Demodulated data is supplied from the conversion circuit 4 (FIG. 8). The signal at the input terminal 401 is supplied to the phase detection circuit 402. The phase detection circuit 402 detects phase data θ for the modulation symbol. The phase data θ from the phase detection circuit 402 is supplied to the phase error detection circuit 403. The phase error detection circuit 403 calculates the phase data θ with respect to the reference phase.
Is detected. Although the reference signal for calculating the phase error is omitted in the figure, the multiplication between the oscillation output from the local oscillator and the input modulated wave has already been performed by the multiplier 3 in FIG. Therefore, for example, if the input modulation wave is QPSK modulation data, a phase error can be obtained by setting the reference phase to 45 ° and calculating the difference from the reference phase. The phase error Δθ is supplied to a multiplier 404 and an adder 406 that form a second-order loop filter. The multiplier 404 multiplies the coefficient αp.
The output of the multiplier 404 is input to the adder 405. The output of the adder 406 is supplied to a latch circuit 407, and the output of the latch circuit (delay circuit) 407 is
8 and is fed back to the adder 406 to implement the integration process. The multiplier 408 multiplies the coefficient βp by a coefficient, and the output is supplied to the adder 405.

The output of the adder 405 is supplied to an AND circuit 409
Supplied to one of the The control signal AFC / PLL supplied to the terminal 412 is supplied to the other end of the AND circuit 409 via the inverting circuit 410. When the frequency pull-in operation is instructed, the control signal AFC / PLL becomes high level “1”. Therefore, this control signal is output from the inverting circuit 4
Since the signal is inverted by 10 and supplied to the AND circuit 409, the output of the carrier recovery circuit 104 is cut off, and no PLL control signal appears at the output terminal 411. Conversely, when the control signal AFC / PLL becomes low level “0”,
The AND circuit 409 is controlled to be in a conductive state and enters a PLL operation mode.

FIG. 12A shows the frequency shift detecting circuit 20.
2 shows a specific configuration example. The input terminal 500
Demodulated data from the A / D conversion circuit 6 is supplied. This demodulated data is input to the phase detection circuit 501. The phase detection circuit 501 is the same as the phase detection circuit 402 described above. Therefore, both may be used in common. The phase data θ output from the phase detection circuit 501 is supplied to a latch circuit (delay circuit) 502 and a subtractor 503. The latch circuit 502 and the subtractor 503 implement a difference operation, which corresponds to performing time differentiation of the phase. Since the time derivative of the phase is a frequency, the output of the subtractor 503 indicates a phase change, that is, a frequency shift. This frequency deviation detection output is supplied to the frequency deviation correction circuit 203 through the terminal 504.

FIG. 12B shows a frequency shift correction circuit 203.
Is shown. The frequency shift detection information supplied to the terminal 600 is supplied to a secondary loop filter. The configuration and function of this loop filter is based on
This is exactly the same as the loop filter described in FIG. It comprises a multiplier 601, adders 602 and 603, a latch circuit 604, and a multiplier 605. Therefore, the description of the configuration and operation is omitted. The output of the loop filter is input to the latch circuit 606. A control signal input terminal 608 of the latch circuit 606 has a control signal AFC / PLL
Is supplied. The control signal is "1" when phase synchronization is established, and "0" when asynchronous. Therefore, when the control signal is “1”, the input / output is through (AFC mode), and when the control signal is “0”, the latch circuit 606 holds the value at that time (PLL mode). The output from the output terminal 607 is supplied to the adder 8.

FIG. 13A shows the synchronization judgment and control circuit 21.
1 is a specific configuration example. The input terminal 700 has an A / D
Demodulated data from the conversion circuit 6 is supplied. This demodulated data is supplied to the synchronization determination circuit 701. The synchronization determination circuit 701 is a circuit that determines synchronization from the number of bit errors of an error correction circuit in a transmission method using, for example, transmission line coding. The synchronization determination output of the synchronization determination circuit 701 is
It is supplied to an OR circuit 702 and a NOR circuit 705.
The OR circuit 702 is also supplied with a master reset signal from a terminal 707. The output of the OR circuit 702 is input to the monostable multivibrator 703, and the output of the monostable multivibrator 703 is further supplied to the monostable multivibrator 704. The output of the monostable multivibrator 704 is input to the NOR circuit 705 and the OR circuit 702.

The synchronization determination circuit 701 outputs logic "1" when it is determined that phase synchronization is established, and outputs logic "0" when it is determined that it is asynchronous. The monostable multivibrators 703, 704 are triggered on the falling edge of the pulse. The pulse output period of the monostable multivibrator 703 is set to TF. The pulse output period of the monostable multivibrator 704 is set to TP.

FIG. 13B is a timing chart for explaining the operation of the above circuit. When the master reset signal is input, the falling edge triggers the circuit 703 to output a pulse having a pulse width TF. Next, when this pulse falls, the circuit 704 is triggered and the pulse width T
The pulse of P is output. During the period when the synchronization determination output from the synchronization determination circuit 701 is “0”, the NOR circuit 70
The output 5 (the control signal AFC / PLL) becomes an AFC mode designation signal with a pulse width TF and a PLL mode designation signal with a pulse width TP. Here, when the synchronization determination output becomes “1”, the output of the NOR circuit 705 becomes a PLL mode designation signal. The output of the NOR circuit 705 is supplied to the control terminals of the carrier recovery circuit 204 and the frequency shift correction circuit 203 through the output terminal 706. As long as the synchronization determination output is “1”, the phase synchronization operation (PLL operation) of the system is continued. When the synchronization determination output becomes “0”, the falling edge triggers the circuit 703 again, and the frequency pull-in operation and the phase synchronization operation are repeated until the synchronization determination output becomes “1”.

As described above, according to this embodiment, the frequency pull-in operation (AFC) and the phase synchronization operation (PLL) are sequentially repeated, and finally the phase synchronization is achieved. According to this device, in a receiver of a digital transmission system that operates in a reception state where the C / N is low and a frequency detuning exists, the demodulator can reproduce a carrier wave at high speed. In the above embodiment, as shown in FIG. 8, an integrated circuit as a single demodulator including the synchronization determination and control circuit 211 and a single demodulator without the synchronization determination and control circuit 211 are used. An integrated circuit form is possible.

However, when an integrated circuit is formed as a single demodulator including the synchronization determination and control circuit 211, whether or not the carrier recovery PLL is synchronized is not controlled by another circuit, and the single demodulator is not controlled. It can be judged at high speed. Also, the interface with other circuits can be made very simple. As a result, the time required for carrier recovery of the receiver can be shortened, the configuration of the receiver system can be simplified, and the performance and cost of the digital modulation receiver can be reduced.

[0055]

As described above, in the demodulator of the digital transmission system operating in the receiving state where the present invention wave, low C / N, and frequency detuning exist, the carrier wave can be reproduced at high speed. Further, according to the present invention, in a demodulator of a digital transmission system operating in a reception state where the C / N ratio is low and a frequency detuning exists, a malfunction of the carrier recovery circuit can be detected by the demodulator alone.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing distribution characteristics of an eye pattern and a sampling output.

FIG. 3 is a diagram showing distribution characteristics of sampling output of binary data.

FIG. 4 is a diagram showing a specific example of the amplitude distribution detection circuit of FIG. 1;

FIG. 5 is a diagram showing a specific example of the synchronization determination circuit of FIG. 1;

FIG. 6 is a diagram showing a phase vector (constellation) at the center of an ideal eye pattern of QPSK modulation.

FIG. 7 is an explanatory diagram showing a case where two-dimensional enemy area division is performed in a construction in a modification of the first embodiment of the present invention.

FIG. 8 is a diagram showing another embodiment of the present invention.

FIG. 9 is a diagram showing an example of an operation procedure of the device in FIG. 8;

FIG. 10 is a diagram for explaining a change in frequency shift during the operation of the device in FIG. 8;

FIG. 11 is a diagram showing a specific example of the carrier recovery circuit of FIG. 8;

FIG. 12 is a diagram showing a specific example of a frequency shift detection circuit and a frequency shift correction circuit of FIG. 8;

FIG. 13 is a diagram showing a specific example of the synchronization determination and control circuit of FIG. 8 and its operation timing.

FIG. 14 is a diagram showing a conventional digital modulation wave demodulator.

[Explanation of symbols]

2 band-limited filter (BPF), 3 detector, 4 low-pass filter (LPF), 5 clock recovery circuit, 6 analog-digital conversion circuit, 7 carrier recovery circuit, 8 adder, 9 local Oscillator, 10 ... sweep signal generation circuit,
11 error correction circuit 101 synchronization determination circuit 102
Amplitude distribution detecting circuit, 203: frequency shift detecting circuit, 20
2: frequency shift correction circuit, 204: carrier wave recovery circuit, 2
11 ... Synchronization determination and control circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Noboru Taga 3-3-9, Shimbashi, Minato-ku, Tokyo Toshiba AV EE Co., Ltd. (56) References JP-A-62-147 (JP, A) JP-A-2-312337 (JP, A) JP-A-61-135262 (JP, A) JP-A-5-145588 (JP, A) JP-A-59-231924 (JP, A) (58) Field (Int. Cl. ⁷ , DB name) H04L 27/00-27/38

Claims (3)

(57) [Claims] 1. A synchronous detection means for multiplying a digital modulation wave by a local oscillation output from a local oscillator to obtain a synchronous detection output, and a sampler for sampling the synchronous detection output of the synchronous detection means at a timing including an eye pattern center. And a position detected from data output from the sampling unit.
A carrier recovery means for providing a phase error to the local oscillator as a phase control signal , and an amplitude of an output of the sampling means are detected.
Perform synchronization judgment from the bias of the amplitude distribution represented by force
Wherein the amplitude detection output is divided by a plurality of thresholds.
The frequency of each region is calculated, and the magnitude is compared by comparing the magnitudes.
Quantify the distribution and measure the amplitude distribution bias with this quantified output.
To obtain a synchronous / asynchronous judgment output from the calculation result.
A synchronous processing apparatus for a digital modulated wave signal, comprising: a period determining unit . 2. The digital modulation includes four-phase modulation.
The amplitude distribution is based on the in-phase axis output and
And two-dimensional amplitude distribution of orthogonal axis output.
The synchronous processing device for digitally modulated wave signals according to claim 1. 3. The sampling means according to claim 1, wherein
2. The synchronous processing apparatus for digitally modulated wave signals according to claim 1, wherein the synchronous processing apparatus is a conversion means .