JP3290779B2 - Semiconductor storage device and information storage method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device based on a novel operation principle and a method of storing information in the semiconductor memory device.

[0002]

2. Description of the Related Art In recent years, progress in semiconductor integrated circuits has been remarkable, and demands for higher speed and higher integration have been increasing. In particular, MOSF made of silicon semiconductor
High integration of semiconductor memory devices using ET is remarkable. For example, 1MO using one MOSFET for a memory cell
In the case of an S cell type dynamic memory (DRAM),
Currently, large-capacity DRAMs of 1 Mbit to 4 Mbits are commercially available, and large-capacity DRAMs of 64 Mbits to 128 Mbits are in the stage of trial production.

[0003] With the high integration of DRAM, transistors and capacitors constituting memory cells have been miniaturized, and the size of memory cells has also been miniaturized to about 2 µm square. In a 1 MOS memory type DRAM,
Since the storage states of 0 and 1 are identified by the amount of electric charge stored in the capacitor, the capacitance of the capacitor needs to be relatively large as compared with the external capacitance such as the wiring capacitance. is necessary. For this reason, a capacitor having a large surface area is realized in a memory cell having a small area by adopting a structure in which a groove is dug in a semiconductor substrate or a capacitor having a fin-type structure. However, even with such a method, miniaturization beyond the current state is difficult.

In addition to a DRAM as a semiconductor memory device, an electrically writable read-only memory (EP)
ROM) is known (SM G. ed., “Semiconductor Device”, page 501, A WILEY INTER SCIENCE PUBLIC)
ATION, 1981). Also in this EROM, it is necessary to provide three wirings which take a long time for electrical writing to one memory cell, and a very high voltage is required even when two wirings are used. It is a major barrier to integration.

[0005] In view of the above situation, research on a storage element (static RAM (SRAM)) using a differential negative resistance due to a quantum effect, particularly a resonance tunnel effect, has been conducted (Federico Capasso (Ed.), "Physics of Quantum
Electron Devices ", pp.207-208, Springer-Verlay, 19
90; Y. Watanabe, et al., "Monolithic Integrationof
InGaAs / InAlAs Resonant Tunneling Dioge and HEMT fo
r Single-TransistorCell SRAM Application ", IEEE IE
DM 92-475, 1992).

For example, a storage element using a resonant tunnel barrier (RTB) as a load element of an FET, or two resonant tunnel barriers connected in series, and the voltage at two stable points by the resonant tunneling barrier is reduced to the adjacent FET The information is written by changing the gate electrode of this FET.
There are proposed an SRAM element for reading stored information by using a threshold diode provided under two resonance tunneling barriers for writing and reading.

[0007]

However, even in these storage elements, there is a problem that the number of wirings per memory cell is three or more, and the area of the memory cell is not so small. Also, these storage elements
In order to retain the stored information by the valley current of the resonant tunnel barrier (RTB), it is desirable to make the valley current sufficiently smaller than the peak current. There is a problem that the valley current cannot be sufficiently reduced.

An object of the present invention is to provide a semiconductor memory device which has a simple structure, has a small number of wires per memory cell, can perform high-speed writing and high-speed reading, and is suitable for miniaturization, and an information storage method thereof. It is in.

[0009]

The object of the present invention is to provide a semiconductor substrate, a non-doped thick barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities. A thin barrier layer formed on the floating conductive layer and having an asymmetric barrier having a high barrier height on the floating conductive layer side; a channel layer formed on the thin barrier layer; and a thin layer formed on the channel layer. The present invention is achieved by a semiconductor memory device having a first electrode and a second electrode.

The above object is achieved by applying a write bias voltage having a higher potential to the second electrode than to the first electrode to the semiconductor memory device described above, thereby forming the thin barrier layer from the first electrode. Writing information into the floating electrode layer by injecting electrons into the floating electrode layer through the first electrode and the second electrode, applying a read bias voltage lower than the write bias voltage between the first electrode and the second electrode; The information stored in the floating electrode layer is read based on whether or not a current flows through the floating electrode layer.

The object is to provide a semiconductor substrate, a thick non-doped barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities, A thin barrier layer having an asymmetric resonance tunneling barrier having a high resonance level on the floating conductive layer side, a channel layer formed on the thin barrier layer, and a first layer formed on the channel layer. This is achieved by a semiconductor memory device having an electrode and a second electrode.

The above object is achieved by applying a write bias voltage having a higher potential to the second electrode than to the first electrode to the semiconductor memory device described above, thereby forming the thin barrier layer from the first electrode. Writing information into the floating electrode layer by injecting electrons into the floating electrode layer through the first electrode and applying a read bias voltage lower than the write bias voltage between the first electrode and the second electrode; Reading information stored in the floating electrode layer based on whether a current flows through the first electrode and the second electrode by applying an erase bias voltage higher than the write bias voltage to the first electrode and the second electrode. A method of storing information in a semiconductor memory device, wherein electrons stored in said floating electrode layer are emitted from a second electrode through said thin barrier layer to erase information in said floating electrode layer. It is achieved by.

The object is to provide a semiconductor substrate, a non-doped thick barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities, An intermediate barrier layer having an asymmetric barrier having a low barrier height on the floating conductive layer side, a channel layer formed on the intermediate barrier layer, and a barrier height formed on the channel layer. This is achieved by a semiconductor memory device comprising: a thin barrier layer having a symmetric barrier that does not change; and a first electrode and a second electrode formed on the thin barrier layer.

The object is to provide a semiconductor substrate, a thick non-doped barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities, An intermediate barrier layer having a symmetric barrier whose barrier height does not change, a channel layer formed on the intermediate barrier layer, and a thin barrier layer formed on the channel layer and having a resonant tunneling barrier. And a first electrode and a second electrode formed on the thin barrier layer.

[0015] The above object is achieved by applying a write bias voltage having a higher potential to the second electrode than to the first electrode to the semiconductor memory device described above, whereby the thin barrier layer and the thin layer are formed from the first electrode. Writing information into the floating electrode layer by injecting electrons into the floating electrode layer through the intermediate barrier layer; applying a read bias voltage lower than the write bias voltage between the first electrode and the second electrode; Reading information stored in the floating electrode layer based on whether a current flows in the channel layer and applying an erase bias voltage higher than the write bias voltage to the first electrode and the second electrode; Accordingly, the electrons stored in the floating electrode layer are released from the second electrode through the thin barrier layer and the intermediate barrier layer, thereby erasing information in the floating electrode layer. It is achieved by an information storage method for a semiconductor memory device according to claim.

The object is to provide a semiconductor substrate, a non-doped thick barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities, A thin barrier layer having an asymmetric barrier having a low barrier height on the floating conductive layer side; a channel layer formed on the thin barrier layer; a first electrode formed on the channel layer; This is achieved by a semiconductor memory device having a second electrode.

The above object is achieved by applying a write bias voltage having a higher potential to the second electrode than to the first electrode to the semiconductor memory device described above, so that the thin barrier layer is removed from the floating electrode layer. Forming an electron storage layer in the channel layer, writing information to the floating electrode layer, and setting a read bias lower than the write bias voltage between the first electrode and the second electrode. Applying a voltage, based on whether a current flows through the channel layer,
Reading the information stored in the floating electrode layer and applying an erase bias voltage lower than the write bias voltage and higher than the read bias voltage between the first electrode and the second electrode; And erasing information in the floating electrode layer by injecting electrons from the electron storage layer into the floating electrode layer through the thin barrier layer.

[0018]

According to the present invention, a non-doped thick barrier layer, a floating conductive layer doped with impurities, and a thin barrier layer having an asymmetric barrier with a high barrier height on the floating conductive layer side are provided on a semiconductor substrate. And a channel layer, and the first electrode and the second electrode are provided on the channel layer. By applying a writing bias voltage having a higher potential to the second electrode than to the first electrode, the first electrode Utilizing the fact that the amount of electrons injected into the floating electrode layer from the floating electrode layer through the thin barrier layer is larger than the amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer. Information is written by injecting electrons, and the stored information is determined based on whether or not a current flows through the channel layer when a read bias voltage lower than the write bias voltage is applied between the first electrode and the second electrode. To read It can be.

Further, according to the present invention, on a semiconductor substrate,
A non-doped thick barrier layer, a floating conductive layer doped with impurities, a thin barrier layer having an asymmetric resonance tunneling barrier having a high resonance level on the floating conductive layer side, and a channel layer are stacked. Since the first electrode and the second electrode are provided, by applying a write bias voltage having a higher potential on the second electrode than on the first electrode, the first electrode is injected into the floating electrode layer via a thin barrier layer. Utilizing that the amount of electrons to be emitted is larger than the amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer, electrons are injected into the floating electrode layer to write information, and the first electrode is written. When a read bias voltage lower than the write bias voltage is applied between the memory cell and the second electrode, the stored information is read based on whether a current flows in the channel layer, and an erase via higher than the write bias voltage is read. By applying a voltage to the first and second electrodes, the amount of electrons emitted from the floating electrode layer to the second electrode via the thin barrier layer is reduced from the first electrode to the floating electrode layer via the thin barrier layer. Utilizing the fact that the amount is larger than the amount of injected electrons, the information can be erased by discharging the electrons accumulated in the floating electrode layer.

Further, according to the present invention, on a semiconductor substrate,
A thick non-doped barrier layer, a floating conductive layer doped with impurities, an intermediate barrier layer having an asymmetric barrier with a low barrier height on the floating conductive layer side, a channel layer, and a symmetric barrier where the barrier height does not change And the first electrode and the second electrode are provided on the thin barrier layer. By applying a write bias voltage having a higher potential on the second electrode than on the first electrode, The amount of electrons injected from the first electrode into the floating electrode layer through the thin barrier layer and the intermediate barrier layer is smaller than the amount of electrons emitted from the floating electrode layer to the second electrode through the intermediate barrier layer and the thin barrier layer. Utilizing the fact that electrons are injected into the floating electrode layer from the first electrode through the thin barrier layer and the intermediate barrier layer to write information in the floating electrode layer, and a write bias voltage is applied between the first electrode and the second electrode. Also low By reading stored information based on whether a current flows through the channel layer when a read bias voltage is applied and applying an erase bias voltage higher than the write bias voltage to the first electrode and the second electrode, The amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer and the intermediate barrier layer is smaller than the amount of electrons injected from the first electrode to the floating electrode layer through the thin barrier layer and the intermediate barrier layer. Utilizing this fact, electrons accumulated in the floating electrode layer can be emitted from the second electrode through the thin barrier layer and the intermediate barrier layer to erase information in the floating electrode layer.

Further, according to the present invention, on a semiconductor substrate,
A non-doped thick barrier layer, a floating conductive layer doped with impurities, an intermediate barrier layer having a symmetric barrier whose barrier height does not change, a channel layer, and a thin barrier layer having a resonant tunneling barrier are stacked, Since the first electrode and the second electrode are provided on the thin barrier layer, by applying a write bias voltage having a higher potential on the second electrode than on the first electrode, the thin barrier layer and the intermediate barrier are removed from the first electrode. The amount of electrons injected into the floating electrode layer through the layer is changed from the floating electrode layer to the second through the intermediate barrier layer and the thin barrier layer.
Utilizing the fact that it is larger than the amount of electrons emitted to the electrode, electrons are injected into the floating electrode layer from the first electrode through the thin barrier layer and the intermediate barrier layer, and information is written into the floating electrode layer. When a read bias voltage lower than the write bias voltage is applied between the two electrodes, the stored information is read based on whether a current flows in the channel layer, and the erase bias voltage higher than the write bias voltage is set to the first. When applied to the electrode and the second electrode, the amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer and the intermediate barrier layer is increased from the first electrode to the thin barrier layer and the intermediate barrier layer. Utilizing the fact that the amount of electrons injected into the floating electrode layer is larger than the amount of electrons injected into the floating electrode layer, the electrons stored in the floating electrode layer are released from the second electrode through the thin barrier layer and the intermediate barrier layer, and information on the floating electrode layer is obtained. It is possible to be removed by.

Further, according to the present invention, on a semiconductor substrate,
A non-doped thick barrier layer, a floating conductive layer doped with impurities, a thin barrier layer having an asymmetric barrier with a low barrier height on the floating conductive layer side, and a channel layer are stacked, and a first layer is formed on the channel layer. Since the electrode and the second electrode are provided, by applying a write bias voltage having a higher potential on the second electrode than on the first electrode, the second electrode is discharged from the floating electrode layer to the second electrode via the thin barrier layer. Utilizing that the amount of electrons is larger than the amount of electrons injected from the first electrode into the floating electrode layer through the thin barrier layer, electrons are emitted from the floating electrode layer to write information, and the first electrode and the first electrode are written. When a read bias voltage lower than the write bias voltage is applied between the two electrodes, the stored information is read based on whether or not a current flows in the channel layer, and a write bias is applied between the first electrode and the second electrode. Read below voltage By applying an erase bias voltage higher than the bias voltage, electrons can be injected from the electron storage layer in the channel layer through the thin barrier layer into the floating electrode layer to erase information in the floating electrode layer. .

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIGS. On the semi-insulating InP substrate 10, a thick barrier layer 12 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 300 nm is formed. On the thick barrier layer 12, n-In _0.53 Ga _0.47 As with a doping amount of silicon (Si) of 5 × 10 ¹⁷ cm ⁻³ is provided.
A floating conductive layer 14 of about 200 nm in thickness is formed.

On the floating electrode layer 14, a non-doped i-
In _0.52 (AlxGa1-x) _0.48 As
A thin barrier layer 16 having a thickness of nm is formed. I-In _0.52 (AlxGa1-x) _0.48 As of thin barrier layer 16
The aluminum composition ratio (x value) linearly changes from x = 1.0 to 0.5 from the semi-insulating InP substrate 10 side to the surface side. The thin barrier layer 16 is shown in FIG.
As shown in (b), the barrier height on the floating electrode layer 14 side is as high as 0.53 eV, the barrier height gradually decreases, and the barrier height on the upper surface is 0.27 eV.

On top of the thin barrier layer 16 is a silicon dopant.
5 × 10¹⁷cm^-3N-In _0.53Ga_0.47As
A channel layer 18 having a thickness of about 30 nm is formed.
You. On the channel layer 18, a silicon doping amount of 5 ×
10¹⁷cm^-3From 5 × 10¹⁹cm^-3Changed to about 2
0 nm thick n-In_0.53Ga_0.47As layer 20a and silicon layer
5 × 10¹⁹cm^-3About 50 nm thick n
-In_0.53Ga_0.47Contact layer composed of As layer 20b
20 are formed. The contact layer 20 has two electrodes.
Protrusions for forming poles are provided.

The two convex portions of the contact layer 20 have approximately 2
A first electrode 22 and a second electrode 24 made of a tungsten silicide (WSi) layer having a thickness of 00 nm are formed. Instead of the tungsten silicide layer, the first electrode 22 and the second electrode 24 are formed of a chromium layer having a thickness of about 20 nm and a chromium layer having a thickness of about 190 nm.
A Cr / Au layer in which a thick gold layer is stacked, or a Pd / Ge layer in which a palladium layer having a thickness of about 60 nm and a germanium layer having a thickness of about 80 nm may be used.

Next, the storage method of the semiconductor memory device according to the present embodiment will be explained with reference to FIG. FIG. 2 is a graph showing the current-voltage characteristics of the thin barrier layer of this embodiment in the forward and reverse directions. First, a method for writing information will be described. When writing information to this semiconductor memory device, the first
One of the electrode 22 and the second electrode 24, for example, the first electrode 22
Are grounded, and a write bias voltage for setting the second electrode 24 to a positive potential is applied. When such a write bias voltage is applied, electrons flow from the first electrode 22 through the channel layer 18 to the second electrode 24 and are injected from the channel layer 18 into the floating electrode layer 14 through the thin barrier layer 16. Then, again, the thin barrier layer 16 tunnels to the channel layer 18 and finally reaches the second electrode 24.

As shown in FIG. 2B, the thin barrier layer 16 has a barrier height from the floating electrode layer 14 side to the channel layer 1.
It is inclined from 0.53 eV to 0.27 eV toward the 8th side. For this reason, the first electrode 22 to the floating electrode layer 14
As shown in FIG. 2 (c), the forward barrier for electrons flowing through has a band structure in which electrons easily tunnel. On the other hand, the barrier in the reverse direction for electrons flowing from the floating electrode layer 14 to the second electrode 24 has a band structure in which electrons do not easily tunnel as shown in FIG.

FIG. 2A shows current values flowing in the forward and reverse directions with respect to the bias voltage applied to the thin bias layer 16 having the inclined band structure at 77K. Up to a bias voltage of about 0.5 V, there is almost no difference between the current values in the forward and reverse directions, and the value is very small, about 0.5 A / cm ² . However, at about 0.9 V, the forward and reverse current values are 10 ⁵ A / cm in the forward direction.
^{2. In} the reverse direction, it is 10 ² A / cm ² , and the difference in current value is about 1000 times.

Therefore, when the first electrode 22 is grounded and a voltage of about 1.8 V is applied to the second electrode 24, at the time of application, a bias voltage (approximately about the same as the forward and reverse thin barrier layers 16) is applied. 0.9 V) is applied, so about 1 ps
Electrons corresponding to a charge amount of about 10 ⁻⁶ C / cm ² are accumulated in the floating electrode layer 14 within a very short time. As a result, the potential of the floating electrode layer 14 rises by about 0.2 V,
A voltage at which the forward current value and the reverse current value are substantially equal (in this case, 0.7V is applied to the thin forward barrier layer 16).
(Approximately 1.2 V across the thin barrier layer 16 in the opposite direction) to reach an equilibrium state, whereby electrons are accumulated in the floating electrode 14 and information can be written.

At this time, the voltage of the second electrode 24 is set to 0V.
Then, the potential of the floating electrode layer 14 increases by about 0.2 V.
However, it is assumed that the floating electrode layer 14 has increased by about 0.2V.
However, as shown in FIG. 2A, the current value in the forward direction is also reverse.
Direction current value is also 10^-FiveA / cm ^TwoOnly a floating electrode
The electrons stored in layer 14 are slowly released,
The state is maintained for about 10 ms. Furthermore, the floating electrode layer 1
4 emits electrons, the potential of the floating electrode layer 14 drops.
The electrons are then emitted more slowly. For example, floating
When the potential of the electrode layer 14 becomes about 0.1 V, the state becomes about
It is held for about 1 s.

Next, a method of reading information will be described. The current flowing from the first electrode 22 to the second electrode 24 through the channel layer 18 is only affected by the surface depletion layer when no charge is stored in the floating electrode layer 14, so that the first electrode 22 and the second electrode When a read bias voltage of about 1 V lower than the write bias voltage is applied during 24, a current of about 10 ³ A / cm ² flows.

On the other hand, when charges are stored in the floating electrode layer 14, a depletion layer extends from the floating electrode layer 14 and the channel layer 18 is almost depleted. Current hardly flows. As described above, the read bias voltage is applied to the first electrode 22 and the second electrode 2.
By detecting the presence or absence of a current flowing between the four, it is possible to read stored information depending on whether or not charges are accumulated in the floating electrode layer 14.

The first electrode 22 and the second electrode 24
When a read bias voltage of about V is applied, the thin barrier layer 16 is tunneled to connect the first electrode 22 to the second electrode 2.
Since the current flowing between the electrodes ⁴ is only about 10 ^-4 A / cm ^2, it does not affect reading of stored information. In the present embodiment, the electrons accumulated in the floating electrode layer 14 are released in about one second, and the stored information is lost.
It is possible to hold for about 24 hours.

The floating electrode layer 1 is irradiated with ultraviolet rays.
By discharging the electrons stored in the information 4, the information can be erased collectively. In this embodiment, since the barrier height is low, it can be erased even with visible light. It is desirable that the semiconductor memory device of the present embodiment be operated at a low temperature of 77 K or less in order to suppress a thermoelectric current component.

As described above, according to the present embodiment, a read-only memory (EPROM) which can be electrically written at high speed at high speed.
Can be realized. Since only two wirings need to be provided, high integration is possible and the writing time can be shortened. In addition, a conventional DR using a write voltage of silicon
It can be reduced to about one tenth of the AM element. Next, a method of manufacturing the semiconductor memory device according to the present embodiment will be described.

First, electron beam epitaxy (MB
The thick barrier layer (buffer layer) 12 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 300 nm, and the silicon doping amount is 5 × 10 ¹⁷ cm ⁻³ on the semi-insulating InP substrate 10 by the E) method. About 200 nm thick floating conductive layer 14 made of n-In _0.53 Ga _0.47 As
-In _0.52 (AlxGa1-x) _0.48 About 2
0 nm thick barrier layer 16 with silicon doping of 5
An about 30 nm thick channel layer 18 of n-In _0.53 Ga _0.47 As of × 10 ¹⁷ cm ^-3 and a silicon doping amount of 5
An n-In _0.53 Ga _0.47 As layer 20a having a thickness of about 20 nm changed from × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁹ cm ^−3, and an n-in thickness of about 50 nm having a silicon doping amount of 5 × 10 ¹⁹ cm ⁻³
Continuously growing a crystal of -In _{0. 53} Ga _0.47 As layer 20b.

Next, about 200 n is formed on the contact layer 20.
m thick tungsten silicide (WSi) layer, about 20 n
C having a chrome layer of about m thickness and a gold layer of about 190 nm thickness
r / Au layer or about 60 nm thick palladium layer and about 8
A Pd / Ge layer in which a germanium layer having a thickness of 0 nm is laminated is formed. Subsequently, the first electrode 22 and the second electrode 24 are formed by pattern etching using a normal photolithography technique.

Next, using the first electrode 22 and the second electrode 24 as a mask, the first electrode 22 and the second electrode are etched by RIE using CH ₄ and H ₂ under the conditions of a gas pressure of 4 Pa and an RF power of 60 W. the n-in _0.53 Ga _0.47 as layer 20b and the n-in _0.53 Ga _{0. 47} as layer 20a between with etched away, to the first electrode 22 reaches the thick barrier layer 12 so as to surround the second electrode 24 etch By removing, the semiconductor memory device of this embodiment is completed.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted or simplified. In this embodiment, in order to prevent the surface leakage current between the floating conductive layer 14 and the channel layer 18, as shown in FIG. 3, Protection of about 300nm thick made of undoped i-In _0.52 Al _0.48 As to the side A layer 26 is provided.

After mesa etching around the first electrode 22 and the second electrode 24, non-doped i-In _0.52 Al
A protective layer 26 made of _0.48 As and having a thickness of about 300 nm is formed. According to this embodiment, since the side surface is covered with the protective layer, the surface leakage current is prevented, and the retention time of the stored information by the electrons accumulated in the floating electrode layer is extended.

Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted or simplified. On the semi-insulating InP substrate 10, a non-doped i
-In _0.52 Al _0.48 to about 300nm thickness of a thick barrier layer 12 made of As, doping amount of silicon 5 × 10 ¹⁷ cm ^-3
About 200 nm thick floating conductive layer 14 of n-In _0.53 Ga _0.47 As, and In _0.52 (AlxGa1-x) _0.48 A
The thin barrier layers 16 each having a thickness of about 30 nm made of s are sequentially stacked.

In _0.52 (AlxGa) of the thin barrier layer 16
1-x) The composition ratio (x value) of _0.48 As aluminum is
From the semi-insulating InP substrate 10 side toward the surface side, x =
It changes linearly from 1.0 to 0.5. For this reason, as shown in FIG. 4B, the barrier height of the thin barrier layer 16 on the floating electrode layer 14 side is as high as 0.53 eV, the barrier height gradually decreases, and the barrier height on the upper surface decreases. 0.2
7 eV. Also, as shown in FIG.
Part of the surface of the thin barrier layer 16 or the thin barrier layer 1
All 6 are doped with silicon to a doping amount of 1 × 10 ¹⁸ cm ⁻³ .

On the thin barrier layer 16, a non-doped i
A channel layer 18 of about 30 nm thick made of -In _0.53 Ga _0.47 As is formed. Electrons seep out of the thin barrier layer 16 into the channel layer 18 and 2
A two-dimensional electron channel 28 is formed. Thin barrier layer 16
Since the electrons seep out and are depleted, they function similarly to the thin barrier layer 16 made of non-doped In _0.52 (AlxGa1-x) _0.48 As.

The configuration and operation other than the formation of the two-dimensional electron channel in the channel layer are the same as those of the first embodiment, and therefore the description is omitted. According to the present embodiment, since information is read depending on whether or not a current flows through the two-dimensional electron channel in the channel layer, information can be read at a very high speed.

Next, a semiconductor memory device according to a fourth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted or simplified. On the semi-insulating InP substrate 10, about 300 nm made of non-doped i-In _0.52 Al _0.48 As, as in the first embodiment.
Thick barrier layer 12 with silicon doping of 5 × 10
Approximately 200 of ¹⁷ cm ^-3 n-In _0.53 Ga _0.47 As
The floating conductive layers 14 having a thickness of nm are sequentially stacked.

On the floating conductive layer 14, instead of the thin barrier layer 16 having the asymmetric barrier height in the first to third embodiments, a resonant tunneling barrier having an asymmetric resonance level is used. A thin barrier layer 30 having (RTB) is formed. The thin barrier layer 30 is shown in FIG.
As shown in (b), from the floating conductive layer 14 side, the i-AlAs barrier layer 3 having a barrier height of 1.36 eV and a thickness of about 3 nm is formed.
0a, i-InGaAs well layer 30b about 3 nm thick, i-In _0.35 A about 3 nm thick with a barrier height of 0.785 eV.
l _0.65 As barrier layer 30c, i-InGa of about 3 nm thickness
As well layer 30d, barrier height 0.53 eV, about 3 nm
It has a structure in which a thick i-In _0.52 Al _0.48 As barrier layer 30e is stacked.

On the thin barrier layer 30, a silicon
5 × 10¹⁷cm^-3N-In _0.53Ga_0.47As
A channel layer 18 of about 30 nm thickness,
5 × 10¹⁷cm^-3From 5 × 10¹⁹cm^-3Change up to
About 20 nm thick n-In_0.53Ga_0.47As layer 20
a, the silicon doping amount is 5 × 10¹⁹cm^-3About 50n
m-thick n-In_0.53Ga_0.47A capacitor composed of the As layer 20b
The tact layers 20 are sequentially stacked. This contact
A first electrode 22 and a second electrode 24 are formed on the layer 20.
I have.

Next, the storage method of the semiconductor memory device according to the present embodiment will be explained with reference to FIG. FIG. 6 is a graph showing the current-voltage characteristics of the thin barrier layer of this example in the forward and reverse directions. As is apparent from FIG. 6, the thin barrier layer 30 having the resonant tunneling barrier in the present embodiment.
The applied voltage is 0.5
It hardly flows up to about V. However, when the applied voltage is 0.8
At V, the thin barrier layer 30 is in a resonant tunneling state in the forward direction and a current of about 4 × 10 ⁴ A / cm ² flows, whereas the thin barrier layer 30 is not in a resonant state in the reverse direction and is 10 ^1. A current of only about A / cm ² flows.

Conversely, when the applied voltage becomes 1.5 V, the thin barrier layer 30 becomes non-resonant in the forward direction and becomes 10 ²
While a current of only about A / cm ² flows, the thin barrier layer 30 enters a resonant tunneling state in the opposite direction, and a reverse phenomenon occurs in which a current of about 4 × 10 ⁴ A / cm ² flows. In this embodiment, by utilizing this reversal phenomenon, it is possible to erase information as well as write information.

One of the first electrode 22 and the second electrode 24, for example, the first electrode 22 is grounded, and the second electrode 24 is set to about 1.6V.
Potential. When such a write bias voltage is applied, the current flowing in the thin barrier layer 30 in the forward direction becomes
1 ps because it is much larger than the current flowing in the reverse direction
Electrons are injected into the floating electrode layer 14 in a short time of 10 to 10 ps. When electrons are accumulated in the floating electrode layer 14, the potential of the floating electrode layer 14 increases by about 0.2V.

In this state, when the voltage applied to the second electrode 24 is set to 0 V, the potential of the floating electrode layer 14 is maintained at about 0.2 V for a certain period of time, for example, about 1 μs. Next, when electrons are accumulated in the floating electrode layer 14 and an erase bias voltage of about 3 V higher than the write bias voltage is applied between the first electrode 22 and the second electrode 24, the thin barrier layer 30 is moved in the forward direction. The current flowing in the reverse direction is larger than the current flowing in the floating electrode layer 14, and the electrons stored in the floating electrode layer 14 are emitted from the second electrode 24 through the thin barrier layer 30 to erase the stored information.

On the other hand, a current flowing from the first electrode 22 to the second electrode 24 through the channel layer 18 is affected only by the surface depletion layer when no charge is accumulated in the floating electrode layer 14. When a read bias voltage of about 1 V lower than the write bias voltage is applied between the second electrode 22 and the second electrode 24, a current of about 10 ³ A / cm ² flows.

On the other hand, when charges are accumulated in the floating electrode layer 14, a depletion layer extends from the floating electrode layer 14 and the channel layer 18 is almost depleted. Current hardly flows. As described above, the read bias voltage is applied to the first electrode 22 and the second electrode 2.
By detecting the presence or absence of a current flowing between the four, it is possible to read stored information depending on whether or not charges are accumulated in the floating electrode layer 14.

In this embodiment, a so-called bistable state circuit in which two resonant tunnel barriers are connected in series is not used. The applied voltage is determined according to the characteristics of the barrier. According to this embodiment, when a write bias voltage of about 1.6 V is applied between the first electrode 22 and the second electrode 24, electrons are accumulated in the floating electrode layer 14 and the stored information 1 is written, and the first electrode 22 is written. When an erasing bias voltage of about 3 V is applied between the second electrode 22 and the second electrode 24, the electrons stored in the floating electrode layer 14 are released, and the storage information 0 is written. A dynamic RAM (DRAM) can be realized using such an information write / erase operation.

However, the stored information in the semiconductor memory device of this embodiment disappears after a certain period of time.
Refresh control for rewriting the stored information within that time is required. In order to extend the retention time of the stored information to about 1 s, it is effective to make the barrier on the substrate side of the thin barrier layer 16 thicker or higher. The barrier layer 30a on the substrate side is made of i-In _0.52 Al having a thickness of about 20 nm.
_{When the 0.48} As layer 30a is used, the storage time at 0.2V is 1
About 10 s to about 10 s. This is a silicon MOSFET
And the holding time of a DRAM using a capacitor. In order to extend the holding time, it is desirable that the mesa portion be buried with i-InAlAs.

Next, a semiconductor memory device according to a fifth embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the fourth embodiment shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted or simplified. On the semi-insulating InP substrate 10, a non-doped i-In _0.52 Al _0.48 As
A thick barrier layer 12 of about 300 nm in thickness is formed. On the thick barrier layer 12, n-In _0.53 Ga with a silicon doping amount of 5 × 10 ¹⁷ cm ⁻³ is formed in the same manner as in the fourth embodiment in a state where the elements are separated into the region on the left side of FIG.
A floating conductive layer 14 made of _0.47 As and having a thickness of about 200 nm, a resonant tunneling barrier (RT) having an asymmetric resonance level.
A thin barrier layer 30 having B) is formed.

As in the case of the fourth embodiment, the thin barrier layer 30 is formed from the side of the floating conductive layer 14 by a barrier height of 1.36 eV and an i-AlAs barrier layer 30a of about 3 nm thickness, and an i-AlGaAs barrier layer of about 3 nm thickness. Well layer 30b, barrier height 0.78
5 eV about 3 nm thick i-In _0.35 Al _0.65 As barrier layer 30 c, about 3 nm thick i-InGaAs well layer 30
d, about 3 nm thick i-In with a barrier height of 0.53 eV
_{A 0.52} Al _0.48 As barrier layer 30e is laminated. In the present embodiment, a part of the thin barrier layer 30 on the surface side or the entire thin barrier layer 30, for example, the uppermost layer i-In _0.52
The Al _0.48 As barrier layer 30e is doped with silicon to a doping amount of 1 × 10 ¹⁸ cm ⁻³ .

On the thin barrier layer 30, a non-doped i
-In _0.53 Ga _0.47 channel layer 18 of approximately 30nm thickness consisting of As, n-I of about 20nm thickness was varied doping amount of silicon from 5 × 10 ¹⁷ cm ^-3 to 5 × 10 ¹⁹ cm ^-3
n _0.53 Ga _0.47 As layer 20a, silicon doping amount is 5
× 10 ¹⁹ cm n-In _0.53 to about 50nm thick ^-3 Ga _{0. 47}
The contact layers 20 composed of the As layers 20b are sequentially stacked. On this contact layer 20, a first electrode 22 and a second electrode 24 are formed. In this manner, the semiconductor memory device of the present embodiment is formed in the left region on the semi-insulating InP substrate 10.

In the semiconductor memory device of this embodiment, electrons leak from the thin barrier layer 30 into the channel layer 18, and a two-dimensional electron channel 28 is formed in the channel layer 18.
The operation other than the formation of the two-dimensional electron channel in the channel layer is the same as that of the fourth embodiment, and the description is omitted. On the other hand, a HEMT having a layer structure similar to that of the semiconductor memory device is also formed in the right region on the semi-insulating InP substrate 10. In other words, the silicon doping amount is 5 × 10 ¹⁷ cm ⁻³ on the thick barrier layer 12 while the elements are separated.
A n-In _0.53 Ga _0.47 As layer 32 having a thickness of about 200 nm;
The electron supply layer 34, the active layer 36, and the contact layer 20 are sequentially stacked.

The electron supply layer 34 has a layer structure having a resonance tunneling barrier (RTB) having an asymmetric resonance level as in the thin barrier layer 30 of the semiconductor memory device, and has an n-In _0.53 Ga _0.47 An i-AlAs barrier layer 3 having a barrier height of 1.36 eV and a thickness of about 3 nm from the As layer 32 side.
0a, i-InGaAs well layer 30b about 3 nm thick, i-In _0.35 A about 3 nm thick with a barrier height of 0.785 eV.
l _0.65 As barrier layer 30c, i-InGa of about 3 nm thickness
As well layer 30d, barrier height 0.53 eV, about 3 nm
A thick i-In _0.52 Al _0.48 As barrier layer 30e is laminated. Part of the surface side of the thin barrier layer 30 or the entire thin barrier layer 30, for example, the uppermost i-In _0.52 A
The l _0.48 As barrier layer 30e is doped with silicon to a doping amount of 1 × 10 ¹⁸ cm ⁻³ .

The active layer 36 has a thickness of about 3
0nm made of non-doped i-In _{0. 53} Ga _0.47 As having a thickness. Electrons seep from the electron supply layer 34 into the active layer 36, and a two-dimensional electron channel 38 is formed in the active layer 34. A source electrode 40 and a drain electrode 42 are formed on the contact layer 20, and a gate electrode 44 made of tungsten silicide (WSi) or aluminum (Al) is formed on the active layer 36 between the source electrode 40 and the drain electrode 42. Is formed.

According to the present embodiment, information is read based on whether or not a current flows through the two-dimensional electron channel in the channel layer, so that information can be read at a very high speed. Further, the same semi-insulating In as in the semiconductor memory device is used.
A HEMT can be formed on a P substrate, and a peripheral circuit for amplifying stored information and a memory element can be easily formed. Next, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

On the semi-insulating InP substrate 10, a thick barrier layer 12 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 300 nm is formed. Thick barrier layer 1
2 on which n is doped with 1 × 10 ¹⁸ cm ⁻³ of silicon.
A floating conductive layer 14 of about 200 nm thick made of -In _0.53 Ga _0.47 As is formed. On the floating electrode layer 14,
Non-doped i-In _0.52 (AlxGa1-x) _0.48 A
An intermediate barrier layer 46 of about 200 nm thick is formed. The i-In _0.52 (Al
xGa1-x) _0.48 As composition ratio of aluminum (x
Value) increases linearly from x = 0.5 to 0.75 from the substrate side to the surface side. Intermediate barrier layer 46
As shown in FIG. 8C, the barrier height on the floating electrode layer 14 side is as low as 0.27 eV, the barrier height is gradually increased, and the barrier height on the upper surface is 0.41 eV. .

On the intermediate barrier layer 46, a silicon
1 × 10¹⁸cm^-3N-In _0.53Ga_0.47As
A channel layer 48 having a thickness of about 30 nm.
You. On the channel layer 48, a non-doped i-In_0.52
Al_0.48A thin barrier layer 50 of about 20 nm thick made of As
Is formed. The thin barrier layer 50 is shown in FIG.
As shown, the barrier height is always symmetrical with 0.53 eV.
Has a barrier.

On the thin barrier layer 50, an n-In _0.53 Ga _0.47 As layer 52 of about 20 nm thickness in which the doping amount of silicon is changed from 5 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁹ cm ^−3.
a and a silicon doping amount of about 60 × 10 ¹⁹ cm ⁻³ .
a contact layer 52 made of nm thick n-In _0.53 Ga _{0. 47} As layer 52b is formed. Contact layer 52
Are provided with protrusions for forming two electrodes, and the first electrode 22,
A second electrode 24 is formed.

Next, the storage method of the semiconductor memory device according to the present embodiment will be explained. First, a method for writing information will be described. When writing information to the semiconductor memory device, one of the first electrode 22 and the second electrode 24, for example, the first electrode 22 is grounded, and the second electrode 24 is set to 1.5 to 2.0V.
A write bias voltage is applied to make the potential about positive.
When such a write bias voltage is applied, electrons are injected from the first electrode into the thin channel layer 48 through the thin barrier layer 50. The electrons injected into the thin channel layer 48 become hot electrons having an energy of about 0.5 to 0.6 eV, pass through the intermediate barrier layer 46, are injected into the thick floating conductive layer 14, and are accumulated.

When electrons are accumulated in the thick floating conductive layer 14, the potential of the floating conductive layer 14 increases, and the channel layer 48 is depleted from the semi-insulating InP substrate 10 side. When the channel layer 48 is depleted, the second through the channel layer 48
No electrons flow into the electrode 24, and no current flows from the second electrode 24 to the first electrode 22. Thus, the state in which the electrons are accumulated in the floating conductive layer 14 can be written as the storage information “1”.

Next, a method for reading information will be described. When no charge is accumulated in the floating electrode layer 14, the channel layer 48 is not depleted. Therefore, when a read bias voltage of about 1 V lower than the write bias voltage is applied between the first electrode 22 and the second electrode 24, , 10 ³ A
/ Cm ² flows.

On the other hand, in the state where charges are accumulated in the floating electrode layer 14, the depletion layer extends from the floating electrode layer 14, and the channel layer 48 is almost depleted, and the space between the first electrode 22 and the second electrode 24 is formed. Current hardly flows. As described above, the read bias voltage is applied to the first electrode 22 and the second electrode 2.
By detecting the presence or absence of a current flowing between the four, it is possible to read stored information depending on whether or not charges are accumulated in the floating electrode layer 14.

In a state where electrons are not accumulated in the floating conductive layer 14 (stored information “0”), even if a read bias voltage of about 1 V is applied, electrons injected into the channel layer 48 will not be thick intermediate barrier. Since the light is reflected by the layer 46 and does not reach the floating conductive layer 14, electrons are injected into the floating conductive layer 14 by reading information and stored information is not changed.

In the state where electrons are accumulated in the floating conductive layer 14 (stored information “1”), the channel layer 48 is depleted, so that at a read bias voltage of about 1 V,
Since almost no electrons are injected, there is no change in stored information due to emission of electrons from the floating conductive layer 14 by reading information. Next, a method of erasing written information will be described.

In the state where electrons are accumulated in the floating conductive layer 14 and information is written, 3-4 between the first electrode 22 and the second electrode 24
When a voltage of about V is applied, i-In _0.52 (AlxGa
1-x) A current flows through the intermediate barrier layer 46 made of _0.48 As. At this time, the intermediate barrier layer 46 has a lower barrier height from the surface side toward the substrate side, and therefore has a higher current than the current flowing from the first electrode 22 to the floating conductive layer 14.
The current from the floating conductive layer 14 to the second electrode 24 is larger, and the electrons accumulated in the floating conductive layer 14 are released to the second electrode 24, and the written information is erased.

When the electrons accumulated in the floating conductive layer 14 are released, the depletion layer of the channel layer 48 becomes short, and a current flows between the first electrode 22 and the second electrode 24 when a read bias voltage is applied. It will flow. In this embodiment, if the thickness of the intermediate barrier layer 46 is increased, the electrons accumulated in the floating conductive layer 14 can be hardly released, and the retention time of the stored information “1” can be made extremely long, for example, about 10 minutes. be able to. Note that a state in which no electrons are accumulated in the floating conductive layer 14 (storage information “0”) is maintained forever unless writing is performed.

As described above, according to the present embodiment, a read-only memory (EPROM) that can be electrically written at high speed is used.
Memory that can be written and read and needs to be rewritten (D
RAM). Since only two wirings need to be provided, high integration is possible and the writing time can be shortened. Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the sixth embodiment shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

On the semi-insulating InP substrate 10, a thick barrier layer 12 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 300 nm is formed. On this thick barrier layer 12, n-In _0.53 Ga _0.47 As is separated from the left region of FIG.
About 200 nm thick floating conductive layer 14, i-In _0.
52 (AlxGa1-x) _0.48 As, about 200 nm
The thickness of the intermediate barrier layer 46, n-In _0.53 Ga _0.47 channel layer 48 of approximately 30nm thickness consisting of As, i-In _{0. 52} Al
A thin barrier layer 50, n of about 20 nm thick made of _0.48 As
-In _0.53 Ga _0. contact layer 50 made of ₄₇ As is formed, is on the contact layer 50 is formed between the first electrode 22 second electrode 24. Thus, semi-insulating In
The semiconductor memory device of the present embodiment is formed in a left region on the P substrate 10.

On the other hand, in the right region on the semi-insulating InP substrate 10, HET and RH having the same layer structure as the semiconductor memory device are provided.
ET is formed. That is, on the thick barrier layer 12, n-In _0.53 Ga _0.47 As
About 200 nm thick collector layer 54, i-In
About 200n consisting of _0.52 (AlxGa1-x) _0.48 As
An m-thick barrier layer 56, a base extraction layer 58 of about 30 nm thickness made of n-In _0.53 Ga _0.47 As, i-In _0.52 A
a thin base layer 60 of about 20 nm thick made of l _0.48 As;
About n-In _0.53 Ga _0.47 As An emitter layer 62 having a thickness of nm is formed stepwise.

The collector layer 54 corresponds to the floating conductive layer 14, the barrier layer 56 corresponds to the intermediate barrier layer 46, the base extraction layer 58 corresponds to the channel layer 48, and the base layer 60
Corresponds to the thin barrier layer 50, and the emitter layer 62 corresponds to the contact layer 52. A collector electrode 64 is formed on the collector layer 54, a base electrode 66 is formed on the base extraction layer 58, and an emitter electrode 68 is formed on the emitter layer 62.

As described above, in the region on the right side of the semi-insulating InP substrate 10, a multi-emitter type InGaAs /
An In (AlGa) As hot electron transistor (HET) or a resonant tunneling hot electron transistor (RHET) can be formed. next,
A semiconductor memory device according to an eighth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device of the sixth embodiment shown in FIG. 8 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

A thick barrier layer 12 and a floating conductive layer 14 are formed on a semi-insulating InP substrate 10, and an intermediate barrier layer 46 is formed on the floating electrode layer 14. The intermediate barrier layer 46 of the present embodiment is made of i-In _0.52 (Al _0.875 Ga _0.125 ) having a thickness of about 30 nm.
_{It is made of 0.48} As, and has a constant symmetric barrier with a barrier height of 0.46 eV, as shown in FIG.

A channel layer 48 is formed on the intermediate barrier layer 46, and a thin barrier layer 70 having a resonant tunneling barrier (RTB) is formed on the channel layer 48. As shown in FIG. 10A, the thin barrier layer 70 has a barrier height of 1.36 eV from the floating conductive layer 14 side.
An i-AlAs barrier layer 70a having a thickness of about 2.36 nm, an i-InGaAs well layer 70b having a thickness of about 3.3 nm, and an i-AlAs barrier layer 70c having a barrier height of about 1.36 eV and having a thickness of about 2.36 nm are stacked. It has a structure.

The contact layer 52 is formed on the thin barrier layer 70.
Is formed, and the first electrode 22 and the second electrode 22 are formed on the contact layer 52.
An electrode 24 is formed. Next, a storage method of the semiconductor memory device according to the present embodiment will be described with reference to FIG. FIG. 11 is a graph showing current-voltage characteristics at 77 K of the intermediate barrier layer 46 and the thin barrier layer 70 of this embodiment.

First, a method of writing information will be described. When a bias voltage of about 1.6 V is applied between the first electrode 22 and the second electrode 24, a voltage of about 0.8 V is initially applied to both the thin barrier layer 70 and the intermediate barrier layer 46.
As shown in FIG. 11, approximately 5 ×
As much as 10 ⁴ A / cm ² flows, electrons are injected into the channel layer 48. The electrons injected into the channel layer 48 are
Since the energy is as high as 0.7 eV, the energy reaches the floating conductive layer 14 beyond the intermediate barrier layer 46. On the other hand, as shown in FIG. 11, even when a voltage of about 0.8 V is applied, only about 1 × 10 ⁻³ A / cm ² flows through the intermediate barrier layer 46. Therefore, the floating conductive layer 14 stores electrons,
The stored information "1" is written.

When the storage information “1” is written and electrons are accumulated in the floating conductive layer 14, the potential rises and the channel layer 4
The depletion layer extends to 8. In this state, the first electrode 22 and the second
When the bias voltage between the electrodes 24 is 0 V, the channel layer 48 is depleted by the potential of the floating conductive layer 14. Next, a method for reading information will be described.

When no charge is stored in the floating electrode layer 14, the channel layer 48 is not depleted.
When a read bias voltage of about 0.7 V lower than the write bias voltage is applied between the first electrode 22 and the second electrode 24, the channel layer 48 passes through the thin barrier layer 70 to 10 ⁴
A current of about A / cm ² flows. On the other hand, in the state where charges are accumulated in the floating electrode layer 14, a depletion layer extends from the floating electrode layer 14 and the channel layer 48 is almost depleted, and almost no current flows between the first electrode 22 and the second electrode 24. It stops flowing.

As described above, by applying the read bias voltage and detecting the presence or absence of the current flowing between the first electrode 22 and the second electrode 24, the storage based on whether or not the charge has been accumulated in the floating electrode layer 14 is stored. Information can be read. When a bias voltage of about 0.7 V is applied between the first electrode 22 and the second electrode, electrons are injected into the channel layer 48 through the thin barrier layer 70, but the injection energy of the electrons is about 0.35 eV. And the lower intermediate barrier layer 46
, And the electrons are not injected into the floating conductive layer 14, so that the accumulated state of electrons is maintained.

In this state, even when a bias voltage of about 1.6 V, which is the same as the write bias voltage, is applied between the first electrode 22 and the second electrode 24, no voltage is applied to the thin barrier layer 70 and electrons are not applied. Is not injected. At this time, a voltage of about 0.7 V is applied to the intermediate barrier layer 46. However, as shown in FIG. 11, since the current density is as small as about 10 ⁻⁶ A / cm ² , the accumulated electrons are released. Takes a long time, and the stored information can be held for about one second. If the bias voltage is set to a short pulse of about 1 second or less, the information can be maintained.

Next, a method of erasing information will be described.
When a high erase bias voltage of about 4V is applied between the first electrode 22 and the second electrode 24, a voltage of about 2V is applied to the intermediate barrier layer 4.
6 is applied. The current density through the intermediate barrier layer 46 is
As shown in FIG. 11, it becomes about 10 ⁴ A / cm ² ,
The electrons accumulated in the floating conductive layer 14 are rapidly released in about 0 ps, the stored information “1” is erased, and the stored information “0” is written.

Even if a high erase bias voltage of about 4 V is continuously applied between the first electrode 22 and the second electrode 24 in a state where electrons are emitted from the floating conductive layer 14, the channel layer 48 is not depleted. Therefore, most of the voltage (about 2.5
V) is a thin barrier layer 7 having a resonant tunneling barrier
0 is applied. However, the thin barrier layer 70
As shown in FIG. 11, the valley state is at 2.5 V,
Since the current density is as low as about 10 ² A / cm ² , the injected electrons do not reach the floating conductive layer 14. The injected electrons are almost scattered to the L valley and flow through the channel layer 48, so that the floating conductive layer 14 hardly accumulates electrons. Therefore, even when an erase bias voltage higher than the write bias voltage is applied, the stored information “1” in which electrons are stored is not written.

Next, a semiconductor according to a ninth embodiment of the present invention will be described.
The storage device will be described with reference to FIG. In this embodiment,
Semiconductor memory device is selectively formed in a region
You. In the present embodiment, the semiconductor memory device according to the fifth embodiment is
The case of forming is described as an example. Semi-insulating InP substrate
10, a non-doped i-In_0.52Al_0.48As
A thick barrier layer 12 having a thickness of about 300 nm
I have. On this thick barrier layer 12, about 200 nm
Thick In_0.53Ga_0.47An As layer 72 is formed. This
In_0.53Ga_0.47The As layer 72 includes a semiconductor storage device.
Silicon is doped only in the central region where
5 × 10¹⁷cm^-3N-In_0.53Ga _0.47As
A floating conductive layer 72a made of
Is undoped n-In_0.53Ga_0.47From As
An element isolation layer 72b is formed.

On the floating conductive layer 72a, a thin barrier layer 30 having a resonant tunneling barrier (RTB) having an asymmetric resonance level is formed. The thin barrier layer 30 has a barrier height of 0.53 e from the floating conductive layer 72 side.
V of i-AlAs barrier layer 30a, i-InGaAs well layer 30b, the barrier height 0.785eV i-In _{0. 35}
Al _0.65 As barrier layer 30c, i-InGaAs well layer 30d, i-In _0.52 Al having a barrier height of 0.53 eV
_{A 0.48} As barrier layer 30e is laminated. In the present embodiment, the uppermost i-In _0.52 Al _0.48 As barrier layer 30e, which is a part of the surface side of the thin barrier layer 30, is doped with silicon to a doping amount of 1 × 10 ¹⁸ cm ⁻³ .

On the thin barrier layer 30, the channel layer 1
8. The contact layer 20 is sequentially stacked, and the first electrode 22 and the second electrode 24 are formed on the contact layer 20. Electrons seep from the barrier layer 30e into the channel layer 18, and a two-dimensional electron channel 28 is formed in the channel layer 18. Thus, the semiconductor memory device of the present embodiment is formed in a desired region on the semi-insulating InP substrate 10.

Note that non-doped In _0.53 Ga _0.47 As
In place of the layer 72, a p-doped amount of about 5 × 10 ¹⁷ cm ^-3
-In _0.53 Ga _0.47 As layer or p-In _0.0.52 Ga _0.48
An As layer may be used. A semiconductor memory device with small leakage current and long holding time can be realized. next,
A method for manufacturing the semiconductor memory device according to the present embodiment will be described.

First, electron beam epitaxy (MB
The thick barrier layer 12 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 300 nm, and the non-doped I layer having a thickness of about 200 nm are formed on the semi-insulating InP substrate 10 by the method E).
The n _0.53 Ga _0.47 As layer 72 is deposited. Next, In _0.53
A resist layer (not shown) is applied on the Ga _0.47 As layer 72, and the resist layer is patterned so that a region for forming a semiconductor memory device is opened. Subsequently, using the patterned resist layer as a mask, In _0.53 Ga _0.47
The As layer 72 is doped with silicon as an impurity at a dose of 5 × 1.
Ion implantation is performed selectively at 0 ¹² cm ^-2 and implantation energy of about 100 KeV. Then, the flash lamp annealing method, activation was approximately 5 seconds annealed In _0.53 Ga _0.47 As layer 72 at 900 ℃, In _0.53 Ga _0.47 As
The layer 72 is selectively doped with 5 × 10 ¹⁷ cm ^-3 n-I
A floating conductive layer 72a made of n _0.53 Ga _0.47 As is formed.

It should be noted that the non-doped In 200
Instead of the _0.53 Ga _0.47 As layer 72, the doping amount is 5 × 10
A p-In _0.53 Ga _0.47 As layer of about ¹⁷ cm ^-3 or p-I
n _0. to accumulate the _0.52 Ga _0.48 As layer, by ion-implanting silicon in the layer, it may be formed a floating conductive layer is an n-type semiconductor layer on the p-type semiconductor layer. Next, on the entire surface of the In _0.53 Ga _0.47 As layer 72, a thin barrier layer 16 of about 20 nm thick made of non-doped i-In _0.52 (AlxGa1-x) _0.48 As, and a silicon doping amount of 5 × 10 ¹⁷ cm ^{− 3} , a channel layer 18 of about 30 nm thickness made of n-In _0.53 Ga _0.47 As, and an n-In thickness of about 70 nm obtained by changing the doping amount of silicon from 5 × 10 ¹⁷ cm ⁻³ to 5 × 10 ¹⁹ cm ^−3. _The contact layer 20 made of _0.53 Ga _0.47 As is continuously crystal-grown.

Next, a tungsten silicide (WSi) layer having a thickness of, for example, about 200 nm is formed on the contact layer 20. Subsequently, the first electrode 22 and the second electrode 24 are subjected to pattern etching by a usual photolithography technique.
To form Next, using the first electrode 22 and the second electrode 24 as a mask, the first electrode 22 and the second electrode 22 are etched by RIE using CH ₄ and H ₂ under an etching condition of a gas pressure of 4 Pascal (Pa) and an RF power of 60 W. Contact layer 2 between electrodes
0 is removed by etching and the first electrode 22 and the second electrode 24 are removed by etching until they reach the In _0.53 Ga _0.47 As layer 72 to complete the semiconductor memory device of this embodiment.

Next, a semiconductor memory device according to a tenth embodiment of the present invention will be described with reference to FIGS. On the semi-insulating InP substrate 10, a non-doped i-In _0.52
Thick barrier layer 1 of about 300 nm thick made of Al _0.48 As
2 are formed. On the thick barrier layer 12, n-In having a doping amount of silicon (Si) of 1 × 10 ¹⁸ cm ⁻³ is formed.
A floating conductive layer 14 of about 200 nm thick made of _0.53 Ga _0.47 As is formed.

On the floating electrode layer 14, a non-doped i-
In _0.52 (AlxGa1-x) _0.48 As
A thin barrier layer 80 having a thickness of nm is formed. I-In _0.52 (AlxGa1-x) _0.48 As of thin barrier layer 80
The aluminum composition ratio (x value) linearly changes from x = 0.5 to 1.0 from the semi-insulating InP substrate 10 side to the surface side. The thin barrier layer 80 is shown in FIG.
As shown in (b), the barrier height on the floating electrode layer 14 side is as low as 0.27 eV, the barrier height is gradually increased, and the barrier height on the upper surface is 0.53 eV.

On the thin barrier layer 80, a non-doped i
A channel layer 18 of about 30 nm thick made of -In _0.53 Ga _0.47 As is formed. On the channel layer 18, the doping amount of silicon is set to 1 × 10 ¹⁸ cm ⁻³ to 5 × 10 ¹⁹ c
n-In _0.53 Ga of about 20 nm thickness changed to m ^-3
_0.47 As layer 20a and silicon doping amount of 5 × 10 ¹⁹
n-In _0.53 Ga _0.47 As layer 2 with a thickness of about 50 nm of cm ^-3
0b is formed. The contact layer 20 is provided with a protrusion for forming two electrodes.

The two convex portions of the contact layer 20 have approximately 2
A first electrode 22 and a second electrode 24 made of a tungsten silicide (WSi) layer having a thickness of 00 nm are formed. Instead of the tungsten silicide layer, the first electrode 22 and the second electrode 24 are formed of a chromium layer having a thickness of about 20 nm and a chromium layer having a thickness of about 190 nm.
A Cr / Au layer in which a thick gold layer is stacked, or a Pd / Ge layer in which a palladium layer having a thickness of about 60 nm and a germanium layer having a thickness of about 80 nm may be used.

Next, the storage method of the semiconductor memory device according to the present embodiment will be explained with reference to FIG. FIG. 14 is a graph showing the current-voltage characteristics of the thin barrier layer of this example in the forward and reverse directions. First, a method for writing information will be described. When writing information to this semiconductor storage device,
One of the first electrode 22 and the second electrode 24, for example, the first electrode 22 is grounded, and a write bias voltage for making the second electrode 24 positive is applied. When such a write bias voltage is applied, electrons accumulated in the floating electrode layer 14 tunnel through the thin barrier layer 80 and flow to the channel layer 18, are extracted from the second electrode 24, and are thinned from the first electrode 22. Electrons are injected into the floating electrode layer 14 by tunneling through the layer 80.

As shown in FIG. 14B, the barrier height of the thin barrier layer 80 is inclined from 0.27 eV to 0.53 eV from the floating electrode layer 14 side to the channel layer 18 side. For this reason, the floating electrode layer 1
4 is a forward barrier to electrons flowing in FIG.
As shown in (c), a band structure in which electrons do not easily tunnel is obtained. On the other hand, from the floating electrode layer 14 to the second electrode 2
The barrier in the reverse direction for the electrons flowing in FIG.
As shown in (d), a band structure in which electrons easily tunnel is obtained.

FIG. 14A shows the current value flowing in the forward and reverse directions with respect to the bias voltage applied to the thin bias layer 80 having the inclined band structure at 77K.
Up to a bias voltage of about 0.5 V, there is almost no difference between the current values in the forward and reverse directions, and the value is very small, about 0.5 A / cm ² . However, at about 0.9 V, the forward and reverse current values are 10 ² A / cm in the forward direction.
^{2. In} the reverse direction, it is 10 ⁵ A / cm ² , and the difference in current value is about 1000 times.

For this reason, when the first electrode 22 is grounded and a voltage of about 1.8 V is applied to the second electrode 24, at the time of application, a bias voltage (approximately equal to the forward and reverse thin barrier layers 80) is applied. 0.9 V) is applied, so about 1 ps
Electrons corresponding to a charge amount of about 10 ^-6 C / cm ² are extracted from the floating electrode layer 14 within a very short time.

As a result, the potential of the floating electrode layer 14 becomes about 0.5.
A voltage that drops by about 2 V and makes the forward current value and the reverse current value almost equal (in this case, about 1.2 V for the forward thin barrier layer 80 and 0.7 V for the reverse thin barrier layer 80). ), And electrons are extracted from the floating electrode 14. When electrons are extracted from the floating electrode 14, a two-dimensional electron channel 28 is formed in the channel layer 18, so that a current flows between the first electrode 22 and the second electrode 24, so that information can be written. .

At this time, when the voltage of the second electrode 24 is set to 0 V, the potential of the floating electrode layer 14 is lowered by about 0.2 V. However, even if the floating electrode layer 14 is lowered by about 0.2 V, as shown in FIG. 14A, the forward current value and the reverse current value are only about 10 ⁻⁵ A / cm ² ,
Electrons are slowly injected into the floating electrode layer 14, and this state is maintained for about 10 ms. Further, the floating electrode layer 14
Is injected, the potential of the floating electrode layer 14 increases, and electrons are injected more slowly. For example, when the potential of the floating electrode layer 14 is lower by about 0.1 V, the state is maintained for about 1 s.

Next, a method of reading information will be described. A current flowing from the first electrode 22 to the second electrode 24 through the channel layer 18 applies a voltage of about 0.5 V between the first electrode 22 and the second electrode 24 when no electrons are extracted from the floating electrode layer 14. Even if added, almost no current flows. On the other hand, when electrons are extracted from the floating electrode layer 14, the two-dimensional electron channel 2
Since 8 is formed, a large current flows between the first electrode 22 and the second electrode 24.

As described above, by applying the read bias voltage and detecting the presence / absence of the current flowing between the first electrode 22 and the second electrode 24, it is possible to determine whether or not electrons have been extracted from the floating electrode layer 14. Information can be read.
When a read bias voltage of about 0.5 V is applied between the first electrode 22 and the second electrode 24, the thin barrier layer 8
Since the current flowing through 0 is only about 10 ⁻⁴ A / cm ^2, it does not affect reading of stored information.

In this embodiment, the electrons accumulated in the floating electrode layer 14 are released in about one second, and the stored information is lost. However, by increasing the thickness of the thin barrier layer 80 from about 20 nm to about 30 nm. , For about 24 hours. Next, a method of erasing information will be described. When an erase voltage of about 1.0 V is applied between the first electrode 22 and the second electrode 24 in a state where electrons are extracted from the floating electrode layer 14 and the two-dimensional electron channel 28 is formed in the channel layer 18, two-dimensional electron channels 28 are formed. The electrons in the electron channel 28 become hot electrons and are injected into the floating electrode layer 14 beyond the thin barrier layer 80. In this case, since the barrier height of the thin barrier layer 80 decreases from the surface side toward the substrate side, the hot electrons easily return to the floating electrode layer 14. The first electrode 22 and the second electrode 2 for a predetermined time or more.
When a voltage of about 1.0 V is continuously applied between the four, the two-dimensional electron channel 28 of the channel layer 18 disappears, and information written in the floating electrode layer 14 is erased.

Further, by irradiating ultraviolet rays, electrons can be injected into the floating electrode layer 14 to collectively erase information. It should be noted that the semiconductor memory device of this embodiment is thermoelectric (t
It is desirable to operate at a low temperature of 77K or less in order to suppress a current component which is not hermonic. As described above, according to this embodiment, a read-only memory (EPROM) that can be electrically written at high speed can be realized. Since only two wirings need to be provided, high integration is possible and the writing time can be shortened.

Next, the fabrication of the semiconductor memory device according to the present embodiment will be described.
The fabrication method will be described. First, electron beam epitaxy
On the semi-insulating InP substrate 10 by the Char (MBE) method
In addition, non-doped i-In_0.52Al_0.48About As
300 nm thick barrier layer (buffer layer) 12
The doping amount of the con (Si) is 1 × 10¹⁸cm ^-3N-In
_0.53Ga_0.47About 200 nm thick floating conductive layer made of As
14. Non-doped i-In_0.52(AlxGa1-x)
_0.48A thin barrier layer 80 of about 20 nm thick made of As;
Doped i-In_0.53Ga_0.47About 30n made of As
channel layer 18 having a thickness of m and a silicon doping amount of 1 × 10
¹⁸cm^-3From 5 × 10¹⁹cm ^-3Changed to about 20n
m-thick n-In_0.53Ga_0.47As layer 20a, silicon
Dope amount is 5 × 10¹⁹cm^-3About 50 nm thick n-In
_0.53Ga_0.47The As layer 20b is continuously grown.

Next, on the contact layer 20, about 200 n
m thick tungsten silicide (WSi) layer, about 20 n
C having a chrome layer of about m thickness and a gold layer of about 190 nm thickness
r / Au layer or about 60 nm thick palladium layer and about 8
A Pd / Ge layer in which a germanium layer having a thickness of 0 nm is laminated is formed. Subsequently, the first electrode 22 and the second electrode 24 are formed by pattern etching using a normal photolithography technique.

Next, using the first electrode 22 and the second electrode 24 as a mask, the first electrode 22 and the second electrode 22 are etched by RIE using CH ₄ and H ₂ under the etching conditions of a gas pressure of 4 Pa and an RF power of 60 W. the n-in _0.53 Ga _0.47 as layer 20b and the n-in _0.53 Ga _{0. 47} as layer 20a between with etched away, to the first electrode 22 reaches the thick barrier layer 12 so as to surround the second electrode 24 etch By removing, the semiconductor memory device of this embodiment is completed.

Next, a semiconductor memory device according to an eleventh embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the tenth embodiment shown in FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted or simplified. On the semi-insulating InP substrate 10, a non-doped i-In _0.52 Al
A thick barrier layer 12 of about 300 nm thick made of _0.48 As is formed. On this thick barrier layer 12, FIG.
In a state where the element is isolated on the left side region, as in the tenth embodiment, the n-type silicon is doped with 5 × 10 ¹⁷ cm ⁻³ .
A floating conductive layer 14 made of In _0.53 Ga _0.47 As and having a thickness of about 200 nm, a non-doped i-In _0.52 (AlxGa1-
x) A thin barrier layer 80 of about 20 nm thick consisting of _0.48 As
Are formed.

In the thin barrier layer 80, as in the tenth embodiment, the composition ratio (x value) of i-In _0.52 (AlxGa1-x) _0.48 As aluminum is changed from the semi-insulating InP substrate 10 side to the surface side. , And changes linearly from x = 0.5 to 1.0. In the thin barrier layer 80, the barrier height on the floating electrode layer 14 side is as low as 0.27 eV, the barrier height is gradually increased, and the barrier height on the upper surface is 0.53 eV.
It has become.

On the thin barrier layer 80, a non-doped i
A channel layer 18 of about 30 nm thick made of -In _0.53 Ga _0.47 As is formed. On the channel layer 18, the doping amount of silicon is set to 1 × 10 ¹⁸ cm ⁻³ to 5 × 10 ¹⁹ c
n-In _0.53 Ga of about 20 nm thickness changed to m ^-3
_0.47 As layer 20a and silicon doping amount of 5 × 10 ¹⁹
n-In _0.53 Ga _0.47 As layer 2 with a thickness of about 50 nm of cm ^-3
0b is formed. The contact layer 20 is provided with a protrusion for forming two electrodes.

The two convex portions of the contact layer 20 have a thickness of about 2
A first electrode 22 and a second electrode 24 made of a tungsten silicide (WSi) layer having a thickness of 00 nm are formed. Thus, a semiconductor memory device similar to that of the tenth embodiment is formed in the left region on the semi-insulating InP substrate 10. On the other hand, a HEMT having a layer structure similar to that of the semiconductor memory device is also formed in the right region on the semi-insulating InP substrate 10. In other words, on the thick barrier layer 12, in a state where the element is separated by the element separation layer 81, the n-In thickness of about 200 nm with the silicon doping amount of 5 × 10 ¹⁷ cm ^−3.
_0.53 Ga _0.47 As layer 82, electron supply layer 84, active layer 8
6. The contact layers 20 are sequentially stacked.

The electron supply layer 84 is a non-doped i-I layer having a thickness of about 20 nm, which is the same as the thin barrier layer 80 of the semiconductor memory device.
n _0.52 (AlxGa1-x) _0.48 As. The active layer 86 consists of the same about 30nm thick undoped channel layer _{18 i-In 0. 53 Ga 0.47} As. Electrons seep from the electron supply layer 34 into the active layer 36 and form a two-dimensional electron channel 88 in the active layer 86.

A source electrode 90 and a drain electrode 92 are formed on the contact layer 20, and an n-In _0.53 Ga _0.47 As layer 20 between the source electrode 90 and the drain electrode 92 is formed.
A gate electrode 94 made of aluminum (Al) or platinum (Pt) is formed on a. According to the present embodiment, since information is read depending on whether or not a current flows through the two-dimensional electron channel in the channel layer, information can be read at a very high speed. Further, the HEMT can be formed on the same semi-insulating InP substrate as the semiconductor memory device, and the amplification of storage information and the peripheral circuit for a memory element can be easily formed. Next, the first of the present invention
A semiconductor memory device according to a second embodiment will be described with reference to FIGS. In the present embodiment, the above-described first to eleventh
The memory is constructed by arranging a large number of memory cells according to the embodiment in a matrix.

Each memory cell MC is provided with a first electrode E1 and a second electrode E2. Word line WL
Are made of Ti / Pt / Au or the like, and connect the first electrodes E1 of the memory cells MC adjacent in the horizontal direction. The bit line BL orthogonal to the word line WL is made of Ti / Pt / Au or the like, and the second electrode E of the memory cell MC adjacent in the vertical direction.
Connect two comrades.

A tri-state buffer TB is connected to each of the word lines WL, and a tri-state buffer TB is connected to each of the bit lines BL. The tri-state buffer TB is a circuit that performs a logical operation as shown in the truth table of FIG. When the control signal OE is at a high level, a low-level signal is output for a high-level input signal, and a high-level signal is output for a low-level input signal. When the control signal OE becomes low level, the output signal becomes high impedance regardless of whether the input signal is high level or low level, and is in a state of being disconnected from the word line WL and the bit line BL.

FIGS. 17B and 17C show specific circuit examples of the tristate buffer. FIG. 17 (b)
FIG. 17C shows a circuit of a CMOS tri-state buffer, and FIG. 17C shows a circuit of an E / D tri-state buffer. When writing to a specific memory cell MC in the memory cell array, the word line WL connected to the first electrode E1 of the memory cell MC is set to low level (0 V) by the tri-state buffer TB, and then the memory is turned on. The bit line BL connected to the second electrode E2 of the cell MC is set to a high level (2 V). In this way, information is written to the specific memory cell MC. Other word lines WL and bit lines BL are connected to a tri-state buffer T
Since the impedance is made high by B, no information is written even if one of the electrodes goes high or low.

Specific memory cell M in memory cell array
When reading information stored in C. The tristate buffer TB allows the second electrode E of the memory cell MC to be set.
After the bit line BL connected to the memory cell MC is set to low level (0 V), the word line WL connected to the first electrode E1 of the memory cell MC is set to high level (1 V). In this manner, information is selectively read from the specific memory cell MC. Other word lines WL, bit lines BL
Are made high impedance by the tri-state buffer TB.

As in the first, second, third, sixth, seventh, and ninth embodiments, a memory cell MC using a barrier layer having an asymmetric barrier with a high barrier height on the floating conductive layer side is used. As described above, as described above, the low level of the word line WL is set to 0 V, the high level is set to 1 V, the low level of the bit line BL is set to 0 V, and the high level is set to 2 V.
Writing, reading, and erasing of "1" were performed selectively. In other embodiments, the levels of the word line WL and the bit line BL are determined according to the memory cell MC.

For example, as in the fourth, fifth, and eighth embodiments, a memory cell M using a resonant tunneling barrier layer
In C, if the low level of the word line WL is 0 V and the high level is 1 V, and the low level of the bit line BL is 0.5 V and the high level is 2 V, writing of information "0" and "1"
Reading and erasing can be selectively performed. Also, the first
As in the zeroth and eleventh embodiments, a write bias voltage of about 1.8 V and a write bias voltage of about 0 V are applied to a memory cell MC using a barrier layer having an asymmetric barrier with a high barrier height on the floating conductive layer side. Word line W so that a read bias voltage of 0.5 V and an erase bias voltage of about 1.0
The low level and the high level of L and the bit line BL may be determined.

According to the present embodiment, it is only necessary to provide two wirings for one memory cell, so that stored information can be written or read at high speed. In the case of a conventional semiconductor memory device, for example, a 1-MOS cell type DRAM using a silicon MOSFET and a capacitor, the cell area is about 2 μm ^{2 according to the} 0.6 μm rule. The area can be reduced to about 1 μm ² .

Further, in this embodiment, since a capacitor requiring a large occupied area is not required, the manufacturing process is very simplified. Further, when further miniaturization is required, the noise margin due to the capacitance of the capacitor has become a problem in the DRAM using silicon, whereas the semiconductor memory device of the present embodiment has an essential There is no particular problem, and further miniaturization is possible.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, InGaAs / I
Although an n (AlGa) As-based compound semiconductor material was used,
GaAs / AlGaAs system, InGaAs / InP system,
A compound semiconductor material such as InAs / AlGaAsSb, a semiconductor material such as Si and SiGe, a Si and SiO ₂ , a combination of a metal and an insulator such as CaF and CoSi,
Superconducting materials such as Nb and NbO, and MgO and SrTiO ₃
Other materials such as oxide superconductors may be used.

[0129]

As described above, according to the present invention, a thick non-doped barrier layer, a floating conductive layer doped with impurities, and an asymmetric barrier having a high barrier height on the floating conductive layer side are provided on a semiconductor substrate. A thin barrier layer having the following structure and a channel layer are stacked, and the first electrode and the second electrode are provided on the channel layer. Therefore, a write bias voltage having a higher potential in the second electrode than in the first electrode is applied. By utilizing the fact that the amount of electrons injected from the first electrode to the floating electrode layer via the thin barrier layer is larger than the amount of electrons emitted from the floating electrode layer to the second electrode via the thin barrier layer. Information is written by injecting electrons into the floating electrode layer, and whether a current flows through the channel layer when a read bias voltage lower than the write bias voltage is applied between the first electrode and the second electrode. Read the stored information It can be in Suyo.

Further, according to the present invention, on a semiconductor substrate,
A non-doped thick barrier layer, a floating conductive layer doped with impurities, a thin barrier layer having an asymmetric resonance tunneling barrier having a high resonance level on the floating conductive layer side, and a channel layer are stacked. Since the first electrode and the second electrode are provided, by applying a write bias voltage having a higher potential on the second electrode than on the first electrode, the first electrode is injected into the floating electrode layer via a thin barrier layer. Utilizing that the amount of electrons to be emitted is larger than the amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer, electrons are injected into the floating electrode layer to write information, and the first electrode is written. When a read bias voltage lower than the write bias voltage is applied between the memory cell and the second electrode, the stored information is read based on whether a current flows in the channel layer, and an erase via higher than the write bias voltage is read. By applying a voltage to the first and second electrodes, the amount of electrons emitted from the floating electrode layer to the second electrode via the thin barrier layer is reduced from the first electrode to the floating electrode layer via the thin barrier layer. Utilizing the fact that the amount is larger than the amount of injected electrons, the information can be erased by discharging the electrons accumulated in the floating electrode layer.

Further, according to the present invention, on a semiconductor substrate,
A thick non-doped barrier layer, a floating conductive layer doped with impurities, an intermediate barrier layer having an asymmetric barrier with a low barrier height on the floating conductive layer side, a channel layer, and a symmetric barrier where the barrier height does not change And the first electrode and the second electrode are provided on the thin barrier layer. By applying a write bias voltage having a higher potential on the second electrode than on the first electrode, The amount of electrons injected from the first electrode into the floating electrode layer through the thin barrier layer and the intermediate barrier layer is smaller than the amount of electrons emitted from the floating electrode layer to the second electrode through the intermediate barrier layer and the thin barrier layer. Utilizing the fact that electrons are injected into the floating electrode layer from the first electrode through the thin barrier layer and the intermediate barrier layer to write information in the floating electrode layer, and a write bias voltage is applied between the first electrode and the second electrode. Also low By reading stored information based on whether a current flows through the channel layer when a read bias voltage is applied and applying an erase bias voltage higher than the write bias voltage to the first electrode and the second electrode, The amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer and the intermediate barrier layer is smaller than the amount of electrons injected from the first electrode to the floating electrode layer through the thin barrier layer and the intermediate barrier layer. Utilizing this fact, electrons accumulated in the floating electrode layer can be emitted from the second electrode through the thin barrier layer and the intermediate barrier layer to erase information in the floating electrode layer.

Further, according to the present invention, on a semiconductor substrate,
A non-doped thick barrier layer, a floating conductive layer doped with impurities, an intermediate barrier layer having a symmetric barrier whose barrier height does not change, a channel layer, and a thin barrier layer having a resonant tunneling barrier are stacked, Since the first electrode and the second electrode are provided on the thin barrier layer, by applying a write bias voltage having a higher potential on the second electrode than on the first electrode, the thin barrier layer and the intermediate barrier are removed from the first electrode. The amount of electrons injected into the floating electrode layer through the layer is changed from the floating electrode layer to the second through the intermediate barrier layer and the thin barrier layer.
Utilizing the fact that it is larger than the amount of electrons emitted to the electrode, electrons are injected into the floating electrode layer from the first electrode through the thin barrier layer and the intermediate barrier layer, and information is written into the floating electrode layer. When a read bias voltage lower than the write bias voltage is applied between the two electrodes, the stored information is read based on whether a current flows in the channel layer, and the erase bias voltage higher than the write bias voltage is set to the first. When applied to the electrode and the second electrode, the amount of electrons emitted from the floating electrode layer to the second electrode through the thin barrier layer and the intermediate barrier layer is increased from the first electrode to the thin barrier layer and the intermediate barrier layer. Utilizing the fact that the amount of electrons injected into the floating electrode layer is larger than the amount of electrons injected into the floating electrode layer, the electrons stored in the floating electrode layer are released from the second electrode through the thin barrier layer and the intermediate barrier layer, and information on the floating electrode layer is obtained. It is possible to be removed by.

Further, according to the present invention, on a semiconductor substrate,
A non-doped thick barrier layer, a floating conductive layer doped with impurities, a thin barrier layer having an asymmetric barrier with a low barrier height on the floating conductive layer side, and a channel layer are stacked, and a first layer is formed on the channel layer. Since the electrode and the second electrode are provided, by applying a write bias voltage having a higher potential on the second electrode than on the first electrode, the second electrode is discharged from the floating electrode layer to the second electrode via the thin barrier layer. Utilizing that the amount of electrons is larger than the amount of electrons injected from the first electrode into the floating electrode layer through the thin barrier layer, electrons are emitted from the floating electrode layer to write information, and the first electrode and the first electrode are written. When a read bias voltage lower than the write bias voltage is applied between the two electrodes, the stored information is read based on whether or not a current flows in the channel layer, and a write bias is applied between the first electrode and the second electrode. Read below voltage By applying an erase bias voltage higher than the bias voltage, electrons can be injected from the electron storage layer in the channel layer through the thin barrier layer into the floating electrode layer to erase information in the floating electrode layer. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a graph showing current-voltage characteristics of a thin barrier layer of a semiconductor memory device according to a first embodiment of the present invention in forward and reverse directions.

FIG. 3 is a diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 5 is a diagram showing a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 6 is a graph showing forward and reverse current-voltage characteristics of a thin barrier layer of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 8 is a diagram showing a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 9 is a diagram showing a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 10 is a diagram showing a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 11 is a graph showing current-voltage characteristics of an intermediate barrier layer and a thin barrier layer of a semiconductor memory device according to an eighth embodiment of the present invention.

FIG. 12 is a diagram showing a semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 13 is a diagram showing a semiconductor memory device according to a tenth embodiment of the present invention.

FIG. 14 is a graph showing current and voltage characteristics of a thin barrier layer of a semiconductor memory device according to a tenth embodiment of the present invention in the forward and reverse directions.

FIG. 15 is a diagram showing a semiconductor memory device according to an eleventh embodiment of the present invention.

FIG. 16 is a diagram showing a semiconductor memory device according to a twelfth embodiment of the present invention.

FIG. 17 is a diagram showing a tri-state buffer used in a semiconductor memory device according to a twelfth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 semi-insulating InP substrate 12 thick barrier layer 14 floating conductive layer 16 thin barrier layer 18 channel layer 20 contact layer 20a n-In _0.53 Ga _0.47 As layer 20b n-In _0.53 Ga _0.47 As layer Reference Signs List 22 first electrode 24 second electrode 26 protective layer 28 two-dimensional electron channel 30 thin barrier layer 30a i-AlAs barrier layer 30b i-InGaAs well layer 30c i-In _0.35 Al _0.65 As barrier layer 30d ... i-InGaAs well layer 30e ... i-In _0.52 Al _0.48 As barrier layer 32 ... n-In _0.53 Ga _0.47 As layer 34 ... electron supply layer 36 ... active layer 38 ... two-dimensional electron channel 40 ... source electrode 42 ... drain Electrode 44 Gate electrode 46 Intermediate barrier layer 48 Channel layer 50 Thin barrier layer 52 Contact layer 52a nI _0.53 Ga _0.47 As layer _{52b ... n-In 0.53 Ga 0.47} As layer 54 ... collector layer 56 ... barrier layer 58 ... base lead layer 60 ... base layer 62 ... emitter layer 64 ... collector electrode 66 ... base electrode 68 ... emitter electrode 70 ... Thin barrier layer 70a i-AlAs barrier layer 70b i-InGaAs well layer 70c i-AlAs barrier layer 72 _{In0.53 Ga0.47} As layer 72a floating conductive layer 72b element isolation layer 80 thin barrier layer 81 element Separation layer 82 n-In _0.53 Ga _0.47 As layer 84 electron supply layer 86 active layer 88 two-dimensional electron channel 90 source electrode 92 drain electrode 94 gate electrode MC memory cell E1 first electrode E2 Second electrode WL: word line BL: bit line TB: tristate buffer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (11)

(57) [Claims] A semiconductor substrate; a non-doped thick barrier layer formed on the semiconductor substrate; a floating conductive layer formed on the thick barrier layer and doped with impurities; and formed on the floating conductive layer. A thin barrier layer having an asymmetric barrier having a high barrier height on the floating conductive layer side; a channel layer formed on the thin barrier layer; a first electrode and a second electrode formed on the channel layer A semiconductor memory device comprising: an electrode; 2. A semiconductor substrate, a non-doped thick barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities, and formed on the floating conductive layer. A thin barrier layer having an asymmetric resonance tunneling barrier having a high resonance level on the floating conductive layer side; a channel layer formed on the thin barrier layer; a first electrode formed on the channel layer; A semiconductor memory device comprising: a second electrode. 3. A semiconductor substrate; a non-doped thick barrier layer formed on the semiconductor substrate; a floating conductive layer formed on the thick barrier layer and doped with impurities; and formed on the floating conductive layer. An intermediate barrier layer having an asymmetric barrier having a low barrier height on the floating conductive layer side; a channel layer formed on the intermediate barrier layer; and a barrier layer formed on the channel layer and having a constant barrier height. A semiconductor memory device comprising: a thin barrier layer having a symmetric barrier; and a first electrode and a second electrode formed on the thin barrier layer. 4. A semiconductor substrate; a non-doped thick barrier layer formed on the semiconductor substrate; a floating conductive layer formed on the thick barrier layer and doped with impurities; and formed on the floating conductive layer. An intermediate barrier layer having a symmetric barrier whose barrier height does not change; a channel layer formed on the intermediate barrier layer; a thin barrier layer formed on the channel layer and having a resonant tunneling barrier; A semiconductor memory device comprising a first electrode and a second electrode formed on a thin barrier layer. 5. A semiconductor substrate, a non-doped thick barrier layer formed on the semiconductor substrate, a floating conductive layer formed on the thick barrier layer and doped with impurities, and formed on the floating conductive layer. A thin barrier layer having an asymmetric barrier with a low barrier height on the floating conductive layer side; a channel layer formed on the thin barrier layer; a first electrode and a second electrode formed on the channel layer A semiconductor memory device comprising: an electrode; 6. The semiconductor memory device according to claim 1, wherein said thin barrier layer is a non-doped semiconductor layer, and said channel layer is a semiconductor layer doped with impurities. A semiconductor memory device characterized by the following. 7. The semiconductor memory device according to claim 1, wherein the thin barrier layer is doped with an impurity at least in a portion on the channel layer side, and the channel layer is a non-doped semiconductor layer. And a two-dimensional electron channel is formed in the channel layer by electrons supplied from the thin barrier layer. 8. The information storage method for a semiconductor memory device according to claim 1, wherein said second electrode has a higher potential than said first electrode by applying a write bias voltage having a higher potential than said first electrode. Writing information into the floating electrode layer by injecting electrons from the first electrode into the floating electrode layer via the thin barrier layer, and applying a voltage between the first electrode and the second electrode that is lower than the write bias voltage. An information storage method for a semiconductor memory device, comprising: applying a low read bias voltage; and reading information stored in the floating electrode layer based on whether a current flows in the channel layer. 9. The information storage method for a semiconductor memory device according to claim 2, wherein said second electrode has a higher potential than said first electrode by applying a write bias voltage having a higher potential than said first electrode. Writing information into the floating electrode layer by injecting electrons from the first electrode into the floating electrode layer via the thin barrier layer, and applying a voltage between the first electrode and the second electrode that is lower than the write bias voltage. A low read bias voltage is applied, and information stored in the floating electrode layer is read based on whether a current flows in the channel layer. An erase bias voltage higher than the write bias voltage is applied to the first electrode and By applying to the second electrode,
An information storage method for a semiconductor memory device, wherein the information stored in the floating electrode layer is erased by emitting electrons stored in the floating electrode layer from the second electrode via the thin barrier layer. 10. A method for storing information in a semiconductor memory device according to claim 3, wherein a write bias voltage having a higher potential on said second electrode than on said first electrode is applied. Thereby, information is written into the floating electrode layer by injecting electrons from the first electrode into the floating electrode layer through the thin barrier layer and the intermediate barrier layer, and the writing is performed between the first electrode and the second electrode. A read bias voltage lower than the write bias voltage is applied, and information stored in the floating electrode layer is read based on whether or not a current flows through the channel layer, and an erase bias voltage higher than the write bias voltage is read. By applying to the first electrode and the second electrode,
An information storage method for a semiconductor memory device, wherein the information stored in the floating electrode layer is erased by emitting electrons stored in the floating electrode layer from the second electrode through the thin barrier layer and the intermediate barrier layer. 11. A method for storing information in a semiconductor memory device according to claim 5, wherein said second electrode has a higher potential than said first electrode by applying a write bias voltage having a higher potential than said first electrode. Emitting electrons from the floating electrode layer through the thin barrier layer, forming an electron storage layer in the channel layer, writing information into the floating electrode layer, and writing information between the first electrode and the second electrode. A read bias voltage lower than the write bias voltage, and reads information stored in the floating electrode layer based on whether a current flows through the channel layer. By applying an erase bias voltage lower than the write bias voltage and higher than the read bias voltage between the electrodes, the thin barrier layer is removed from the electron storage layer in the channel layer. And injecting electrons into the floating electrode layer to erase information in the floating electrode layer.