JPH07122660A - Semiconductor memory and method for storing information - Google Patents

Abstract

PURPOSE:To provide a semiconductor memory suitable for fine patterning in which the number of wiring per unit memory cell is decreased through a simple structure while allowing high speed writing and reading. CONSTITUTION:A floating conductive layer 14 doped with impurities, an undoped barrier layer 16, a channel layer 18, an undoped thin barrier layer 20, and a conductive layer 22 are formed sequentially on a semiconductor substrate 10 and then first and second electrodes 24, 26 are provided, respectively, on the conductive layer 22 and the channel layer 18. Information is written into the floating conductive layer 14 by applying a write bias voltage which is higher for the second channel 26 than for the first electrode 24. Stored information is read out by applying a read bias voltage which is lower for the second electrode 26 than for the first electrode 24. Information written into the floating conductive layer 14 is erased by applying a erasure voltage having absolute value larger than that of the read bias voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device based on a novel operating principle and an information storage method thereof.

[0002]

2. Description of the Related Art In recent years, the progress of semiconductor integrated circuits has been remarkable, and the demand for higher speed and higher integration has been increasing. In particular, MOSF made of silicon semiconductor
High integration of semiconductor memory devices using ET is remarkable, and for example, 1 MO using one MOSFET in a memory cell.
In the case of S cell type dynamic memory (DRAM),
Currently, a large capacity DRAM of 1 Mbit to 4 Mbit is commercially available, and a large capacity DRAM of 64 Mbit to 128 Mbit is in the stage of trial manufacture.

Along with the higher integration of DRAMs, miniaturization of transistors and capacitors forming memory cells is progressing, and the size of memory cells is also miniaturized to about 2 μm square. In the 1MOS memory type DRAM,
Since the storage states of 0 and 1 are identified by the amount of electric charge accumulated in the capacitor, it is necessary to make the capacitance of the capacitor relatively large compared to the external capacitance such as wiring capacitance, which results in a large surface area for the capacitor. is necessary. Therefore, a structure having a groove formed in the semiconductor substrate or a fin structure for the capacitor is used to realize a capacitor having a large surface area in a memory cell having a small area. However, even with such a method, further miniaturization than the current situation is difficult.

In addition to a DRAM as a semiconductor memory device, an electrically writable read-only memory (EP
ROM) is known (SM G. Ed., “Semiconductor Devices”, page 501, A WILEY INTER SCIENCE PUBLIC
ATION, 1981). In this EPROM as well, it is necessary to provide three wirings for one memory cell, which takes a long time to electrically write, and even if there are two wirings, a very high voltage is required, so that a high voltage is required. It is a major barrier to integration.

In response to such a situation, a storage element (static RAM (SRAM)) using a differential negative resistance due to a quantum effect, particularly a resonance tunnel effect, has been studied (Federico Capasso (Ed.), "Physics of Quantum
Electron Devices ", pp.207-208, Springer-Verlay, 19
90; Y. Watanabe, et al., "Monolithic Integrationof
InGaAs / InAlAs Resonant Tunneling Dioge and HEMT fo
r Single-TransistorCell SRAM Application ", IEEE IE
DM 92-475, 1992).

For example, a storage element using a resonance tunnel barrier (RTB) as a load element of an FET or two resonance tunnel barriers connected in series, and voltages at two stable points due to the resonance tunneling barriers are applied to adjacent FETs. Write information by changing the gate electrode of
There has been proposed an SRAM element for reading stored information, an SRAM element for writing / reading by a threshold diode provided under two resonant tunneling barriers, and the like.

[0007]

However, these storage elements also have a problem that the number of wirings per memory cell is three or more and the area of the memory cell does not become so small. In addition, these storage elements are
Since the stored information is retained by the valley current of the resonance tunnel barrier (RTB), it is desirable to make the valley current sufficiently smaller than the peak current, but at present, the ratio of the peak current to the valley current is about 10 to 100, There is a problem that the valley current cannot be made sufficiently small.

An object of the present invention is to provide a semiconductor memory device having a simple structure, a small number of wirings per memory cell, high-speed writing and high-speed reading, and suitable for miniaturization, and an information storage method thereof. Especially.

[0009]

The above object is to provide a semiconductor substrate, a floating conductive layer formed on the semiconductor substrate and doped with impurities, a non-doped barrier layer formed on the floating conductive layer, and a barrier layer. A channel layer formed on the channel layer, a non-doped thin barrier layer formed on the channel layer, a conductive layer formed on the thin barrier layer, a first electrode formed on the conductive layer, and a channel layer And a second electrode formed on the semiconductor memory device.

The above object is to apply a write bias voltage having a higher potential to the second electrode than to the first electrode,
Information is written in the barrier layer and / or the floating conductive layer by injecting electrons from the first electrode into the barrier layer and / or the floating conductive layer through the thin barrier layer, and the potential of the second electrode is lower than that of the first electrode. The information stored in the floating conductive layer is read based on whether or not a current flows through the channel layer by applying a read bias voltage, and the potential of the second electrode is lower than that of the first electrode,
By applying an erase bias voltage having an absolute value larger than the read bias voltage, electrons accumulated in the barrier layer and / or the floating conductive layer are emitted from the first electrode through the thin barrier layer to erase information. And a method for storing information in a semiconductor memory device.

[0011]

According to the present invention, a floating conductive layer doped with impurities, a non-doped barrier layer, a channel layer, a thin non-doped barrier layer, and a conductive layer are laminated on a semiconductor substrate to form a conductive layer. Since the first electrode is formed on the first electrode and the second electrode is provided on the channel layer, by applying the write bias voltage having a higher potential to the second electrode than to the first electrode, the second electrode is thinned from the first electrode. Barrier layer and / or via barrier layer
Alternatively, whether electrons flow into the channel layer by injecting electrons into the floating conductive layer to write information in the barrier layer and / or the floating conductive layer and applying a read bias voltage having a lower potential to the second electrode than to the first electrode. Based on whether or not the information stored in the floating conductive layer is read, an erase bias voltage having a lower potential on the second electrode than the first electrode and an absolute value larger than the read bias voltage is applied, Information can be erased by discharging electrons accumulated in the barrier layer and / or the floating conductive layer from one electrode through the thin barrier layer.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to a first embodiment of the present invention will be described with reference to FIGS. A thick barrier layer 12 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 300 nm is formed on the semi-insulating InP substrate 10. On the thick barrier layer 12, n-In _0.53 Ga _0.47 As having a silicon (Si) doping amount of 1 × 10 ¹⁸ cm ⁻³ is formed.
The floating conductive layer 14 having a thickness of about 200 nm is formed.

On the floating conductive layer 14, non-doped i-
Approximately 50 consisting of In _0.52 (AlxGa1-x) _0.48 As
A barrier layer 16 having a thickness of nm is formed. Barrier layer 16
I-In _0.52 (AlxGa1-x) _0.48 As has a constant aluminum composition ratio (x value) of x = 0.5, and its barrier height is 0.27 eV as shown in FIG. 1 (b).
And is constant.

On the barrier layer 16, the doping amount of silicon is set.
Is 5 × 10¹⁷cm^-3N-In_0.53Ga_0.47From As
A channel layer 18 having a thickness of about 30 nm is formed. Chi
In the region on the left side of FIG. 1 on the channel layer 18, undoped i
-In_0.52Al_0.48Thin burr of about 5 nm thick made of As
A layer 20 is formed. Figure 1 on thin barrier layer 20
In the left side region, the silicon doping amount is 1 × 10¹⁸cm
^-3From 5 × 10¹⁹cm ^-3Up to about 20 nm thickness
n-In_0.53Ga_0.47As layer 22a and silicon layer
5 x 10¹⁹cm^-3About 50 nm thick n-In_0.53
Ga_0.47A contact layer 22 made of As layer 22b is formed.
Has been done.

A first electrode 24 made of a tungsten silicide (WSi) layer having a thickness of about 200 nm is formed on the contact layer 22, and a tungsten silicide (thickness of about 200 nm is formed on a region on the right side of FIG. 1 on the channel layer 18. WS
The second electrode 26 composed of the i) layer is formed. Instead of the tungsten silicide layer, the first electrode 24 and the second electrode 26 include a chromium layer having a thickness of about 20 nm and a thickness of about 190 n.
A Cr / Au layer in which a m-thick gold layer is stacked, or a Pd / Ge layer in which a palladium layer having a thickness of about 60 nm and a germanium layer having a thickness of about 80 nm are stacked may be used.

Next, the information storage method of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS. First, a method of writing the information “1” will be described with reference to the energy band diagram of FIG. When writing information "1" to this semiconductor memory device, one of the first electrode 24 and the second electrode 26, for example, the first electrode 24 is grounded and the second electrode 26 is set to a positive potential, about 1 V. Write bias voltage Vw is applied. When such a write bias voltage Vw is applied, most of the electrons (about 95%) injected from the first electrode 24 tunnel from the contact layer 22 to the thin barrier layer 20 as shown in FIG. , As hot electrons across the barrier layer 16 and floating conductive layer 14
To reach. Some electrons (about 5%) that cannot pass through the barrier layer 16 reach the channel layer 18 as cold electrons, as shown in FIG.

The electrons tunneling through the thin barrier layer 20 are
Most of them are hot electrons in the floating conductive layer 14.
It reaches and accumulates and raises the potential of the floating conductive layer 14.
It When the potential of the floating conductive layer 14 rises, the barrier layer 16
The potential also rises, and as shown in FIG. 2B, the barrier layer 16
As a result, hot electrons can be injected into the floating conductive layer 14.
Be blocked. As a result, the floating conductive layer 14 has a certain amount of charge.
Quantity (5 × 10^-9C / cm ²The degree of electrons accumulated
Report "1" is written.

At this time, even if the voltage of the second electrode 26 is set to 0 V and the write bias voltage Vw is removed, as shown in FIG. 2C, the potential of the floating conductive layer 14 becomes 0 due to the accumulated electrons. It will be about 2V higher. Although the electrons accumulated in the floating conductive layer 14 are slowly released, the barrier layer 16 is thick, so that the electrons are retained for about 10 seconds or longer at 77K. Next, a method of reading information will be described with reference to the energy band diagram of FIG. 3 and the graph of FIG.

In the state where no charges are accumulated in the floating conductive layer 14, the channel layer 18 is not depleted because it is only affected by the surface depletion layer (FIG. 3A). Here, when the read bias voltage Vr of about 1 V that grounds the first electrode 24 and sets the second electrode 26 to a negative potential is applied,
A current of about 5 × 10 ³ A / cm ² flows (Fig. 4
(A)).

On the other hand, when charges are accumulated in the floating conductive layer 14, the depletion layer extends from the floating conductive layer 14 and the channel layer 18 is almost depleted (FIG. 3B).
Here, even if the read bias voltage Vr of about 1 V that grounds the first electrode 24 and sets the second electrode 26 to a negative potential is applied, only a current of about 1 × 10 ³ A / cm ² flows (FIG. 4 (b)).

As described above, by applying the read bias voltage Vr and detecting the presence or absence of the current flowing between the first electrode 24 and the second electrode 26, it depends on whether or not the charge is accumulated in the floating conductive layer 14. The stored information can be read.
Next, a method of erasing the written information "1" (a method of writing the information "0") will be described with reference to the energy band diagram of FIG.

When erasing the written information "1" (when writing the information "0"), one of the first electrode 24 and the second electrode 26, for example, the first electrode 24 is grounded, The second electrode 26 is set to a negative potential, and the erase bias voltage Ve of about 3V having an absolute value larger than the read bias voltage Vr is applied. In the state where electrons are accumulated in the floating conductive layer 14 and the information “1” is written, the depletion layer extends from the floating conductive layer 14 and the channel layer 18 is depleted, so that the first electrode 24 and the second electrode 24 are depleted.
The channel layer 18 does not electrically connect between the electrodes 26. Therefore, when the erase bias voltage Ve is applied, it reaches the floating conductive layer 14 from the first electrode 24 through the contact layer 22, the thin barrier layer 20, the channel layer 18, and the barrier layer 16, and further, the floating conductive layer 14 is reached. To the second electrode 26 through the barrier layer 16 and the channel layer 18.
A current path is formed that reaches

An energy band diagram along this current path is shown in FIG. Since a large erase bias voltage Ve of about 3 V is applied, as shown in FIG. 5A, the electrons accumulated in the floating conductive layer 14 are extracted to the channel layer 18 beyond the barrier layer 16 and further thin. Barrier layer 20
The information "1" written above is erased by passing through the contact layer 22 to the first electrode 24 (the information "0" is written).

In the state where electrons are not accumulated in the floating conductive layer 14 and the information "1" is not written (the information "0" is written), the channel layer 18 is not depleted. Directly from the first electrode 24 to the second electrode 2 via the contact layer 22, the thin barrier layer 20, and the channel layer 18.
A current path reaching 6 is formed. The energy band diagram at that time is shown in FIG.

FIG. 6 shows the semiconductor memory device of this embodiment for the above-described operations of writing information "1", reading information "0" and "1", and erasing information "1" (writing information "0"). The voltage-current characteristic is shown. The first electrode 24 is grounded to the second
The voltage applied to the electrode 26 is V, and the first electrode 24 and the second electrode
The current flowing between the electrodes 26 is I. When the voltage V is increased from 0V to 1V, the current I also increases almost in proportion and the information "1" is written. Then, the voltage V is changed from 1V to 0.
When it is lowered to V, the current I is also reduced almost in proportion.

Next, the voltage V is lowered from 0V to -1V, but the current I remains almost non-flowing, and information "1" is given.
Is read. Subsequently, when the voltage V is lowered from -1V to -3V, the current I rapidly increases and the information "1" is erased (information "0" is written). Next, the voltage V
If the voltage is increased from -3V to 0V, the current I also decreases in a substantially proportional manner, but even if the voltage V is -1V, a constant amount of the current I flows and the information "0" is read.

FIG. 7 shows a pulse of +1 V (write bias voltage Vw), -1 for the semiconductor memory device of this embodiment.
The following shows an input pulse signal and an output pulse signal when V (read bias voltage Vr) pulse, -3V (erase bias voltage Vr) pulse, -1V (read bias voltage Vr) pulse, ... Are sequentially applied. It is a time chart. The input signal is shown by a solid line and the output signal is shown by a broken line. The pulse width is 1 μsec and the pulse interval is 1 μsec.

As is apparent from FIG. 7, when the read bias voltage Vr is applied, the magnitude of the output pulse is different depending on whether the information "1" is written or the information "0" is written. Is different. By setting the threshold value in the middle of the magnitude of these output pulses, the written information can be discriminated. In the semiconductor memory device of the present embodiment, since information "1" and "0" can be freely written as described above, it is usually unnecessary, but it is accumulated in the floating conductive layer 14 by irradiating with ultraviolet rays. Information can be erased at once by emitting the generated electrons.

Further, the semiconductor memory device of this embodiment is preferably operated at a low temperature of 77K or less in order to suppress a thermoelectric current component. The information storage mechanism of the semiconductor memory device according to the present embodiment will be described with reference to FIG.
Although it has been described using the energy band diagrams of FIGS. 3 and 5,
It turns out that other information storage mechanisms also exist. The mechanism will be described with reference to FIGS. 8 and 9.

First, regarding the writing method of the information "1",
This will be described with reference to the energy band diagram of FIG. When writing information "1" to this semiconductor memory device, one of the first electrode 24 and the second electrode 26, for example, the first electrode 24 is grounded and the second electrode 26 is set to a positive potential, about 1 V. Write bias voltage Vw is applied. When such a write bias voltage Vw is applied, the electrons injected from the first electrode 24 initially reach the floating conductive layer 14 as hot electrons through the barrier layer 16 as shown in FIG. 8A. .

When electrons are accumulated in the floating conductive layer 14, as shown in FIG. 8B, the potential of the floating conductive layer 14 rises and the potential of the barrier layer 16 also rises. The hot electrons injected from the first electrode 24 lose energy in the barrier layer 16 and are trapped in a deep level in the barrier layer 16. Electrons are accumulated in most of the deep levels in the barrier layer 16 and a constant charge amount (5 × 10 ⁻⁹ C / cm
^When about ² ) electrons are accumulated, as shown in FIG. 8C, the potential of the barrier layer 16 rises, hot electrons are prevented from being injected into the floating conductive layer 14, and the information “1” is written. Get caught.

At this time, the voltage of the second electrode 26 is set to 0V.
Even if the write bias voltage Vw is removed by the method shown in FIG.
As a result, the potential of the barrier layer 16 is changed by the accumulated electrons.
It becomes higher by about 0.2V. In addition, it is accumulated in the barrier layer 16.
Electrons are released slowly, but the level is about 0.15e
Deep with V, electron capture cross section is 10^{-twenty two}cm^-2Degree and small
So, at 77K, about 10¹⁹Hold for more than sec, 3
About 3 × 10 even at 00K ⁶Holds for about sec and is non-volatile
Functions as a memory.

Next, a method of reading information will be described. The method of reading information is the same as that of the mechanism described above. In the state where no electric charge is accumulated in the barrier layer 16, the channel layer 18 is not depleted because it is only affected by the surface depletion layer.
4 is grounded, and a read bias voltage Vr of about 1 V that makes the second electrode 26 a negative potential is applied, 5 × 10 ³ A /
A current of about cm ² flows.

On the other hand, in the state where charges are accumulated in the barrier layer 16, since the depletion layer extends from the barrier layer 16 and the channel layer 18 is almost depleted, the first electrode 24 is grounded and the second electrode is grounded. Even if a read bias voltage Vr of about 1 V is applied to make 26 a negative potential, 1 × 10 ³ A / cm
Only about ² current flows. In this way, by applying the read bias voltage Vr and detecting the magnitude of the current flowing between the first electrode 24 and the second electrode 26, the barrier layer 1
It is possible to read the stored information depending on whether or not the electric charge is accumulated in 6.

Next, a method of erasing the written information "1" (a method of writing the information "0") will be described with reference to the energy band diagram of FIG. When erasing the written information “1” (when writing the information “0”), one of the first electrode 24 and the second electrode 26, for example, the first electrode 24 is grounded, and the second electrode An erasing bias voltage Ve of about 3 V having an absolute value larger than that of the read bias voltage Vr is applied by setting 26 to a negative potential.

Information "1" is generated when electrons are accumulated in the barrier layer 16.
In the state in which is written, since the depletion layer extends from the barrier layer 16 and the channel layer 18 is depleted, the channel layer 18 is not electrically connected between the first electrode 24 and the second electrode 26. ing. Therefore, the erase bias voltage V
When e is applied, from the first electrode 24 to the contact layer 2
2, thin barrier layer 20, channel layer 18, barrier layer 16
A current path is formed that reaches the floating conductive layer 14 via the barrier layer 16 and the second electrode 26 from the floating conductive layer 14 via the barrier layer 16 and the channel layer 18.

An energy band diagram along this current path is shown in FIG. 9 (a). Since a large erase bias voltage Ve of about 3 V is applied, as shown in FIG. 9A, the electrons accumulated in the deep level in the barrier layer 16 are floating conductive layer 1
4 and the channel layer 18, and further the first electrode 24 over the thin barrier layer 20 and the contact layer 22.
And the written information "1" is erased (information "0" is written).

In the state where electrons are not accumulated in the barrier layer 16 and the information "1" is not written (the state where information "0" is written), the channel layer 18 is not depleted. The second electrode 26 directly from the first electrode 24 through the contact layer 22, the thin barrier layer 20, and the channel layer 18.
A current path is formed that reaches The energy band diagram at that time is shown in FIG.

It is considered that the above-mentioned mechanism in which the electrons are captured and accumulated in the deep level in the barrier layer 16 is as dominant as the above-mentioned mechanism. As described above, according to this embodiment, it is possible to realize a read-only memory (EEPROM) capable of electrically writing and erasing at high speed and a memory (DRAM) capable of writing, reading and erasing. Two
Since it is only necessary to provide a book wiring, high integration can be achieved and writing time can be shortened.

However, in the semiconductor memory device of this embodiment,
The stored information will disappear after a certain time, so
Refresh that rewrites stored information within that time
Control is needed. Next, the semiconductor memory device according to the present embodiment
A method of manufacturing the device will be described. First, the electron beam
Semi-insulating InP substrate by the epitaxial (MBE) method
10 on top of undoped i-In_0.52Al_0.48From As
Thick barrier layer (buffer layer) with a thickness of about 300 nm
2. Dope amount of silicon is 1 × 10¹⁸cm^-3N-In
_0.53Ga_0.47About 200nm thick floating conductive layer made of As
14, undoped i-In_0.52(AlxGa1-x)
_0.48Approximately 50 nm thick barrier made of As (x = 0.5)
Layer 16, silicon doping 5 × 10¹⁷cm^-3N-
In_0.53Ga _0.47About 30 nm thick channel made of As
Layer 18, undoped i-In_0.52Al_0.48From As
Thin barrier layer 20 with a thickness of about 5 nm, and the doping amount of silicon
1 x 10¹⁸cm^-3From 5 × 10¹⁹cm^-3Up to
About 20 nm thick n-In_0.53Ga_0.47As layer 22a
And the silicon doping amount is 5 × 10¹⁹cm^-3About 50n
m-thick n-In_0.53Ga_0.47As layer 22b is continuously connected
Grow crystals.

Next, the contact layer 22 is mesa-etched so that the region of the first electrode 24 remains, and the thin barrier layer 20, the channel layer 18, the barrier layer 16, and the floating conductive layer 14 are further removed so that the element region remains. Element isolation is performed by mesa etching. Next, on the contact layer 22 and the channel layer 18, about 200 nm thick tungsten silicide (WS) is formed.
i) layer, a Cr / Au layer in which a chromium layer having a thickness of approximately 20 nm and a gold layer having a thickness of approximately 190 nm are stacked, or a Pd / Ge layer in which a palladium layer having a thickness of approximately 60 nm and a germanium layer having a thickness of approximately 80 nm are stacked. To do. Then, pattern etching is performed by a normal photolithography technique to perform the first electrode 24.
And the second electrode 26 is formed.

The second electrode 26 made of an AuGe / Au layer is formed on the barrier layer 20 and alloyed to penetrate the barrier layer 20 to contact the channel layer 18 with the second electrode 26. Good. Next, a semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description.

On the semi-insulating InP substrate 10, as in the first embodiment, undoped i-In _0.52 Al _0.48 As.
A thick barrier layer 12 of about 300 nm thick, n-In _0.53 Ga _{0.47 with} a silicon doping amount of 1 × 10 ¹⁸ cm ^−3.
A floating conductive layer 14 made of As and having a thickness of about 200 nm is sequentially stacked. On the floating conductive layer 14, the undoped i-In _0.52 (AlxGa1-
x) Instead of the barrier layer 16 made of _0.48 As, a barrier layer 16 having a thickness of about 50 nm is formed by doping a part or the entire layer on the channel layer 18 side with silicon at a doping amount of 1 × 10 ¹⁸ cm ^−3. There is.

On the barrier layer 16, n-In having a silicon doping amount of 5 × 10 ¹⁷ cm ^-3 in the first embodiment is formed.
Instead of the channel layer 18 made of _0.53 Ga _0.47 As,
About 30 made of undoped i-In _0.53 Ga _0.47 As
A channel layer 18 having a thickness of nm is formed. A thin barrier layer 20 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 5 nm is formed on the channel layer 18, and the doping amount of silicon is changed from 1 × 10 ¹⁸ cm ⁻³ to 5 × 10 ¹⁹ cm ^−3. About 20 nm thick n-In _0.53 Ga _0.47 As layer 22
a and a silicon doping amount of 5 × 10 ¹⁹ cm ⁻³ , about 50
a contact layer 22 made nm thick n-In _0.53 Ga _{0. 47} As layer 22b is formed.

Electrons seep out from the barrier layer 16 into the channel layer 18, and the two-dimensional electron channel 2 appears in the channel layer 18.
8 is formed. The configuration and operation other than the formation of the two-dimensional electron channel in the channel layer are the same as those in the first embodiment, and the description thereof will be omitted. According to the present embodiment, the information is read out depending on whether or not a current flows through the two-dimensional electron channel in the channel layer, so that the information can be read out at a very high speed. Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description.

On the semi-insulating InP substrate 10, as in the first embodiment, undoped i-In _0.52 Al _0.48 As.
A thick barrier layer 12 of about 300 nm thick, n-In _0.53 Ga _{0.47 with} a silicon doping amount of 1 × 10 ¹⁸ cm ^−3.
A floating conductive layer 14 made of As and having a thickness of about 200 nm is sequentially stacked. On the floating conductive layer 14, the undoped i-In _0.52 (AlxGa1-
x) A resonant tunneling barrier layer 30 having a resonant tunneling barrier (RTB) is formed instead of the barrier layer 16 made of _0.48 As. The original peak voltage of the resonant tunneling barrier layer 30 is 0.5V and the valley voltage is 1.0V.

The resonant tunneling barrier layer 30 is shown in FIG.
As shown in (b), from the floating conductive layer 14 side, an i-InAlAs barrier layer 30a having a barrier height of 0.53 eV and a thickness of about 3 nm, and an i-InGaAs well layer 30 having a thickness of about 2 nm.
b, i-InA with a barrier height of 0.53 eV and a thickness of about 3 nm
It has a structure in which the 1As barrier layer 30c is laminated.
On the resonance tunneling barrier layer 30, as in the first embodiment, n− with a silicon doping amount of 5 × 10 ¹⁷ cm ⁻³ is used.
A channel layer 18 made of In _0.53 Ga _0.47 As, a thin barrier layer 20 made of undoped i-In _0.52 Al _0.48 As with a thickness of about 5 nm, and a silicon doping amount of 1 × 10 ¹⁸ c
The n-In _0.53 Ga _0.47 As layer 22a having a thickness of about 20 nm changed from m ⁻³ to 5 × 10 ¹⁹ cm ⁻³ and the n-In having a thickness of about 50 nm with a silicon doping amount of 5 × 10 ¹⁹ cm ^−3.
_The contact layer 22 made of _0.53 Ga _0.47 As layer 22b is sequentially laminated.

A first electrode 24 is formed on the contact layer 22, and a second electrode 26 is formed on the channel layer 18. Next, the information storage method of the semiconductor memory device according to the present embodiment will be described with reference to FIG. FIG. 12 shows the voltage-current characteristics of the semiconductor memory device of this embodiment. First electrode 24
Is grounded and the voltage applied to the second electrode 26 is V,
The current flowing between the electrode 24 and the second electrode 26 is I.

When the voltage V is increased from 0V to 1V, the current I reaches its maximum value in the vicinity of the peak voltage V, and then decreases. The electrons injected by tunneling the thin barrier layer 20 are resonantly tunneled by the resonant tunneling barrier layer 30 and injected and accumulated in the floating conductive layer 14. In this way, the information "1" is written. It takes about 1 psec for the electrons injected from the first electrode 24 to reach the floating conductive layer 14 as hot electrons.
Very high speed information writing is possible. Moreover, in this case, the current that effectively flows when the voltage is applied from 0 V to 1 V can have low power consumption due to the existence of the valley region.

Then, when the voltage V is lowered from 1V to 0V, the current I changes in the same manner as when the voltage V rises. When electrons are accumulated in the floating conductive layer 14, the potential rises by about 0.2 V, whereby the channel layer 18 is depleted. Even if the voltage of the second electrode 26 is set to 0V, the resonant tunneling barrier layer 30 exists, so that electrons are not immediately emitted from the floating conductive layer 14 and the potential of the floating conductive layer 14 is kept at about 0.2V for a certain period of time. Retained. In this embodiment, 10 ⁶ s
The potential is held at about ec.

Next, when the voltage V is lowered from 0 V to -1 V while the potential of the floating conductive layer 14 is held, the channel layer 18 is depleted by the electrons accumulated in the floating conductive layer 14. Therefore, the current I is as small as about 1 × 10 ³ A / cm ² . Then, when the voltage V is lowered from -1V to -3V, the current I gradually increases, the collect barrier becomes reverse bias, the electrons accumulated in the floating conductive layer 14 are extracted, and the information "1" is erased. (Information “0” is written). The electrons accumulated in the floating conductive layer 14 are transmitted through the resonance tunneling barrier layer 30 to the first electrode 2
The tunnel time for pulling out to 4 is about 10 psec. At this time, the characteristics of the resonant tunneling barrier layer 30 are irrelevant, and are limited by the channel current limited to the velocity saturation from the second electrode 26 to the channel layer 18 immediately below the first electrode 24.

Next, when the voltage V is increased from -3V to 0V, the channel layer 18 is conducting, so that the current I increases and a large hysteresis is drawn in the vicinity of -1V. Therefore, a large current I of about 1 × 10 ⁴ A / cm ² at a voltage V of −1 V flows, and information “0” is read. As described above, according to this embodiment, a read-only memory (EEPRO) capable of electrically writing and erasing at high speed and low power consumption is used.
M) and memory that can be written, read and erased (DRAM)
Can be realized. Since only two wirings need to be provided, high integration is possible and writing time can be shortened.

However, since the stored information in the semiconductor memory device of this embodiment disappears after a certain time,
Refresh control is required to rewrite the stored information within that time. Next, a semiconductor memory device according to the fourth embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description.

On the semi-insulating InP substrate 10, as in the first embodiment, undoped i-In _0.52 Al _0.48 As.
A thick barrier layer 12 of about 300 nm thick, n-In _0.53 Ga _{0.47 with} a silicon doping amount of 1 × 10 ¹⁸ cm ^−3.
A floating conductive layer 14 made of As and having a thickness of about 200 nm is sequentially stacked. On the floating conductive layer 14, the undoped i-In _0.52 (Al _0.5 G in the first embodiment is formed.
a _0.5 ) _0.48 As, instead of the barrier layer 16 made of non-doped i-In _0.52 (A
A barrier layer 30 made of lxGa1-x) _0.48 As and having a thickness of about 50 nm is formed. For example, as shown in FIG. 13B, if x = 0.50 on the floating conductive layer 14 side, x = 0.75 on the opposite side, and x = 0.75 on the floating conductive layer 14 side.
If 0.25, x = 0.50 on the opposite side.

On the barrier layer 30, the same as in the first embodiment.
And the silicon doping amount is 5 × 10 ¹⁷cm^-3N-In
_0.53Ga_0.47Channel layer 18 made of As, non-doped
I-In_0.52Al_0.48Thin about 5 nm thick consisting of As
Barrier layer 20, the doping amount of silicon is 1 × 10¹⁸cm^-3
From 5 × 10¹⁹cm^-3Up to about 20 nm n
-In_0.53Ga_0.47As layer 22a and silicon doping
The amount is 5 × 10¹⁹cm^-3About 50 nm thick n-In_0.53G
a_0.47The contact layer 22 composed of the As layer 22b is in order.
Are stacked on.

Next, the information storage method of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS. 14 to 16. First, a method of writing the information “1” will be described with reference to the energy band diagram of FIG. When writing information "1" to this semiconductor memory device, the first electrode 24
One of the second electrodes 26, for example, the first electrode 24 is grounded, and a write bias voltage Vw of about 1 V that makes the second electrode 26 a positive potential is applied. When such a write bias voltage Vw is applied, most of the electrons injected from the first electrode 24 tunnel through the thin barrier layer 20 from the contact layer 22 as shown in FIG. Floating conductive layer 14 beyond layer 32
To reach.

The electrons tunneling through the thin barrier layer 20 are
Although it is accumulated in the floating conductive layer 14 and raises the potential of the floating conductive layer 14, in this embodiment, since the barrier height on the floating conductive layer 14 side is low, as shown in FIG. Therefore, injection of hot electrons into the floating conductive layer 14 is hard to be blocked, and as a result, a large amount of electrons (about 5 × 10 ⁻⁹ C / cm ² ) are accumulated in the floating conductive layer 14.

After that, even if the write bias voltage Vw is removed by setting the voltage of the second electrode 26 to 0V, the potential of the floating conductive layer 14 becomes 0. It becomes about 2V higher. Next, a method of reading information will be described with reference to the energy band diagram of FIG.

In the state where no charges are accumulated in the floating conductive layer 14, the channel layer 18 is not depleted because it is only affected by the surface depletion layer (FIG. 15A). Here, when the read bias voltage Vr of about 1 V that grounds the first electrode 24 and sets the second electrode 26 to a negative potential is applied,
A current of about 5 × 10 ⁻³ A / cm ² flows. On the other hand, in the state where electric charges are accumulated in the floating conductive layer 14, the depletion layer extends from the floating conductive layer 14 and the channel layer 18 is almost depleted (FIG. 15B). Here, the first electrode 2
4 is grounded, and a read bias voltage Vr of about 1 V that makes the second electrode 26 a negative potential is applied, 1 × 10 ⁻³ A /
Only a current of about cm ² flows.

As described above, by applying the read bias voltage Vr and detecting the presence / absence of a current flowing between the first electrode 24 and the second electrode 26, it depends on whether or not the charge is accumulated in the floating conductive layer 14. The stored information can be read.
Next, a method of erasing the written information "1" (writing method of the information "0") will be described with reference to the energy band diagram of FIG.

When erasing the written information "1" (when writing the information "0"), one of the first electrode 24 and the second electrode 26, for example, the first electrode 24 is grounded, The second electrode 26 is set to a negative potential, and the erase bias voltage Ve of about 2V having an absolute value larger than the read bias voltage Vr is applied. In the state where electrons are accumulated in the floating conductive layer 14 and the information “1” is written, the depletion layer extends from the floating conductive layer 14 and the channel layer 18 is depleted.
Contact layer 22, thin barrier layer 20, channel layer 1
8, the floating conductive layer 14 is reached through the barrier layer 32, and the barrier layer 32 and the channel layer 1 are further extended from the floating conductive layer 14.
A current path reaching the second electrode 26 via 8 is formed.

An energy band diagram along this current path is shown in FIG. Since a large erase bias voltage Ve of about 3 V is applied, as shown in FIG.
The electrons accumulated in the floating conductive layer 14 are extracted to the channel layer 18 over the barrier layer 32, and further to the first electrode 24 via the contact layer 22 over the thin barrier layer 20 and written. Information "1" is erased (information "0" is written). Barrier layer 3 on the side of the floating conductive layer 14
Since the barrier height of 2 is low, the information "1" can be erased at a high speed with a low erase bias voltage Ve of about 2V.

In the state where electrons are not accumulated in the floating conductive layer 14 and information "1" is not written, the channel layer 1
Since 8 is not depleted, a current path is formed from the first electrode 24 directly to the second electrode 26 via the contact layer 22, the thin barrier layer 20, and the channel layer 18. The energy band diagram at that time is shown in FIG.

As described above, according to this embodiment, the read-only memory (EPRO) capable of electrically writing and erasing at high speed is used.
M) and memory that can be written, read and erased (DRAM)
Can be realized. Since the barrier height of the barrier layer on the floating conductive layer side is low, writing and erasing of information can be performed with a low bias voltage. Next, a semiconductor memory device according to the fifth embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description.

On the semi-insulating InP substrate 10, undoped i-In _0.52 Al _0.48 As was formed as in the first embodiment.
A thick barrier layer 12 of about 300 nm thick, n-In _0.53 Ga _{0.47 with} a silicon doping amount of 1 × 10 ¹⁸ cm ^−3.
A floating conductive layer 14 made of As and having a thickness of about 200 nm is sequentially stacked. On the floating conductive layer 14, the undoped i-In _0.52 (Al _0.5 G in the first embodiment is formed.
Instead of the barrier layer 16 made of a _0.5 ) _0.48 As, as shown in FIG. 17B, a non-doped i-In _0.52 Al _0.48 As layer 34 a having a thickness of about 1.465 nm and a thickness of about 1.46 are used.
Non-doped i-In _0.53 Ga _0.47 As layer 3 with a thickness of 5 nm
Approximately 14 consisting of superlattices in which 4b are alternately laminated for 50 periods
A superlattice barrier layer 34 having a thickness of 6.5 nm is formed.
Electrons are accumulated in the multiple quantum wells of the superlattice barrier layer 34.

On the superlattice barrier layer 34, as in the first embodiment, n having a silicon doping amount of 5 × 10 ¹⁷ cm ⁻³ is used.
-In _0.53 Ga _0.47 channel layer 18 made of As, thin barrier layer 20 of approximately 5nm thickness made of undoped i-In _0.52 Al _0.48 As, a doping amount of silicon 1 × 10 ¹⁸
Approximately 20 nm varied from cm ^-3 to 5 x 10 ¹⁹ cm ^-3
N-In _0.53 Ga _0.47 As layer 22a with a thickness of about 50 nm with a silicon doping amount of 5 × 10 ¹⁹ cm ^−3.
_The contact layer 22 made of _0.53 Ga _0.47 As layer 22b is sequentially laminated.

As the superlattice barrier layer 34, as shown in FIG.
7 (c), a non-doped i-In _0.52 Al _0.48 As layer 34a having a thickness of about 1.465 nm and a thickness of about 1.465 are formed.
nm non-doped i-In _0.52 (AlxGa1-
x) About _0.48 As layers 34b are alternately stacked for about 50 cycles
A superlattice structure having a thickness of 46.5 nm may be used. In this embodiment,
Information is stored by accumulating the electrons injected from the electrodes in the multiple quantum well of the superlattice barrier layer 34 together with the floating conductive layer 14. The operation other than the operation of accumulating electrons in the superlattice barrier layer 34 is the same as that of the first embodiment, and therefore its explanation is omitted.

According to the present embodiment, electrons are stored in the multiple quantum wells of the superlattice barrier layer 34, and it is relatively easy to form multiple quantum wells with desired characteristics. It is possible to realize a good memory cell. Next, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description.

On the semi-insulating InP substrate 10, non-doped
I-In_0.52Al_0.48About 300nm thick consisting of As
Thick barrier layer 12 is formed. This thick barrier
On the layer 12, elements are isolated in the region on the left side of FIG.
In the same manner as the first embodiment, the silicon doping amount is 1 ×.
10¹⁸cm^-3N-In_0.53Ga_0.47About 2 consisting of As
00 nm thick floating conductive layer 14, non-doped i-In
_0.52(AlxGa1-x)_0.48Barrier layer 1 made of As
6, the doping amount of silicon is 5 × 10¹⁷cm^-3N-In
_0.53Ga_0.47Channel layer 18 made of As, non-doped
I-In_0.52Al_0.48Thin about 5 nm thick consisting of As
Barrier layer 20, the doping amount of silicon is 1 × 10¹⁸cm^-3
From 5 × 10¹⁹cm^-3About 70 nm thick n-I
n_0.53Ga _0.47Contact layer 22 made of As is in order
Are stacked on. Further, the first layer is formed on the contact layer 22.
The electrode 24 is formed, and the second electrode 26 is formed on the channel layer 18.
Are formed.

In this way, on the semi-insulating InP substrate 10
The semiconductor memory device of this embodiment is formed in the region on the left side of
There is. On the other hand, the right region on the semi-insulating InP substrate 10
In addition, HET and RHET having the same layer structure as the semiconductor memory device
Are formed. That is, on the thick barrier layer 12,
With the elements separated, the doping amount of silicon is 1 × 10
¹⁸cm^-3N-In_0.53Ga_0.47About 200 made of As
nm collector layer 40, undoped i-In
_0.52(AlxGa1-x)_0.48Barrier layer 4 made of As
2. Dope amount of silicon is 5 × 10¹⁷cm^-3N-In
_0.53Ga_0.47Base lead-out layer 44 made of As, non-doped
I-In_0.52Al_0.48About 5 nm thick made of As
Thin base layer 46, silicon doping amount of 1 × 10¹⁸c
m^-3From 5 × 10¹⁹cm^-3About 70 nm thick
-In_0.53Ga_0.47Emitter layer 4 composed of As layer 48b
8 and 8 are sequentially stacked in a step-like manner.

The collector layer 40 is the same layer as the floating conductive layer 14, the barrier layer 42 is the same layer as the barrier layer 16,
The base extraction layer 44 is the same layer as the channel layer 18,
The base layer 46 is the same layer as the thin barrier layer 20, and the emitter layer 48 is the same layer as the contact layer 22. A collector electrode 50 is formed on the collector layer 40, a base electrode 52 is formed on the base extraction layer 44, and an emitter electrode 54 is formed on the emitter layer 48.

As described above, according to this embodiment, the multi-emitter type InGaAs / In (AlGa) As hot electron transistor (HET) and the resonant tunneling hot electron transistor (simultaneously with the memory element are formed on the semi-insulating InP substrate 10. RHET) can be formed. Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to FIG. The same components as those of the semiconductor memory device of the sixth embodiment shown in FIG. 18 are designated by the same reference numerals to omit or simplify the description.

In the present embodiment, FET is used in the right region on the semi-insulating InP substrate 10 instead of HET or RHET.
(HEMT) is formed. That is, n-In _0.53 G having a thickness of about 200 nm and a doping amount of silicon of 1 × 10 ¹⁸ cm ⁻³ is isolated on the thick barrier layer 12 in a device isolation state.
a _0.47 As layer 60, undoped i-In _0.52 (Alx
Ga1-x) _0.48 As layer 62, the doping amount of silicon is 5
A channel layer 64 of × 10 ¹⁷ cm ^{−3 made} of n-In _0.53 Ga _0.47 As is laminated in order.

On the left side of the contact layer 64, a thin barrier layer 66 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 5 nm, and a silicon doping amount of 1 × 10 ¹⁸ cm.
^-3 to 5 x 10 ¹⁹ cm ^-3 n- with a thickness of about 70 nm
A source electrode 70 is formed via a contact layer 68 made of In _0.53 Ga _0.47 As. A drain electrode 72 is formed on the right side of the contact layer 64. A gate electrode 74 made of tungsten silicide (WSi) or aluminum (Al) is formed on the contact layer 64 between the source electrode 70 and the drain electrode 72.

The electron supply layer 60 is the same layer as the floating conductive layer 14, the active layer 62 is the same layer as the barrier layer 16, the contact layer 64 is the same layer as the channel layer 18, and the thin barrier layer 66 is thin. The contact layer 68 is the same layer as the barrier layer 20, and the contact layer 68 is the same layer as the contact layer 22. As described above, according to the present embodiment, the FET (HEMT) can be formed simultaneously with the memory element on the semi-insulating InP substrate 10, and the amplification of the stored information and the peripheral circuit for the memory element can be easily formed. be able to.

Next, a semiconductor memory device according to the eighth embodiment of the present invention will be described with reference to FIGS. In this embodiment, a large number of memory cells according to the above-mentioned first to seventh embodiments are arranged in a matrix to form a memory. Each memory cell MC11, MC12, ..., MC5
4, MC55 has a first electrode E1 and a second electrode E, respectively.
2 and are provided. Word lines WL1, WL2, ...
WL5 is made of Ti / Pt / Au or the like, and is horizontally adjacent to the memory cells MC11, MC12, ..., MC54, M.
The first electrodes E1 of C55 are connected to each other. Word line WL
1, WL2, ..., WL5 and bit lines BL1 and B orthogonal to
L2, ..., BL5 are made of Ti / Pt / Au or the like, and vertically adjacent memory cells MC11, MC12 ,.
The second electrodes E2 of C54 and MC55 are connected to each other.

Next, a specific example of the information storage method of the semiconductor memory device according to the present embodiment will be described with reference to FIGS. First, a method of writing information "1" in a specific memory cell in the memory cell array will be described with reference to FIG. When writing information “1” to a specific memory cell in the memory cell array, for example, the memory cell MC15, 0V (ground) is applied to the word line WL1, the word line WL2,
Applying + 1V to WL3, WL4, WL5, and bit line B
0V (ground) is applied to L1, BL2, BL3, and BL4, and + 1V is applied to the bit line BL5. Only memory cell MC15 has 0V applied to the first electrode E1 and + 1V applied to the second electrode E2, and information "1" is written.

Regarding the other memory cells, the memory cells MC11, MC12, MC13 and MC14 are the first memory cells.
Since 0 V is applied to both the electrode E1 and the second electrode E2,
The memory content does not change. Also, the memory cell MC
25, MC35, MC45, MC55, the first electrode E
Since +1 V is applied to both 1 and the second electrode E2, the stored contents do not change. Furthermore, the memory cell MC2
1, MC22, MC23, MC24, MC31, MC3
2, MC33, MC34, MC41, MC42, MC4
3, MC44, MC51, MC52, MC53, MC5
In No. 4, since + 1V is applied to the first electrode E1 and 0V is applied to the second electrode E2, the stored contents do not change.

Next, a method of erasing information "1" of a specific memory cell in the memory cell array (a method of writing information "0") will be described with reference to FIG. A specific memory cell in the memory cell array, for example, memory cell MC1
When erasing the information "1" of 5 (writing the information "0"), 0 V (ground) to the word line WL1 and the word line W
Apply -1.5V to L2, WL3, WL4, WL5,
-1V is applied to the bit lines BL1, BL2, BL3, BL4 and -3V is applied to the bit line BL5. Memory cell MC15
Only 0V is applied to the first electrode E1 and -3V is applied to the second electrode E2, and the information "1" is erased (information "0" is written).

For the other memory cells, the memory cells MC11, MC12, MC13, MC14 are
Since 0V is applied to the electrode E1 and -1V is applied to the second electrode E2, the stored contents do not change. Further, in the memory cells MC25, MC35, MC45, and MC55, since −1.5V is applied to the first electrode E1 and −3V is applied to the second electrode E2, the stored content does not change. Further, memory cells MC21, MC22, MC23, MC24, MC
31, MC32, MC33, MC34, MC41, MC
42, MC43, MC44, MC51, MC52, MC
53 and MC54, the first electrode E1 is -1.5V,
Since -1 V is applied to the electrode E2, the stored contents do not change.

Next, a method of reading information from a specific memory cell in the memory cell array will be described with reference to FIG. A specific memory cell in the memory cell array, for example,
Memory cells MC11, MC12, MC13, MC14,
When reading the information of MC15, 0 is applied to the word line WL1.
V (ground), word lines WL2, WL3, WL4, WL5
To the bit lines BL1, BL2, BL3,
-1V is applied to BL4 and BL5. Memory cell MC1
0V and -1V are applied to the first electrode E1 and the second electrode E2 of 1, MC12, MC13, MC14, and MC15, respectively, and the memory cells MC11, MC12, MC13, MC14, and MC
The stored contents are read out at 15.

Other memory cells MC21, MC22,
MC23, MC24, MC25, MC31, MC32,
MC33, MC34, MC35, MC41, MC42,
MC43, MC44, MC45, MC51, MC52,
In MC53, MC54, and MC55, since -1V is applied to both the first electrode E1 and the second electrode E2, the stored content is not read out and the stored content does not change.

Next, a method of collectively erasing the information "1" of the memory cells in a specific area in the memory cell array (a method of collectively writing the information "0") will be described with reference to FIG. A specific area in the memory cell array, for example,
9 memory cells MC22, MC23, MC24, MC
32, MC33, MC34, MC42, MC43, MC
When collectively erasing the information "1" of 44 (when collectively writing the information "0"), -1.5 is applied to the word line WL1.
V, 0V (ground) to the word lines WL2, WL3, WL4,
Applying -1.5V to WL5, 0V to bit line BL1,
-3V to bit lines BL2, BL3, BL4, bit line B
0V is applied to L5. 9 memory cells MC described above
22, MC23, MC24, MC32, MC33, MC
0V is applied to the first electrode E1 and -3V is applied to the second electrode E2 of 34, MC42, MC43, and MC44, and the information "1" is erased (information "0" is written).

For memory cells outside the specific region, memory cells MC11, MC12, MC13, MC14, M
C15, MC21, MC22, MC23, MC24, M
In C25, -1.5V is applied to the first electrode E1 and the second electrode E2 is applied.
Since 0V or -3V is applied to, the stored contents do not change. In addition, the memory cells MC21, MC31,
In MC41, MC25, MC35, and MC45, 0 V is applied to the first electrode E1 and 0 V is applied to the second electrode E2,
The memory content does not change.

Next, another specific example of the information storage method of the semiconductor memory device according to the present embodiment will be described with reference to FIGS. This specific example is different from the specific examples shown in FIGS. 20 and 21 in the method of erasing the information “1” (the method of writing the information “0”). In the specific examples shown in FIGS. 20 and 21, a maximum voltage of 3V is required when erasing the information “1”.
In this specific example, a maximum voltage of 1.5 V is sufficient. Since the method of writing the information "1" in the memory cell and the method of reading the information in the memory cell are the same, the description thereof will be omitted.

First, a method of erasing information "1" of a specific memory cell in the memory cell array (a method of writing information "0") will be described with reference to FIG. A specific memory cell in the memory cell array, for example, memory cell MC1
When erasing the information "1" of No. 5 (when writing the information "0"), + 1.5V is applied to the word line WL1 and the word line WL
0V is applied to 2, WL3, WL4, and WL5, 0V is applied to the bit lines BL1, BL2, BL3, BL4, and the bit line BL
5 is applied with -1.5V. Only in the memory cell MC15, + 1.5V is applied to the first electrode E1 and −1.5V is applied to the second electrode E2, and the information “1” is erased (information “0” is written).

Regarding the other memory cells, the memory cells MC11, MC12, MC13, MC14 are
Since + 1.5V is applied to the electrode E1 and 0V is applied to the second electrode E2, the stored contents do not change. Further, in the memory cells MC25, MC35, MC45, and MC55, since 0 V is applied to the first electrode E1 and −1.5 V is applied to the second electrode E2, the stored contents do not change. Further, memory cells MC21, MC22, MC23, MC24, M
C31, MC32, MC33, MC34, MC41, M
C42, MC43, MC44, MC51, MC52, M
In C53 and MC54, since 0 V is applied to the first electrode E1 and 0 V is applied to the second electrode E2, the stored contents do not change.

Next, a method of collectively erasing information "1" of memory cells in a specific area in the memory cell array (a method of collectively writing information "0") will be described with reference to FIG. A specific area in the memory cell array, for example,
9 memory cells MC22, MC23, MC24, MC
32, MC33, MC34, MC42, MC43, MC
When collectively erasing the information "1" of 44 (when collectively writing the information "0"), 0V is applied to the word line WL1, + 1.5V is applied to the word lines WL2, WL3 and WL4, and 0 is applied to the WL5.
V is applied to the bit line BL1 to 0 V, the bit line BL2,
-1.5V is applied to BL3 and BL4, and 0V is applied to the bit line BL5. The nine memory cells MC22 and MC2 described above
3, MC24, MC32, MC33, MC34, MC4
2, + 1.5V to the first electrode E1 of MC43, MC44,
-1.5V is applied to the second electrode E2, and the information "1" is erased (information "0" is written).

For memory cells outside the specific region, memory cells MC11, MC12, MC13, MC14, M
C15, MC21, MC22, MC23, MC24, M
In C25, 0V is applied to the first electrode E1 and 0V is applied to the second electrode E2.
Alternatively, since −1.5 V is applied, the stored contents do not change. Also, the memory cells MC21, MC31, M
In C41, MC25, MC35, and MC45, since +1.5 V is applied to the first electrode E1 and 0 V is applied to the second electrode E2, the stored contents do not change.

As described above, according to the present embodiment, since two wirings may be provided for one memory cell, the stored information can be written or read at high speed. Also, a conventional semiconductor memory device, for example, a silicon MOS
1MOS cell type DRA using FET and capacitor
In the case of M, the cell area is about 2 μm ^{2 according} to the rule of 0.6 μm, whereas in the case of this embodiment, the cell area is about 1 μm ²
Can be made smaller.

Further, in the present embodiment, since a capacitor having a large occupied area is not required, the manufacturing process becomes very simple. Furthermore, if further miniaturization is requested,
In the DRAM using silicon, the noise margin due to the capacitance of the capacitor is a problem, whereas in the semiconductor memory device of this embodiment, there is no particular problem with miniaturization, and further miniaturization is required. Is possible. Next, a semiconductor memory device according to a ninth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. The same components as those of the semiconductor memory device of the first embodiment shown in FIG. 1 are designated by the same reference numerals to omit or simplify the description.

The semiconductor memory device of this embodiment is shown in FIG.
Explain. In this embodiment, the memory cell is as shown in FIG.
It is a structure suitable for arranging in a matrix
It has a feature. On the semi-insulating InP substrate 10, the first
In the same manner as in the above example, non-doped i-In_0.52Al_0.48
A thick barrier layer 12 made of As and having a thickness of about 300 nm is formed.
Has been done. An oxide film 80 is formed on the thick barrier layer 12.
Each memory cell is separated and the silicon doping amount is 1
× 10¹⁸cm^-3N-In_0.53Ga_0.47Approximately composed of As
200 nm thick floating conductive layer 14, non-doped i-In
_0.52(AlxGa1-x) _0.48Barrier layer 1 made of As
6, the doping amount of silicon is 5 × 10¹⁷cm^-3N-In
_0.53Ga_0.47The channel layer 18 made of As is laminated in order.
Has been done.

The area on the left side of the channel layer 18 of each memory cell
In the region, undoped i-In_0.52Al_0.48From As
And a thin barrier layer 20 having a thickness of about 5 nm and silicon doping
1 x 10¹⁸cm^-3From 5 × 10¹⁹cm^-3Changed
About 70 nm thick n-In _0.53Ga_0.47Consists of As
The contact layer 22 is sequentially stacked. Each memory
In the region on the right side of the channel layer 18 of the cell, the second electrode 82
Are formed. The second electrode 82 is on the paper surface of FIG.
The second electrode of each memory cell
It functions as a commonly connected bit line BL. Bit line B
L is filled with an oxide film 84.

On the contact layer 22 of each memory cell,
The first electrode 86 is formed. The first electrode 86 is
It functions as a word line WL that extends in the left-right direction on the paper surface of FIG. 24 and commonly connects the first electrodes of the memory cells. As described above, according to the present embodiment, the matrix in which the memory cells are connected by the word lines and the bit lines that connect the memory cells vertically and horizontally without newly forming the wiring that commonly connects the first electrode or the second electrode of each memory cell. Arrays can be realized.

Next, the method of manufacturing the semiconductor memory device according to the present embodiment will be explained with reference to FIGS. First, by a molecular beam epitaxial (MBE) method, semi-insulating In
On the P substrate 10, non-doped i-In _0.52 Al _0.48 A
A thick barrier layer 12 made of s and having a thickness of about 300 nm, and n-In _0.53 Ga having a silicon doping amount of 1 × 10 ¹⁸ cm ^−3.
About 200 nm thick floating conductive layer 14 of _0.47 As, undoped i-In _0.52 (AlxGa1-x) _0.48 As
And a channel layer 18 of about 30 nm thick made of n-In _0.53 Ga _0.47 As with a silicon doping amount of 5 × 10 ¹⁷ cm ⁻³ are sequentially deposited (FIG. 25A). ).

Next, a resist layer 90 is applied on the entire surface and patterned into a memory cell shape, and the floating conductive layer 14, barrier layer 16 and channel layer 18 are etched into a mesa shape using the patterned resist layer 90 as a mask. (FIG. 25 (b)). Next, a resist layer 92 is applied on the entire surface, and the resist layer 92 is patterned into a shape on the mesa of the memory cell so as to cover a region where first electrodes and second electrodes to be described later are formed. Then, an oxide film 80 is formed on the entire surface.
Are deposited to isolate the elements between the memory cells (see FIG. 25).
(C)).

Next, the resist layer 92 was removed (see FIG. 26).
After (d)), a resist layer 94 is newly applied on the entire surface and patterned so that the region where the second electrode (bit line) is formed is opened (FIG. 26E). Then, a tungsten silicide layer 82 forming the second electrode 82 (bit line BL) is deposited on the entire surface (FIG. 26E). Next, the resist layer 94 is removed and the excess tungsten silicide layer is removed by lift-off to expose the surface of the channel layer 18 (FIG. 26 (f)).

Next, electron beam epitaxial (MB
By the method E), a crystal is regrown on the exposed surface of the channel layer 18, and a thin barrier layer 20 made of non-doped i-In _0.52 Al _0.48 As and having a thickness of about 5 nm, and a silicon doping amount of 1 × 10 ¹⁸ cm 2. ^-3 to 5 × 10 ¹⁹ cm ^-3, and a contact layer 22 made of n-In _0.53 Ga _0.47 As having a thickness of about 70 nm is sequentially deposited (FIG.
(G)).

Next, an oxide film 84 is formed on the entire surface and the second
The entire memory cell including the electrode (bit line) 82 is embedded (FIG. 27 (h)). Next, the oxide film 84 is etched by a mixed etching gas of CF ₄ and O ₂ , and is etched until the oxide film 84 is flattened and the upper surface of the contact layer 22 is exposed (FIG. 27I). Subsequently, a Cr / Au layer or a Pd / Ge layer to be the first electrode (word line) is deposited on the entire surface and then patterned to form a first electrode 86 (word line WL), and a semiconductor memory device is manufactured. Ends (FIG. 27 (i)).

As described above, according to this embodiment, a semiconductor memory device in which memory cells are arranged in a matrix can be manufactured with a small number of steps. Next, a semiconductor memory device according to a tenth embodiment of the present invention will be described with reference to FIG. This embodiment is also suitable for arranging memory cells in a matrix as shown in FIG. It is characterized in that the structure of the semiconductor memory device according to the first to ninth embodiments is turned upside down and the second electrode is embedded in the substrate as a common wiring (word line).

On the semi-insulating InP substrate 100, approximately 200 nm of undoped i-In _0.52 Al _0.48 As is formed.
A thick buffer layer 102 is formed. Buffer layer 1
On 02, the emitter layer 104 doped amount of silicon is made of 1 × 10 ¹⁹ cm to about 200nm thick ^{_{-3 n-In 0. 53 Ga 0.47}} As is formed. The emitter layers 104 of the memory cells arranged in the left-right direction on the paper surface are commonly connected and function as word lines WL. It should be noted that the first electrode 10 common to each memory cell is provided at the end of the emitter layer 104.
6 is provided.

[0102] On the emitter layer 104 is separated for each memory cell, a thin barrier layer 108 of about 5nm thick made of undoped _{i-In 0. 52 Al 0.48 As} , doping amount of silicon 5 × 10 ¹⁷ cm ^-3 n-In _0.53 Ga _0.47 As
The channel layer 110 having a thickness of about 30 nm is laminated. In a region on the right side of the channel layer 110 of each memory cell, tungsten silicide (WS) having a thickness of about 200 nm is formed.
The second electrode 112 including the i) layer is formed. The second electrode 112 penetrates from the front side to the back side of the paper surface of FIG. 28 and functions as a bit line BL that commonly connects the second electrodes of the memory cells.

To the left of the channel layer 110 of each memory cell
In the region, undoped i-In_{0. 52}(AlxGa1-
x)_0.48Thick barrier layer 1 made of As and having a thickness of about 200 nm 1
12 are formed. On top of the thick barrier layer 114,
The doping amount of recon (Si) is 1 × 10¹⁸cm^-3N-I
n_0.53Ga_0.47About 200 nm thick floating conductor made of As
The layer 116 is formed. On the floating conductive layer 116,
Undoped i-In _0.52Al_0.48About 5n made of As
A barrier layer 118 having a thickness of m is formed.

As described above, according to this embodiment, the word line and the bit line connecting the memory cells vertically and horizontally are formed without newly forming the wiring commonly connecting the first electrode or the second electrode of each memory cell. A connected matrix arrangement can be realized. The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, InGaAs / I
An n (AlGa) As-based compound semiconductor material was used,
GaAs / AlGaAs system, InGaAs / InP system,
Compound semiconductor materials such as InAs / AlGaAsSb series, semiconductor materials such as Si and SiGe, Si and SiO ₂ and combinations of metals and insulators such as CaF and CoSi,
Superconducting materials such as Nb and NbO, MgO and SrTiO ₃
Other materials such as oxide superconductors may also be used.

[0105]

As described above, according to the present invention, a floating conductive layer doped with impurities, a non-doped barrier layer, a channel layer, a thin non-doped barrier layer, and a conductive layer are formed on a semiconductor substrate. Since the first electrode was formed on the conductive layer and the second electrode was provided on the channel layer by applying a writing bias voltage in which the second electrode had a higher potential than the first electrode, , Electrons are injected from the first electrode through the thin barrier layer into the barrier layer and / or the floating conductive layer to write information in the barrier layer and / or the floating conductive layer, and the potential of the second electrode is higher than that of the first electrode. The information stored in the floating conductive layer is read based on whether or not a current flows through the channel layer by applying a low read bias voltage, and the potential of the second electrode is lower than that of the first electrode and is lower than the read bias voltage. Also has a large absolute value By applying a scan voltage, the first
Information can be erased by discharging electrons accumulated in the barrier layer and / or the floating conductive layer from the electrode through the thin barrier layer.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is an energy band diagram for explaining a method of writing information “1” in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is an energy band diagram for explaining a method of reading information from the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a graph for explaining a method of reading information from the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is an energy band diagram for explaining a method of erasing information “1” of the semiconductor memory device according to the first example of the present invention.

FIG. 6 is a graph showing voltage-current characteristics of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a time chart showing an information storage operation of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is an energy band diagram for explaining another mechanism of the method of writing information “1” of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is an energy band diagram for explaining another mechanism of the method of erasing information “1” of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a diagram showing a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 12 is a graph showing voltage-current characteristics of a semiconductor memory device according to a third example of the present invention.

FIG. 13 is a diagram showing a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 14 is an energy band diagram for explaining a method of writing information “1” in the semiconductor memory device according to the fourth example of the present invention.

FIG. 15 is an energy band diagram for explaining a method of reading information from the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 16 is an energy band diagram for explaining a method of erasing information “1” of the semiconductor memory device according to the fourth example of the present invention.

FIG. 17 is a diagram showing a semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 18 is a diagram showing a semiconductor memory device according to a sixth embodiment of the present invention.

FIG. 19 is a diagram showing a semiconductor memory device according to a seventh embodiment of the present invention.

FIG. 20 is an explanatory diagram of a specific example of the information storage method of the semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 21 is an explanatory diagram of a specific example of the information storage method of the semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 22 is an explanatory diagram of another specific example of the information storage method of the semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 23 is an explanatory diagram of another specific example of the information storage method of the semiconductor memory device according to the eighth embodiment of the present invention.

FIG. 24 is a diagram showing a semiconductor memory device according to a ninth embodiment of the present invention.

FIG. 25 is a process sectional view (1) showing the method for manufacturing the semiconductor memory device according to the ninth embodiment of the present invention.

FIG. 26 is a process sectional view (2) showing the method for manufacturing the semiconductor memory device according to the ninth embodiment of the present invention.

FIG. 27 is a process sectional view (3) showing the method of manufacturing the semiconductor memory device according to the ninth embodiment of the present invention.

FIG. 28 is a diagram showing a semiconductor memory device according to a tenth embodiment of the present invention.

[Explanation of Codes] 10 ... Semi-insulating InP substrate 12 ... Thick barrier layer 14 ... Floating conductive layer 16 ... Barrier layer 18 ... Channel layer 20 ... Thin barrier layer 22 ... Contact layer 22a ... n-In _0.53 Ga _0.47 As layer 23b ... n-In _0.53 Ga _0.47 As layer 24 ... First electrode 26 ... Second electrode 28 ... Two-dimensional electron channel 30 ... Resonant tunneling barrier layer 30a ... i-InAlAs barrier layer 30b ... i-InGaAs well layer 30c ... i-InAlAs barrier layer 32 ... i-In (AlxGa1- x) As barrier layer 34 ... superlattice barrier layers _{34a ... i-In 0.52 Al 0.48} As layer _{34b ... i-In 0.53 Ga 0.47} As layer 40 ... collector layer 42 ... barrier layer 44 ... Base extraction layer 46 ... Base layer 48 ... Emitter layer 50 ... Collector electrode 52 ... Base electrode 54 ... Emitter electrode _{60 ... n-In 0.53 Ga 0.47} As layer _{62 ... i-In 0.52 (AlxGa1} -x) 0.48 As layer 64 ... channel layer 66 ... thin barrier layer 68 ... contact layer 70 ... Source electrode 72 ... drain electrode 74 ... gate electrode 80 Oxide film 82 second electrode (bit line) 84 oxide film 86 first electrode (word line) 90 resist layer 92 resist layer 94 resist layer 100 semi-insulating InP substrate 102 buffer layer 104 Emitter layer 106 ... First electrode 108 ... Thin barrier layer 110 ... Channel layer 112 ... Second electrode 114 ... Thick barrier layer 116 ... Floating conductive layer 118 ... Barrier layer E1 ... First electrode E2 ... Second electrode WL1, WL2 ... , WL5 ... Word line BL1, BL2, ..., BL5 ... Bit line MC11, MC12, ..., MC54, MC55 ... Memory cell

─────────────────────────────────────────────―― ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G11C 16/02 H01L 27/115 7210-4M H01L 27/10 434

Claims (10)

[Claims] 1. A semiconductor substrate, an impurity-doped floating conductive layer formed on the semiconductor substrate, a non-doped barrier layer formed on the floating conductive layer, and a barrier layer formed on the barrier layer. A channel layer, a non-doped thin barrier layer formed on the channel layer, a conductive layer formed on the thin barrier layer, a first electrode formed on the conductive layer, and a channel layer on the channel layer And a second electrode formed on the semiconductor memory device. 2. A semiconductor substrate, a conductive layer formed on the semiconductor substrate, a non-doped thin barrier layer formed on the conductive layer, a channel layer formed on the thin barrier layer, A non-doped barrier layer formed on the channel layer, a floating conductive layer formed on the barrier layer and doped with impurities, a first electrode formed on the conductive layer, and a channel layer on the channel layer. And a formed second electrode. 3. The semiconductor memory device according to claim 1, wherein the barrier layer has a symmetrical barrier whose barrier height does not change. 4. The semiconductor memory device according to claim 1, wherein the barrier layer has an asymmetric barrier having a high barrier height on the channel layer side. 5. The semiconductor memory device according to claim 1, wherein the thin barrier layer has a resonant tunneling barrier. 6. A semiconductor substrate, a barrier layer formed on the semiconductor substrate for accumulating electrons, a channel layer formed on the barrier layer, and a non-doped thin barrier layer formed on the channel layer. And a conductive layer formed on the thin barrier layer, a first electrode formed on the conductive layer, and a second electrode formed on the channel layer. Storage device. 7. The semiconductor memory device according to claim 6, wherein the barrier layer is a superlattice layer having multiple quantum wells, and stores electrons in the multiple quantum wells. 8. The semiconductor memory device according to claim 1, wherein the thin barrier layer is a non-doped semiconductor layer, and the channel layer is a semiconductor layer doped with impurities. A characteristic semiconductor memory device. 9. The semiconductor memory device according to claim 1, wherein at least a portion of the thin barrier layer on the channel layer side is doped with impurities, and the channel layer is a non-doped semiconductor layer. A semiconductor memory device, wherein a two-dimensional electron channel is formed in the channel layer by electrons supplied from the thin barrier layer. 10. The method of storing information in a semiconductor memory device according to claim 1, wherein the second electrode has a higher potential than the first electrode. By applying a voltage, electrons are injected from the first electrode into the barrier layer and / or the floating conductive layer through the thin barrier layer to write information in the barrier layer and / or the floating conductive layer, The information stored in the floating conductive layer is read based on whether or not a current flows through the channel layer by applying a read bias voltage having a lower potential to the second electrode than the first electrode. By applying an erase bias voltage having a lower potential to the second electrode than the first electrode and having an absolute value larger than the read bias voltage, the second electrode can pass through the thin barrier layer from the first electrode. A method of storing information in a semiconductor memory device, characterized in that electrons stored in the barrier layer and / or the floating conductive layer are emitted to erase information.