JP3289961B2 - Circuit element constant measuring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring constants of circuit elements, and more specifically, to measuring synchronous constant rectification and a reference signal in measurement of LCR, etc., and to measure constants (parameters) of circuit elements from two AC signals. ) Can be obtained.

[0002]

2. Description of the Related Art Japanese Patent Publication No. 2-35949 discloses a vector voltage ratio measuring device capable of measuring a vector voltage ratio and a phase difference between two AC signals by digital processing.

[0003] The apparatus will be schematically described with reference to a vector diagram of FIG. First, one cycle of each of two AC signals Ea and Eb having the same frequency is sampled and held at time intervals equal to N, and the A / D conversion circuit converts the data into digital data Eai and Ebi (i = Ebi). 1 to N)
Convert to

Here, assuming that the phase difference between the AC signal Ea and a reference vector of Eb is α and β, respectively, the vector voltage ratio to be obtained is (Eb / Ea) · cos (β−
α) and (Eb / Ea) · sin (β-α).

An AC signal E corresponding to a reference vector
If the in-phase components of a and Eb are Eax and Ebx, and the quadrature components are Eay and Eby, (Eb / Ea) · cos (β−α) = (Eax · Ebx + Eay · Eby) / (Eax ² + Eay ² ) (Eb / Ea) · sin (β−α) = (Eax · Eby−Eay · Ebx) / (Eax ² + Eay ² ). The in-phase components Eax and Ebx and the quadrature components Eay and Eby are obtained by the following equations. ^{_{Eax = i = 1 Σ N Eai}} · Acos (2πi / N + θ) Eay = i = 1 Σ N Eai · Asin (2πi / N + θ) Ebx = i = 1 Σ N Ebi · Acos (2πi / N + θ) Eby = i = 1 Σ ^N Ebi · Asin (2πi / N + θ)

[0006]

According to this, synchronous rectification can be equivalently performed on a calculation basis.
Although the circuit configuration is simple and high-speed processing is possible, it has the following disadvantages.

That is, since the in-phase components Eax and Ebx and the quadrature components Eay and Eby are calculated using trigonometric functions, it is necessary to prepare numerical tables for sin and cos.

[0008] Even if the calculation is performed, it takes time to read the numerical value from the same table each time. Further, this conventional device also requires a third AC signal as a reference vector.

[0009]

According to the present invention, at least one cycle of an AC voltage V applied to a device under test and an AC current I detected through the device under test is specified. voltage data V _i and the current data I _i of N each simultaneously sampled at the time interval
(I = 1 to N) and the A / D converter circuit for converting, these voltage data V _i and the current data I _i variable is the mean effective power component from A _R, the average is reactive power component variable A
_X and a divisor variable H, and arithmetic processing means for executing arithmetic operations A _R / H and A _X / H to obtain at least the effective resistance R and the reactance X of the device under test. processing means, the variable A _R the voltage data V _i and the current data I _i for
Calculated based on the following equation (1) from, for the variable _{A X} is divided into the N voltage data _{V i} and _(V 1 _{~V N / 4)} and _{(V N / 4} + 1 ~V _N) phase Is virtually 90
° determined based on the following formula (2) and the current data I _i as different causes data sorted, the divisor variable H is characterized by obtaining, based on the following equation (3) by the current data I _i.

(Equation 4)

(Equation 5)

(Equation 6)

In this case, data sampling and A /
The D conversion is performed by PLL (Phase-Locked-Loo).
It is preferable that the input signal is controlled synchronously by the p) circuit, whereby N data are always obtained even if the input signal changes.

The following parameters are further obtained from the effective resistance R and the reactance X. Angular velocity is ω
Then, the capacitor component C is obtained from 1 / ωX. Further, the inductance component L is obtained from X / ω. A loss coefficient D is obtained from R / X, and tan ^-1 X
/ R determines the phase difference θ.

[0012]

[Action] The CPU N digital voltage data _V i, electrostatic
From the flow data _Ii , the variable _AR

(Equation 7) Is calculated. This corresponds to the average active power component. That is, assuming that a sine wave voltage applied to the device under test is v and a sine wave current flowing through the device under test is i, v = Vmsin (ωt−ψ) = 2 ^1/2 | V | sin (ωt−ψ) ) I = Imsin (ωt−ψ−θ) = 2 ^1/2 | I | sin (ωt−ψ−θ) Vm and Im are maximum values, | V | and | I | are effective values of voltage and current, θ is a phase difference between voltage and current, and ψ is an arbitrary phase. Here, when the instantaneous active power P is obtained, P = | V || I | {cos θ-cos (2ωt−2−−θ)}, and the average active power Pa is Pa = (VmIm / 2) cos θ = | V || I | cos θ (a) Here, in the vector diagram of FIG. 4, assuming that the effective resistance component of the device under test is R and the reactance component is X, cos θ in equation (a) represents a power factor, so that cos θ = R /
(R ² + X ² ) ^1/2 . Therefore, Pa = | V ||| I | cos θ = | V | · | I | · R / (R ² + X ² ) ^1/2 where | Z | = (R ² + X ² ) ^1/2 = | V | / | I
| And therefore | V | = | I | × (R ² + X ² ) ^1/2
Since it is, Pa = ^{| I |} is 2 · R ...... (b), which is equivalent to _{A R.}

Next, in order to calculate the reactive power component, a virtual signal v 'having the same frequency and having a phase shifted by 90 ° from the sine wave voltage v is obtained. This, N pieces of data V _i sampled from a sine wave voltage v is used.

[0014] In the waveform diagram of FIG. 3, if that data V _i of 1~N along its time axis in one period of the voltage v is sampled, the phase 90 ° shifted signal v '1 in the period will be data _{V i} of up to N / 4 + 1~ (N + N / 4) is sampled.

Here, data 1 to N / 4 of the signal v,
Since the data of N + 1 to (N + N / 4) of the signal v 'is equal, the data of N / 4 + 1 to N and the data of 1 to N / 4 can be converted into the data of the signal v' having a phase shift of 90 °. By the data V _i and I _{i of the} virtual signal v ′,
The variable _AX is calculated.

(Equation 8) According to this, the data I _i has a phase of 90 ° more than that.
(N / 4 by the order of the data) deviation are data V _i
Will be multiplied.

[0016] The same variable _{A X} corresponds to an average reactive power. That is, the signal v 'whose phase is shifted by 90 ° is represented by v' = Vmsin (ωt−ψ−π / 2). Therefore, as described above, the reactive instantaneous power P 'is P' = | V || I | {sin θ-sin (2ωt−2｝ −θ)}, so that the average reactive power Pb is Pb = (VmIm / 2) sin θ = | V || I | sin θ (c) Here, since sin θ = X / (R ² + X ² ) ^1/2 and | V | = | I | × (R ² + X ² ) ^1/2 , Pb = | I | ² · X (d) ), which is equivalent to the variable _{a X.}

Therefore, the effective resistance R
The _A R / ^| I | sought at ^2, also, reactance
X is obtained by A _X / | I | ² from equation (d).

By the way, | I | ² = (Im / 2 ^1/2 )
² = because it is ^Im 2/2, to determine this from the data _{I i,}

(Equation 9) The following operation is performed, and the variable name H is given to this.

Therefore, the effective resistance R is obtained from A _R / H, and the reactance X is obtained from A _X / H. Then, the resistance value, the capacitor component, the inductance component, the loss coefficient, the quality, the impedance, the phase difference, and the like are obtained from R and X.

[0020]

Embodiments of the present invention will be described below. FIG. 1 shows a schematic block diagram of a constant device for this circuit element. According to this, the device has two sample-and-hold circuits 11 and 12.

In this case, as illustrated in FIG.
One of the sample-hold circuit 11 obtains the N data AV _i by sampling one cycle of the voltage V applied between both terminals of the device under test at a predetermined time interval. Similarly, the other sample-and-hold circuit 12 obtains the N data AI _i by sampling one cycle of the current flowing through the device under test at a predetermined time interval. These samplings are performed simultaneously.

These data AV _i and AI _i are stored in the next stage A
The digital data V _i , I _i (i
= 1 to N), and the CPU 1 as an arithmetic processing means
4 given.

The CPU 14 calculates the active average power A _R , the reactive average power _AX and the variable H from the data V _i and I _i . First of all, when determining the _{A R,}

(Equation 10) Is performed. Then, although the A _X is obtained, in this case, the phase data of the virtual voltage V 'of different identical frequency is made for the same voltage V from the data V _i of the voltage V.

That is, as illustrated in FIG.
If along the data sampled one period of the voltage V to the time axis and V ₁ ~V _N, data phase is sampled one period of the voltage V 'which are shifted 90 ° in V
_{N / 4 + 1 to} VN _{+ N / 4. In} this case, the data of VN _{+ 1 to} VN _{+ N / 4} of the voltage V ′ is the voltage V
Equal up of _V 1 _{~V N / 4} data. Therefore,

[Equation 11] By performing becomes operational, 90 ° voltage data V _i whose phase is shifted is to be multiplied with respect to the current data I _i. Then, only the current data _Ii is used as the variable H,

(Equation 12) Obtains the variable H.

Then, the effective resistance R is calculated by A _R / H, and the reactance _X is calculated by A _X / H. Then, other parameters are obtained as necessary from the effective resistance R and the reluctance X.

That is, a resistance value R = R, a capacitor component C = 1 / ωX (ω is an angular velocity), and an inductance component L =
X / ω, loss coefficient D = R / X, quality Q = X /
Each parameter such as R, phase difference θ = tan ⁻¹ 1 / D is obtained. These parameters are displayed on display 1
5 and supplied to other circuits via the output circuit 16.

FIG. 5 shows that the input signal V
2 shows an example in which the sampling frequency and the A / D conversion are synchronized with respect to. That is, by controlling the sampling frequency in a constant proportional relation to the frequency of the input signal, N data can be always obtained even if the frequency of the input signal changes.

In the above embodiment, N data is sampled from one cycle of the input signals V and I, but the sampling cycle may be M cycles (an integer of 2 or more).

Whether the sample and hold circuits 11 and 12 are provided separately from the A / D conversion circuit 13 as in the above embodiment depends on the type of the A / D conversion circuit used and its conversion speed.

[0030]

As described above, according to the present invention,
There is no need for a table of sin or cos to determine the constants of the circuit elements. In addition, a third reference vector
Is unnecessary.

That is, according to the present invention, the operation is performed directly using N digital data V _i and I _i sampled from one cycle of two signals, so that the configuration is further simplified and Accordingly, the arithmetic processing speed can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram according to one embodiment of the present invention.

FIG. 2 is a waveform diagram showing two signal waveforms to be measured.

FIG. 3 is an explanatory diagram for explaining a method of creating virtual signal data having a phase difference of 90 °;

FIG. 4 is a vector diagram used for understanding the present invention.

FIG. 5 is a schematic block diagram according to another embodiment of the present invention.

FIG. 6 is a vector diagram for explaining a conventional example.

[Explanation of symbols]

 11, 12 sample and hold circuit 13 A / D conversion circuit 14 CPU 17 PLL circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-52-26257 (JP, A) JP-A-3-92770 (JP, A) JP-B-2-35949 (JP, B2) (58) Field (Int.Cl. ⁷ , DB name) G01R 27/02 G01R 27/26

Claims (1)

(57) [Claims] At least one cycle of an AC voltage V applied to a device under test and an AC current I detected through the device under test is simultaneously sampled at predetermined time intervals, and each of the samples is N samples. Voltage data V _i and current data I _i
An A / D converter circuit for converting (i = 1 to N) and the variables _{A X} and a variable _{A R,} the average reactive power component is the average effective power component from these voltage data _{V i} and the current data _{I i} While calculating the divisor variable H, A _R /
Running becomes H and A _{X /} H operations and an arithmetic processing means for obtaining the effective resistance component R and reactance X of at least the measuring device, the processing means, the voltage for the variable A _R formula from the data _{V i} and the current data _{I i} (1)
Based on the calculated, for the variable _{A X} is the N voltage data _{V i} and _{(V 1 ~V N / 4)} (V N / 4 + 1 ~
Calculated based on the following formula (2) and the current data I _i as data sorted which has virtually different 90 ° phase divided into V _N) and, following by the current data I _i for the divisor variable H A circuit element constant measuring device, which is obtained based on (3). (Equation 1) (Equation 2) (Equation 3)