JP3289616B2 - Explosive element ignition device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for decoding a coded expansion signal to drive an ignition device, thereby obtaining a C signal.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a detonating element ignition device that prevents runaway of a PU or noise due to noise.

[0002]

2. Description of the Related Art The importance of the role of an airbag system as an occupant restraint for protecting a vehicle occupant from an impact in a collision has been recognized, and the occupant is protected not only from a frontal collision accident but also from a side collision accident. To be able to do so, vehicles equipped with both frontal airbags and side airbags are becoming widespread. Both frontal airbags and side airbags use the same principle as the squib, in which the squib is deployed as a deployment trigger for the airbag. Is basically the same in configuration as the ignition circuit for causing ignition and detonation.

A detonating element ignition device 1 shown in FIG. 4 computes an acceleration signal detected by an acceleration sensor 2 to determine a threshold value to determine a collision, and a detonating switching element that conducts according to a deployment signal from the CPU 3. And an explosion element 5 that receives the conduction of the ignition switching element in the ignition device 4 and is energized by an ignition current to explode. The air bag is triggered by the explosion energy of the explosion element 5. It is configured to be deployed and driven. The CPU 3 logically determines the threshold value determination output of the absolute value of the acceleration signal and the threshold value determination output of the interval integral value, and has a function of conducting the detonation switching element in the ignition device 4 with the output of the logic gate.

[0004]

SUMMARY OF THE INVENTION A detonating element ignition device comprises:
When the CPU 3 goes out of control, the deployment signal is given to the detonation switching element in the ignition device 4 although the detonation element 5 does not normally need to be detonated, and the detonation element 5 explodes. There is fear.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and has a device for igniting a detonating element which decodes a coded expansion signal and drives an igniting device to prevent runaway of CPU and explosion due to noise. The purpose is to provide.

[0006]

In order to achieve the above object, the present invention provides a collision judging means for judging a collision and generating an expansion signal coded according to a predetermined code; A decoder that receives an expansion signal, decodes the expansion signal and issues an ignition signal, and an ignition device that operates by the ignition signal supplied from the decoder and energizes and detonates the detonating element. It is.

Further, according to the present invention, the collision judging means generates the expansion signal as a plurality of bits of serial data having a predetermined bit arrangement, and the decoder comprises:
A shift register for holding the plurality of bits of the expanded signal, and a shift output of the shift register logically determined for all bits, and a logical determination signal is output only when the received expanded signal matches the predetermined bit arrangement. It is characterized by comprising a logic circuit and output means for amplifying a logic determination signal of the logic circuit and outputting the signal as the ignition signal. Furthermore, the collision determination means outputs 2n-bit serial data in which the first half n bits and the second half n bits have a polarity inversion relation as the expansion signal, and the collision determination means outputs the plurality of bits of the expansion signal. Externally supplies two series of mutually synchronized clock signals, the decoder monitors the phase shift of the two series of clock signals, and when a phase shift of a certain width or more occurs,
Another feature is to reset the shift register.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a schematic configuration diagram showing one embodiment of a detonating element ignition device of the present invention,
FIG. 2 is a circuit diagram showing a specific configuration of the decoder shown in FIG. 1, and FIG. 3 is a signal waveform diagram of each section of the decoder shown in FIG.

The explosive element ignition device 11 shown in FIG. 1 calculates a collision signal by calculating an acceleration signal from an acceleration sensor 12 and generates a deployment signal coded according to a predetermined code. It comprises a decoder 20 which receives a deployment signal from the CPU 13 and decodes the deployment signal to generate an ignition signal, and an ignition device 14 for energizing and initiating the initiating element 15 by the output of the decoder 20.

The CPU 13 receives the acceleration signal output from the acceleration sensor 12, makes a logical determination on the threshold value determination output of the absolute value of the acceleration signal and the threshold value determination output of the interval integral value, and outputs a development signal with the output of the logic gate. . As the expanded signal, 8-bit serial data having a predetermined array whose bit array is specified in advance, that is, a bit array of "10010110" is used. Two series of mutually synchronized clock signals CLK1 and CLK1 attached to the expanded signal are used. 2 is C
The PU 13 outputs one serial data, that is, eight clocks. As the expansion signal, in principle, serial data of even-numbered bits is used.
“001” and the latter four bits “0110” use 8-bit serial data having a polarity inversion relationship. this is,
Even if a pseudo-expansion signal with a bit arrangement similar to the expansion signal is accidentally generated due to electromagnetic wave interference, such pseudo-expansion signal is irregular noise, and the regularity is such that the bit arrangement in the first and second half has a polarity inversion relationship. And is based on an empirical rule that the probability of coincidence with a normal expansion signal, even if accidentally, is almost zero.

The decoder 20 determines whether or not the expanded signal has a predetermined bit arrangement. The decoder 20 stores the expanded signal consisting of 8-bit serial data and the shift output of the shift register 21 as a whole. A logic circuit 22 that performs bit logic determination and outputs a logic determination signal only when a specific combination of bit arrays is obtained, and a pre-driver 23 that amplifies the logic determination signal of the logic circuit 22 and outputs an ignition signal Be composed. Shift register 2
1 can use a single 8-bit output type,
Here, a 4-bit output type shift register 21a, 21
b are connected in tandem. The first shift register 21a includes a data input terminal D to which coded data from the CPU 13 is supplied, and a clock input terminal CLK to which a first clock signal CLK1 is supplied from the CPU 13.
And a reset input terminal R to which a reset signal from a reset circuit 24 to be described later is supplied, and bit output terminals Q0 to Q0 to 3rd-stage shift signals.
It has Q3. Also, the second shift register 21b
A data input terminal D to which a bit output is supplied from a bit output terminal Q3 of the first shift register 21a;
3, a clock input terminal CLK to which the first clock signal CLK1 is supplied, a reset input terminal R to which the reset signal from the reset circuit 24 is supplied, and a fourth to seventh shift signals. It has bit output terminals Q4 to Q7.

The logic circuit 22 logically determines the coded data of the bit array "10010110", and outputs the data from the bit output terminals Q7 to Q0 of the shift registers 21a and 21b. Is output when a bit output of the combination is obtained. More specifically, an AND gate 22a for performing an AND operation on four bits “1” and a NOR gate 22b for performing a NOR operation on four bits “0”
And an AND gate 22c that calculates the logical product of the outputs of the AND gate 22a and the NOR gate 22b. That is, the AND gate 22a is connected to the bit output terminals Q1,
The logical product of the bit outputs of Q2, Q4 and Q7 is taken, and NOR gate 22b is connected to bit output terminals Q0, Q3, Q5 and Q6.
OR the bit outputs of

The pre-driver 23 comprises a common emitter transistor 23a receiving the output of the AND gate 22c in the logic circuit 22 at a base, and a buffer amplifier 23b for amplifying and extracting the collector output of the transistor 23a. Rb is the base resistance of the transistor 23a, and Rbe is the base-emitter resistance of the transistor 23a. When the transistor 23a receives a high-active logic determination signal from the AND gate 22c and conducts, the collector potential decreases, and a low-active ignition signal is applied from the buffer amplifier 23b to the detonation switching element in the ignition device 14. .

The reset circuit 24 monitors the phase shift between the two clock signals CLK1 and CLK2 output from the CPU 13 in phase. When a phase shift occurs between the clock signals CLK1 and CLK2, the CPU 13 runs away. The reset signal is supplied to the reset input terminals of the shift registers 21a and 21b. Specifically, an exclusive OR gate 2 that performs an exclusive OR operation on the clock signals CLK1 and CLK2 and outputs a phase difference signal between the two clock signals
4a and an integrating circuit 24b for integrating the output of the exclusive OR gate 24a. The integration circuit 24b
It consists of a time constant circuit consisting of a resistor R and a capacitor C,
The terminal voltage of the capacitor C is extracted from the connection point between the resistor R and the capacitor C, and is supplied to the reset input terminals R of the shift registers 21a and 21b. Shift registers 21a, 2
A minimum operation voltage is specified for the reset input 1b, and a reset signal less than the minimum operation voltage is not accepted. Therefore, the clock signal CLK1
Even if a phase shift occurs between the clock signal and CLK2, if the phase shift is less than the allowable range, the output signal width of the exclusive OR gate 24a is also ignored, and the terminal voltage of the capacitor C exceeds the minimum operating voltage. There is no runaway judgment.

Here, when the CPU 13 makes a collision determination,
A development signal having the bit array “10010110” is sent from the CPU 13 to the decoder 20. This 8
The bit serial data is provided by a first clock signal CLK.
1 and is taken in from the data input terminal D of the shift register 21a at the rise of the first clock signal CLK.
Shift registers 21a and 21b at the rise of 1
Is sequentially shifted. When all the 8-bit serial data is taken into the shift registers 21a and 21b in this manner, the clock signals CLK1 and CLK2 disappear, and as shown by the dotted lines in FIGS.
Bit output terminals Q0 of shift registers 21a and 21b
From Q7, Is obtained, and this output state is maintained. That is, the clock signals CLK1 and CL
As long as K2 is not overshot, the same bit output state is maintained.

Thus, the shift registers 21a, 21b
"01101001" to the bit output terminals Q0 to Q7 of
When all the bit outputs are obtained, the output of the AND gate 22a for determining the logical product of the bit "1" and the output of the NOR gate 22b for determining the logical OR of the bit "0" both become logical "1", and the outputs of the AND gate 22a and the NOR gate 22b are determined. The output of the AND gate 22c that takes the logical product of the outputs also becomes logic "1". The output of the AND gate 22c is the pre-driver 2
3 is applied to the base of the transistor 23a, and the transistor 23a conducts. As a result, the buffer amplifier 2
The output level of 3b decreases, a low active ignition signal is supplied to the ignition device 14, and an ignition current flows through the ignition device 15 with the conduction of the switching device for ignition.
When the detonating element 15 is ignited and detonated by the application of the ignition current,
The airbag is deployed with the firing energy at this time as a trigger.

When a phase shift between the clock signals CLK1 and CLK2 exceeding an allowable range occurs, an exclusive OR gate 24a that performs an exclusive OR process on the clock signals CLK1 and CLK2 outputs a phase difference signal between the two clock signals. When the output of the integration circuit 24b exceeds the minimum operating voltage set at the reset input terminal R of the shift registers 21a and 21b, the CPU 1
3 is determined to have run away, and shift registers 21a,
All the bit outputs output from the bit output terminal 21b are reset. Also, the bit array “1001”
While the CPU 13 is sending the expansion signal “0110” to the decoder 20, the CPU 13 causes a runaway, and the false expansion signal different from the normal bit arrangement is held in the shift registers 21 a and 21 b in the decoder 20. In this case, no logic determination signal is obtained from the logic circuit 22, and the pre-driver 23 does not operate.

As described above, the explosive element ignition device 11
The CPU 13 that determines the collision generates an expansion signal coded according to a predetermined code, and the decoder 20 that has received the expansion signal decodes the expansion signal to generate an ignition signal, and the ignition device 14 that operates based on the ignition signal But,
Since the detonating element 15 is configured to be energized and detonated, unlike the conventional apparatus in which the ignition device is directly driven by a simple deployment signal such as a bit “1” or “0”, the coded deployment signal is decoded by the decoder 20. Since the ignition device 14 is driven by the ignition signal obtained by decoding in the above, it is possible that the ignition device 14 malfunctions due to extraneous noise, or that the ignition device 14 malfunctions due to runaway of the CPU 13 itself. In addition, the explosion of the detonating element due to the electromagnetic wave disturbance or the runaway can be reliably eliminated.

Further, the CPU 13 generates an expansion signal as 8-bit serial data having a predetermined bit arrangement, and this expansion signal is held by the shift register 21 in the decoder 20, and the shift output of the shift register 21 is output. The logic circuit 22 makes a logical decision on all bits, outputs a logical decision signal only when the received expansion signal matches the predetermined bit arrangement, and outputs a pre-driver 23 which amplifies the logical decision signal as an ignition signal. With this configuration, the decoder 20 determines whether the 8-bit bit array output as serial data is a predetermined bit array.
Can be reliably determined by the shift register 21 and the logic circuit 22. Since the serial signal of 8 bits is used as the expansion signal, a specific one of 2 8 power combinations considered as the expansion signal can be used. By discriminating only the signal having the bit array as the expansion signal, the probability of malfunction can be reduced to 1/256 even if it is simply estimated, thereby preventing the explosion of the detonating element 15 due to electromagnetic wave disturbance or runaway. It can be reliably eliminated.

Further, since the CPU 13 is configured to output 8-bit serial data in which the first 4 bits and the latter 4 bits have a polarity inversion relationship as a development signal, the CPU 13 specifies from among 256 combinations considered as the development signal. Since only the signal having the bit arrangement of the above is used as a development signal, and the arrangement is a special form of bit arrangement in which the first 4 bits and the latter 4 bits have a polarity inversion relationship, it is supposed that the expansion signal is accidentally generated due to electromagnetic interference. Even if a pseudo-expansion signal of a similar bit array is generated, such a pseudo-expansion signal is irregular noise, which is far from the regularity that the first and second bit arrays have a polarity inversion relationship. There is almost no danger that a deployment signal will be generated due to an electromagnetic wave disturbance or runaway of the CPU 13.
Can be reliably eliminated.

Further, the CPU 13 supplies two series of mutually synchronized clock signals CLK to the 8-bit expansion signal.
1 and 2 are supplied externally, and the decoder 20 monitors the phase shift of the two series of clock signals CLK1 and CLK2, and resets the shift register 21 when a phase shift of a certain width or more occurs. 2 that CPU13 has runaway
The determination can be made based on the phase shift of the series clock signal, and the explosion of the detonating element due to the explosion of the CPU 13 can be more reliably prevented.

In the above embodiment, the CPU 13 uses the two clock signals CLK attached to the coded expansion signal.
Although the configuration has been described in which output of 1 and 2 is performed, a configuration in which the CPU 13 outputs coded data of start-stop synchronization type may be employed. In that case, it is possible to use no clock signal. However, in the case of start-stop synchronization, it is necessary to add header data to the head of the coded data,
It should also be noted that as the number of bits of the serial data used as the expansion signal increases, the risk of misreading in the decoder increases.

[0023]

As described above, according to the present invention,
Collision determination means for determining a collision generates an expansion signal coded according to a predetermined code, and a decoder that receives the expansion signal decodes the expansion signal to generate an ignition signal, and an ignition device that operates based on the ignition signal, Unlike the conventional device that drives the ignition device directly with a simple deployment signal such as "1" or "0" of a bit, the coded deployment signal is decoded by a decoder because the firing device is configured to energize the device. Since the ignition device is driven by the ignition signal obtained by decoding, the ignition device does not malfunction due to external noise, or the ignition device does not malfunction due to the runaway of the collision determination means itself. An excellent effect is obtained such that the explosion of the detonating element due to an obstacle or a runaway can be reliably eliminated.

Further, the collision judging means generates the expansion signal as a plurality of bits of serial data having a predetermined bit arrangement, and a decoder holds a shift register holding the plurality of bits of the expansion signal; A logic circuit that performs a logical decision on the shift output of all bits and outputs a logical decision signal only when the received expansion signal matches the predetermined bit arrangement, and amplifies the logical decision signal of the logic circuit, Output means for outputting as an ignition signal, the shift register and the logic circuit in the decoder can determine whether or not the bit arrangement of a plurality of bits outputted as serial data is a predetermined bit arrangement. When 2n serial data bits are used as the development signal, 2 @ 2 powers considered as the development signal By discriminating only a signal having a specific bit arrangement from among the combinations as the expansion signal, it is possible to reduce the probability of malfunction by a factor of 2 2n even if it is simply estimated. This has the effect that the explosion of the detonating element due to the runaway can be reliably eliminated.

Further, since the collision determining means is configured to output 2n-bit serial data in which the first n bits and the second half n bits have a polarity inversion relationship as the expansion signal, 2n 2n considered as the expansion signal can be considered. Only a signal having a specific bit arrangement from the combinations of the powers is used as a developed signal, and the arrangement is composed of n bits in the first half and n in the second half.
Because the bit is a special form of bit arrangement that has a polarity inversion relationship, even if a pseudo-expansion signal of a bit arrangement similar to the expansion signal is accidentally generated due to electromagnetic interference,
Such a pseudo-expansion signal is irregular noise, which is far from the regularity in which the bit arrangement in the first and second half is in a polarity inversion relationship. Therefore, the expansion signal is generated by an electromagnetic wave disturbance or runaway of the collision determination means. There is almost no danger that the explosion of the detonating element can be reliably eliminated.

The collision determining means externally supplies two series of mutually synchronized clock signals attached to the plurality of bits of the expanded signal, and the decoder monitors a phase shift between the two series of clock signals. The configuration is such that the shift register is reset when a phase shift of a certain width or more occurs, so that the runaway of the collision determination means can be determined based on the phase shift of the two series of clock signals. There is an effect that the explosion of the detonating element based on the explosion can be more reliably prevented.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of a detonating element ignition device of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a decoder shown in FIG.

FIG. 3 is a signal waveform diagram of each section of the decoder shown in FIG. 2;

FIG. 4 is a schematic configuration diagram showing an example of a conventional explosive element ignition device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Explosive element ignition device 12 Acceleration sensor 13 Collision determination means (CPU) 14 Ignition device 15 Explosive element 20 Decoder 21 21, 21a, 21b Shift register 22 Logic circuit 22a, 22c AND gate 22b OR gate 23 Output means (predriver) 23a Transistor 23b Buffer amplifier 24 Reset circuit 24a Exclusive OR gate 24b Integration circuit

Claims (2)

(57) [Claims] 1. A method for determining a collision and determining a bit arrangement specified in advance.
Multi-bit serial data with columns
2n bits in which n bits and the latter half n bits have a polarity inversion relationship
Collision determination means for generating serial data of the bit as a development signal, and before receiving the development signal supplied from the collision determination means,
A shift register for holding a development signal;
All bits are logically judged for the shift output of the
If the signal matches the previously specified bit sequence,
And a logic circuit for outputting a logic decision signal.
Output means for amplifying the logical judgment signal and outputting it as an ignition signal
And an ignition device that operates according to an ignition signal supplied from the decoder and energizes and detonates the detonating element. Wherein said collision judging means, a clock signal synchronized with each other two series incidental to prior Symbol deployment signal externally supplied, the decoder monitors the phase shift of the clock signal of the two series, a constant width When the above phase shift occurs, a reset circuit for resetting the shift register is further provided.
The igniting element ignition device according to claim 1, further comprising: