JP3289181B2 - DC / AC converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main pulsating wave corresponding to a substantially sinusoidal full-wave rectified waveform by switching supplied DC power, temporarily converting the DC power into AC power, rectifying and smoothing the AC power. DC / AC that generates a signal and alternately inverts the polarity of the main pulsating wave signal every cycle to generate AC power
The present invention relates to a conversion device.

[0002]

2. Description of the Related Art FIG. 19 shows a conventional ringer circuit. This ringer circuit is composed of two elements, a DC / DC converter and an amplifier. The DC / DC converter includes a transformer T21, a semiconductor switch M21, rectifier diodes D22 to D23, and smoothing capacitors C22 to C22.
24, a resistor R23, a power control circuit PSC, and an input capacitor C21.

The power supply control circuit PSC outputs a high-frequency pulse having a duty ratio (ratio of a pulse width time to a cycle) according to a control voltage VSI applied to an input terminal SI to an output terminal D.
An output from R drives the semiconductor switch M21. As a result, between the drain terminal and the source terminal of the semiconductor switch M21, ON and OFF are repeated at the cycle of the high frequency pulse, and the voltage VS applied to the input terminal SI is applied.
In accordance with the level of I, the switch operates as a switch in which the ratio between the ON period and the cycle, that is, the duty ratio changes.

Here, the first winding L2 of the transformer T21
1 and the semiconductor switch M21 are connected in series and connected to the DC power supply Ei via the power supply terminals IPN and ING, so that the first winding L21 of the transformer T21 has a high frequency by the on / off operation of the semiconductor switch M21. Pulse voltage is applied.

Therefore, the second winding L22 and the third winding L
23, the fourth winding L24 generates a pulse voltage having a magnitude corresponding to the turn ratio between each winding and the first winding L21, and the pulse voltage generated in each winding is a diode voltage. D21, D22 and D23 respectively rectify and further charge the smoothing capacitors C22, C23 and C24, respectively, to generate DC voltages of the positive voltage VSP, the negative voltage VSN and the control voltage VSI. Smoothing capacitor C2
The voltage VSI charged to 4 is applied to the input terminal SI of the power supply control circuit PSC.

When the voltage of the DC power supply Ei changes, the voltages VSP, VSN, and VSI also change.
Is increased, the power supply control circuit PSC reduces the duty ratio of the semiconductor switch M21 to control the voltage VSI to decrease. Conversely, when the voltage VSI decreases, the duty ratio of the semiconductor switch M21 is increased to control the voltage VSI to increase.

[0007] At this time, the duty ratio of the pulse voltage generated in the second winding L22 and the third winding L23 has the same effect. Therefore, even if there is a voltage fluctuation of the DC power supply Ei, rectification and smoothing are performed. The applied voltages VSP and VSN are kept substantially constant. The positive voltage VSP stabilized in this manner is supplied to the positive power terminal VP of the amplifier RGA, and the negative voltage VSN is supplied to the negative power terminal VN of the amplifier RGA.

The amplifying section includes a sine wave signal source SG having a frequency of about 16 Hz, an amplifier RGA, an input resistor R21 connected between the sine wave signal source SG and the negative input terminal II of the amplifier RGA, and a negative electrode of the amplifier RGA. It comprises a feedback resistor R22 connected between the input terminal II and the output terminal OUT. Input resistor R21 and feedback resistor R22
Is an element for using the amplifier RGA as a negative feedback amplifier circuit. Since the voltage gain is determined by the ratio between the feedback resistor R22 and the input resistor R21, the sine wave signal can be set by appropriately setting this voltage gain. The sine wave signal of the source SG is used as a ringing signal and the effective voltage VRG is approximately 80
V AC signal can be formed.

This amplifier RGA is configured, for example, as shown in FIG. That is, the constant current source IB31,
A differential input circuit formed by PNP transistors Q31 and Q32, a current mirror circuit formed by NPN transistors Q33 and Q34, an NPN transistor Q35 forming an amplifier circuit, a constant current source IB32, bias diodes D31 and D32, and an NPN transistor Q36, PN
It comprises an output circuit formed by a P transistor Q37.

The differential input circuit and the Karen Miller circuit are PN
A voltage corresponding to the difference between the voltages applied to the base terminals of the P transistors Q31 and Q32, that is, the negative input terminal II and the positive input terminal NI, is output from the collector terminal of the NPN transistor Q34, and is applied to the base terminal of the amplifier NPN transistor Q35. The NPN transistor Q35
, A differential voltage between the voltages applied to the positive input terminal NI and the negative input terminal II is amplified and appears to the output circuit.

The NPN transistor Q3 of this output circuit
6. The PNP transistor Q37 both functions as an emitter follower and is used to lower the output impedance. Diodes D31 and D32 are constant current sources IB
By applying a voltage drop caused by the flow of the current of 32 between the base terminal and the emitter terminal of the NPN transistor Q36 and the PNP transistor Q37, the occurrence of crossover distortion is suppressed. Thus, this amplifier RGA
Amplifies the difference voltage between the voltages applied to the positive input terminal NI and the negative input terminal II and guides the amplified voltage to the output terminal OUT.

The maximum amplitude voltage that can be formed when the amplifier RGA is used is determined by the voltages VSP and VSN applied to the power supply terminals VP and VN of the amplifier RGA and the output circuit configuration of the amplifier RGA. In the case of the amplifier of FIG. 20, the voltage drop of the output circuit is caused by the base-emitter voltage of the NPN transistor Q36 and the PNP transistor Q37 (approximately 0.7
V), the maximum amplitude is (VSP-0.7V)
（(VSN + 0.7 V).

Accordingly, assuming that the effective voltage of the ringing signal is VRG as shown in FIG. 21, the absolute value voltage VSA between the output voltages VSP and VSN of the DC / DC converter is obtained.
VAS ≧ 1.414VRG + 0.7V (1) is set to, for example, 114V. Conventionally, the power of the DC power supply Ei is thus converted into AC power as a low-frequency ringing signal.

[0014]

However, the prior art mainly has (a) a large power consumption at no load,
(B) There is a problem that power conversion efficiency is low. Hereinafter, each problem will be specifically described.

Regarding (a): In order to reduce the crossover distortion of the output signal, the amplifier RGA has the NP of the output circuit.
A voltage formed by using diodes D31 and D32 is applied between the base and the emitter of the N transistor Q36 and the PNP transistor Q37. Therefore, a constant bias current always flows through these transistors. Since this bias current is, for example, 1 mA or more, even when the load RL is not connected between the output terminals RGP and RGG, the bias current is always 0.228 W (the positive power supply terminal VP and the negative power supply terminal of the amplifier RGA). (For example, when 228 V is applied) between V.sub.N and V.sub.N.

On the other hand, the conversion efficiency of the DC / DC converter section is designed to be approximately maximum at the rated output, and is approximately 80%.
%. However, at light load, for example, 1
The conversion efficiency in the case of about 0% is as low as about 20%. Therefore, the conventional ringer circuit has about 1 W even when there is no load.
Consumes about power.

The cause of such a decrease in the conversion efficiency of the DC / DC converter under a light load is that the power supply terminals VP and VN
To keep the voltage of the winding L2 of the transformer T21 constant.
2. This is because the peak value of the pulse power generated in L23 is substantially constant regardless of the duty ratio of the main switch M21. That is, the charging energy for the parasitic capacitance around the transformer T21, including the output capacitance of the main switch M21, is substantially constant, and most of the energy is consumed by the main switch M2 when the main switch M21 is turned on. This power becomes the fixed power consumption of the DC / DC converter together with the power consumption of the power supply control circuit PSC, and becomes a factor for lowering the conversion efficiency under light load.

Regarding (b): output terminals RGP, RGG
When a resistor RL having a resistance value of RL is connected therebetween, a current flowing through the resistor RL is as follows: I = ERG · sin (ωt) / RL (2) Here, ERG is a peak voltage of the ringing signal, and ERG = 1.414 · VRG (3) Therefore, the output power Pout and the input power Pin of the amplifier RGA can be derived as follows.

(Equation 1) Here, ω = 2πf, T1 = 1 / (2f), and f is the frequency of the ringing signal.

Here, the conversion efficiency η is a ratio between the output power and the input power, and is expressed as follows: η = Pout / Pin = πERG / 4VSA (6) Therefore, even in an ideal state where VSA is equal to ERG, the conversion efficiency η is η = π / 4 = 0.885 (7) That is, 78.5%. The conversion efficiency at the rated output of the DC / DC converter is 80% as described above.
Therefore, the conversion efficiency of this DC / AC converter is about 62% or less.

In other words, this means that power of about 3.4 W or more is required to obtain the AC power of 2 VA required to sound about 3 KΩ which is the effective resistance of the doorbell of a typical communication terminal. Is shown. This second problem is a phenomenon that occurs in principle when a linear operation analog amplifier is used, and is a factor that lowers the conversion efficiency at the time of load.

As described above, the first factor of the problem of large power consumption in the conventional DC / AC converter is that DC / AC
The second factor was the power consumption due to the difference voltage between the power supply voltage supplied to the amplifying unit and the output signal voltage.

It is an object of the present invention to reduce the parasitic capacitance around the transformer in the DC / DC converter section and make the output voltage waveform a pulsating wave, thereby making it possible to charge the parasitic capacitance around the transformer, which is one factor of power consumption. And reducing the difference voltage between the power supply voltage and the output voltage generated in the amplification unit by changing the amplification unit to a polarity inversion unit as much as possible, thereby suppressing power consumption and improving power conversion efficiency. It is.

[0023]

According to a first aspect of the present invention, a DC power supply is switched on a primary side of a transformer by a main switch to supply AC power to a secondary side of the transformer. A switching amplifier for generating and rectifying and smoothing the AC power to generate a main pulsating wave signal corresponding to a substantially sinusoidal full-wave rectified waveform;
A polarity reversing unit having a switching element that generates an AC output signal by reversing the polarity every cycle, and a reference pulsating flow of a full-wave rectified waveform
Reference pulsating wave signal generating means for generating a
Return pulse that generates full-wave rectification of the force signal and generates a return pulse wave signal
Flow wave signal generating means, the reference pulsation wave signal and the return pulsation flow
Error detection means for generating a difference signal corresponding to the difference from the wave signal
Stage and duty according to the signal level of the error signal
Having pulse width conversion means for generating a high frequency pulse having a ratio ,
A control circuit section for turning on / off the main switch by the high frequency pulse.
It was configured as an AC converter.

[0024] The second invention according to the first invention, the
The reference pulsating wave signal generation means of the control circuit
Generating means and full-wave rectification of an output signal of the sine wave signal generating means.
And a sine wave signal.
Duty ratio synchronized with the output signal of the signal generation means is approximately 5
A pulse conversion means for generating a 0% pulse;
In the polarity inverting section corresponding to the output signal of the
The DC / AC converter is characterized in that the polarity inversion of the main pulsating wave signal is controlled .

[0025] The third invention is the second invention, the
The reference pulsating wave signal generating means performs full-wave rectification of the sine wave signal.
N references for a half cycle of the formed reference pulsating wave signal waveform
A storage device storing the pulsating wave information,
The read address is set to one of the storage addresses of the reference pulsating wave information.
First reading means for increasing from the Nth to the Nth order;
The read address for the storage device is set to the reference pulse wave.
Decrease the information storage address from Nth to 1st
Second reading means, and a continuation of the first reading means.
Between the read operation and the read operation by the second read means.
Repeating means that repeat each other and occur at predetermined time intervals
When the interrupt signal is generated, the first or second reading means reads the signal.
Converting the detected reference pulsation wave information into an analog signal
/ Analog converter that generates a reference pulsating wave signal
Replace with another reference pulsating wave signal generating means having a step,
Reading the pulse conversion means by the first reading means
Polarity at the time of reading and at the time of reading by the second reading means.
Means for outputting information, and 1
The polarity information was "1" after the reading of the information
Inverts to "0" when it is "0" and to "1" when it is "0"
Replace with another pulse conversion means having polarity inversion means.
Further, the DC / AC converter is characterized in that:

In a fourth aspect based on the second or third aspect , when the activation signal is set for activation, the pulse change is performed.
The edge of the pulse obtained by the conversion means is detected later.
To operate the control circuit unit to perform DC / AC conversion operation.
When the start signal is set for stop,
The edge of the pulse obtained by the pulse conversion means is
The main switch is controlled to be inoperative by being detected.
And all the switching elements of the polarity reversing section are turned on.
The DC / AC converter is provided with a start / stop control means for setting the state to a state .

The fifth invention, in the fourth aspect, the
Start / stop control means for setting the start signal for stop
Of the pulse obtained by the pulse conversion means.
The main switch is then detected by detecting an even number of
And the switch element of the polarity reversal unit.
The DC / AC converter is characterized in that it operates to set all of the children to the ON state .

[0028] A sixth invention is any one of the first to fifth 1
In one aspect of the invention, the polarity inverting unit includes the switch
The main pulsating wave signal obtained from the
A first switch group for outputting to an output terminal, and the main pulsating wave signal;
A second switch for inverting the polarity of the signal and outputting the inverted signal to the output terminal.
And a duty ratio of the pulse width conversion means.
Duty ratio detecting means for detecting that the value is 0 or close to 0
And the duty ratio is detected by the duty ratio detection means.
By detecting that 0 or close to 0, the first
Or the switch that is currently off in the second switch group
Intermediate state of at least one switch of the group on and off
This is configured as a DC / AC conversion device characterized by performing the following control .

[0029]

[0030]

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a block diagram of a DC / AC converter according to a first embodiment for explaining the principle configuration of the present invention. It is a waveform diagram of the signal in each point. In FIG.
SWA is a switching amplifier that generates a main pulsating wave voltage corresponding to a full-wave rectified waveform of a sine wave signal from a supplied DC power supply, and PSW changes the main pulsating wave voltage every cycle (every half cycle of a sine wave). A polarity reversing unit for forming a sine wave voltage corresponding to a ringing signal by reversing the polarity, CONT
Is a control circuit section for controlling the switching amplification section SWA and the polarity inversion section PSW.

The control circuit unit CONT generates a reference pulsating wave signal VX1 corresponding to a full-wave rectified waveform of a sine wave signal, and controls the ON / OFF of the switches SW1 to SW4 of the polarity reversing unit PSW. Wave generation / polarity controller SSC
C, having a pulse width converter PSCC that receives the reference pulse wave signal VX1 and outputs a pulse signal VDR that is pulse width modulated so as to increase the pulse width in proportion to the level of the reference pulse wave signal VX1. . As the reference pulsating wave signal VXI generated by the reference pulsating wave generation / polarity control unit SSCC, for example, a signal obtained by full-wave rectifying a sine wave generated from a sine wave generating means is used.

In order to obtain a pulse width modulation waveform in the pulse width converter PSCC, for example, a ramp wave generating circuit for generating a high-frequency triangular signal (or sawtooth signal) and a voltage comparator are used, and a voltage comparator is used as a reference. The pulsating wave signal VX1 and the triangular wave signal are input. When the voltage level of the reference pulsating wave signal VX1 is higher, “1” is output as an output signal, and when the voltage level is lower, “0” is output. Thereby, the reference pulsating wave signal V
A pulse signal VDR obtained by pulse width modulation so as to increase the pulse width in proportion to the level of X1 is obtained.

The switching amplifier SWA includes a main switch SW0, a primary winding L1, a transformer T1 having a secondary winding L2 having a secondary winding L2, a rectifying diode D1, and a smoothing capacitor C2. The main switch SW0 is connected to the control circuit C
It is turned on and off according to “1” and “0” of the pulse width modulation signal VDR supplied from the ONT.

The current flowing from the DC power supply Ei is turned on / off by the main switch SW0, so that the pulse wave front voltage changes with time in the secondary winding L2 of the transformer T1 and the envelope of the voltage value changes. A voltage EL2 having a waveform such that the line forms a sine wave is generated. Since this voltage EL2 is smoothed by the rectifying diode D1 and the smoothing capacitor C2, a main pulsating wave voltage EC2 corresponding to a full-wave rectified waveform of a sine wave signal appears at both ends of the capacitor C2. Note that the capacitor C1 connected in parallel to the DC power supply Ei is an input capacitor.

In the polarity inversion section PSW, the control circuit section CON
Each time the reference pulsating wave signal VXI generated from the reference pulsating wave generation / polarity control unit SSCC during T becomes zero level, one of the pair of switches SW1 and SW3 and the pair of switches SW2 and SW4 is turned on. The sine wave signal corresponding to the ringing signal is formed by inverting the polarity of the main pulsating wave voltage EL2 obtained by the switching amplifier SWA by repeating the other set so that the other set is turned off. L3 is an inductor, C
Reference numeral 3 denotes a capacitor, which forms a low-pass filter.

The reason why the maximum voltage (wavefront voltage) of the voltage EL2 generated in the secondary winding L2 of the transformer T1 changes for each pulse will be described here. The period during which the main switch SW0 is in the ON state is changing every moment. Main switch SW
When 0 is turned on, the voltage of the DC power supply Ei is applied to the primary winding L1 of the transformer T1. As is well known, the voltage developed across an inductor is proportional to the rate of change of the current flowing through it over time. When a constant voltage is applied, the current flowing therethrough increases in proportion to time.

When the main switch SW0 changes from the on-state to the off-state, the current flowing through the winding L1 that has been increasing tends to decrease. Therefore, a voltage having a polarity opposite to that when the main switch SW0 is on is generated in the winding L1. In addition, since the main switch SW0 is turned off, the current flowing through the winding L1 suddenly becomes 0, so that a very high voltage is generated in the winding L1. Since this voltage also occurs in the secondary winding L2 of the transformer T1, if this voltage becomes higher than the voltage EC2 of the capacitor C2, the rectifier diode D1 is biased in the forward direction, so that it is generated in the winding L2. Voltage is almost voltage EC
It can be reduced to 2.

At this time, a current flows from the winding L2 to the capacitor C2 and the load via the rectifier diode D1. The charging energy for this capacitor C2 is
Excitation energy corresponding to the current flowing when the main switch SW0 was turned off from the on state substantially corresponds to the difference between the amount of energy released and the amount of energy supplied to the load.

Therefore, if the duty ratio of the switch SW0 is large, that is, if the ON period is long, the excitation energy increases, and a part of the excitation energy charges the capacitor C2, and the voltage E of the capacitor C2 is increased.
C2 increases. If the duty ratio of the main switch SW0 is small, that is, if the ON period is short, the excitation energy is reduced, and the charging energy and the excitation energy of the capacitor C2 are supplied to the load, so that the voltage EC2 of the capacitor C2 decreases. I do. Thus, the main switch S
By appropriately controlling the on / off duty ratio of W0 as indicated by VDR in FIG. 2, the waveform of the voltage EC2 generated in the capacitor C2 is made into a pulsating waveform corresponding to a full-wave rectified waveform of a sine wave signal. Can be.

Conventionally, the supplied DC power is converted into bipolar power and supplied to an amplifier, and the amplifier amplifies a sine wave signal to form a ringing signal. The form is such that a pulsating wave corresponding to a full-wave rectified waveform of a sine wave signal is formed from the DC power supplied in the switching amplifier SWA, and the pulsating wave is transferred to the polarity inverting unit PSW, where the sine wave corresponding to the ringing signal is generated. In terms of forming
to differ greatly.

The switch amplifying unit SWA of this embodiment has D
Although the same as the main circuit of the C / DC converter, the duty ratio of the main switch SW0 is
By controlling the maximum value of the pulse voltage EL2 generated in the secondary winding L2 to draw an envelope of the pulsating wave, a pulsating wave is formed. As described above, the difference between the output voltage of the main circuit and the pulsating wave affects the amount of charging energy for the parasitic capacitance around the transformer T1.

That is, the peak value of the pulse voltage generated in the winding of the transformer T1 draws a sine wave envelope (maximum value Vx) having a frequency f, and the main switch SW0 operates N times within a half cycle of the sine wave. Es is the charging energy for the parasitic capacitance C when the switching operation is performed.

(Equation 2) On the other hand, when the output is DC as in a conventional DC / DC converter, the charging energy Ea for the parasitic capacitance C when the peak value of the pulse voltage generated in the winding of the transformer is Vx is: Ea = Vx2CN / 2 (9) It can be seen that the pulsating waveform corresponding to the full-wave rectified sine wave has half the charging energy for the parasitic capacitance C.

Further, in this embodiment, the transformer T1 has one secondary winding, so that the parasitic capacitance C existing between the winding lines can be reduced as compared with the conventional transformer T21. Although not all of this charging energy is consumed, it is consumed when the main switch is turned on and as iron loss of the transformer. Therefore, it can be considered that the smaller the charging energy, the lower the power consumption.

The polarity inversion section PSW for converting the pulsating wave voltage into a sine wave ringing signal includes four switches SW1 to SW
Since the current path is formed from W4 and the current path is formed by two of the switches, for example, if a Darlington-connected transistor is used, the voltage drop per switch is approximately 1 V, and the polarity inversion portion PSW is approximately This results in a voltage drop of 2V. Therefore, the conversion efficiency when a ringing signal having an output effective voltage value of 80 Vrms is formed is about 98% (80/82). For example, if the conversion efficiency of the switching amplifier SWA is estimated to be about 80%, this DC / AC converter has a total conversion efficiency of about 78%
Therefore, superior performance can be realized as compared with the conventional 62%.

[Second Embodiment] FIG. 3 shows a second embodiment of the present invention.
1 is a block diagram of a DC / AC converter according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of a signal at each point. 3, the switching amplifier SWA and the polarity inverting unit PSW are the same as those in FIG. 1 described in the first embodiment, and the internal configuration of the control circuit unit CONT is different.

Here, the control circuit unit CONT includes a reference pulsating wave generation / polarity control unit SSCC and a pulse width conversion unit PSC.
In addition to C, a full-wave rectifier REC0 that performs full-wave rectification on the output voltage Vo output from the polarity inverting unit PSW to the load RL and converts the output voltage Vo into a feedback pulsation wave signal VD1, and uses the feedback pulsation wave signal VD1 as a reference pulsation. The signal subtracted from the wave signal VR1 is a signal VA1
And an error amplifier AMP0 to be input to the pulse width converter PSCC, whereby the output signal Vo is negatively fed back.

The reason why the output signal Vo is negatively fed back is to reduce a change in the output voltage Vo and a waveform distortion of the output signal caused by a load fluctuation or a voltage fluctuation of a power supply source.

[0049] Pulse width converter PS in the present embodiment
As the CC, for example, a power supply control circuit PSC shown in FIG. 6 described later may be used. However, at this time,
The output signal VA of the error amplifier AMP0 is used for negative feedback.
It is necessary to invert I (or to reverse the connection between VR1 and VD1).

Thus, in the second embodiment, when the output voltage Vo input to the control circuit unit CONT increases, the duty of the pulse width signal decreases, and when the output voltage Vo decreases, the operation increases, and the output voltage Vo increases. Stabilizes.

[Third Embodiment] FIG. 5 shows a third embodiment of the present invention.
FIG. 6 is a specific circuit diagram of the control circuit unit CONT in the circuit of FIG. 5, and FIG. 7 is a waveform diagram of a signal at each point.

In FIG. 5, the same components as those shown in FIG. 1 are denoted by the same reference numerals. Switching amplifier S
The WA includes an input capacitor C1, a main switch M1 including a MOS transistor, a transformer T1 having windings L1 and L2, a rectifier diode D1, and a smoothing capacitor C2. Switch SW1 configuring polarity reversing unit PSW
To SW4 are resistors R1, R2, R3, R4, photocoupler light receiving transistors PC1T, PC2T, PC3T,
PC4T, PNP transistors Q1, Q2, Q3, Q4
It consists of.

The control circuit unit CONT has a feedback input terminal SP
Is connected to an output terminal RGP of a ringing signal (output signal), the drive terminal DR is connected to the gate terminal of the main switch M1, the polarity control terminal PS1 for outputting negative polarity is connected to light emitting diodes PC1D and PC3D of a photocoupler, and the positive polarity is connected. Is connected to the light-emitting diodes PC2D and PC4D of the photocoupler.

The light emitting diode PC1D and the light receiving transistor PC1T, the light emitting diode PC2D and the light receiving transistor PC2T, the light emitting diode PC3D and the light receiving transistor PC3T, the light emitting diode PC4
The set of D and the phototransistor PC4T each form a set of photocouplers. Further, although PNP transistors are used for the switches SW1 to SW4, when an NPN transistor is used, the switch circuit SW shown in the corner of FIG.
It can be replaced with W.

The terminal D of the control circuit unit CONT is
The ringing signal output to the output terminal RGP of the C / AC converter is connected, and the control circuit unit CONT outputs a high-frequency pulse signal having a duty ratio controlled such that the ringing signal approaches a sine wave from the terminal DR to the main switch M1. The on / off operation of the main switch M1 (VDR in FIG. 7) is controlled by applying the voltage to the gate terminal.

The DC voltage Ei supplied to the supply terminals INP and ING of the DC power supply is converted into a pulse voltage by the switching operation of the main switch M1 and applied to the primary winding L1 of the transformer T1. A pulse voltage (see EL2 in FIG. 7), which is a pulsating wave whose peak voltage envelope corresponds to a sine-wave full-wave rectified waveform, is generated in the winding. This pulse voltage is rectified by the rectifier diode D1 and smoothed by the smoothing capacitor C2, and the above-mentioned pulsating waveform voltage (see EC2 in FIG. 7) is generated between the terminals GP and GN.

The polarity control terminal PS1 of the control circuit unit CONT
When a voltage of "0" is output to the pixel and a voltage of "1" is output to the PS2, a current flows through the light emitting diodes PC2D and PC4D, and a current flows between the collector terminal and the emitter terminal of the light receiving transistors PC2T and PC4T. At this time, no current flows through the light emitting diodes PC1D and PC3D. The collector terminal of the light receiving transistor PC2T is a PNP transistor Q2
, The current flows from the emitter terminal to the collector terminal of the PNP transistor Q2. Since the collector terminal of the light receiving transistor PC4T is connected to the base terminal of the PNP transistor Q4, current flows from the emitter terminal of the PNP transistor Q4 to the collector terminal.

Thus, the switches SW2 and SW4 are turned on and the switches SW1 and SW3 are turned off, and the terminals GP → P
NP transistor Q2 → inductor L3 → output terminal RG
P → load → output terminal RGG → current path is formed in the direction of terminal GN via PNP transistor Q4, and terminal RG
A voltage having the same polarity as that of the terminal GP appears at P.

Next, when a voltage of “1” is output to the polarity control terminal PS1 and a voltage of “0” is output to PS2 of the control circuit unit CONT, a current flows through the light emitting diodes PC1D and PC3D,
A current flows between the collector terminal and the emitter terminal of the light receiving transistors PC1T and PC3T. At this time, no current flows through the light emitting diodes PC2D and PC4D. Since the collector terminal of the light receiving transistor PC1T is connected to the base terminal of the PNP transistor Q1, this PN
A current flows from the emitter terminal of the P transistor Q1 to the collector terminal. Also, the light receiving transistor PC
Since the collector terminal of 3T is connected to the base terminal of PNP transistor Q3, this PNP transistor Q3
The current flows from the emitter terminal of No. 3 to the collector terminal.

Thus, the switches SW1 and SW3 are turned on, and the switches SW2 and SW4 are turned off, and the terminals GP → P
NP transistor Q1 → terminal RGG → load → terminal RGP
→ A current path is formed in the direction of the terminal GN via the inductor L3 → PNP transistor Q3, and a voltage having a polarity opposite to that of the terminal GP appears at the terminal RGP. As described above, when current is alternately supplied to the photocoupler from the two polarity control terminals PS1 and PS2, the polarity of the voltage appearing between the output terminals RGP and RGG is inverted.

In the switches SW1 to SW4,
The light-receiving transistor and the PNP transistor are Darlington connected, and when a current flows between the emitter terminal and the collector terminal of the PNP transistor, the light-receiving transistor is in a saturation operation state. (Collector saturation voltage) is about 0.2V.

Therefore, the potential difference between the emitter terminal and the collector terminal of the PNP transistor is the sum of the potential difference (approximately 0.7 V) between the emitter terminal and the base terminal of the PNP transistor and the collector saturation voltage of the light receiving transistor. It becomes approximately 0.9V and switches SW1 to SW
4 operates as a switch with a voltage drop of approximately 1V.

As described above, the pulsating waveform voltage EC2 formed in the smoothing capacitor C2 is converted into a sinusoidal AC waveform by controlling the polarity reversing unit PSW by the polarity control terminals PS1 and PS2 of the control circuit unit CONT. And output from the terminals RGP and RGG as a ringing signal.

FIG. 6 is a diagram showing a configuration of the control circuit unit CONT. The control circuit unit CONT includes a signal comparison circuit SCC for detecting an error component between a feedback signal obtained by feeding back the output voltage and an internally generated reference signal, a polarity control circuit PCN for switchingly controlling the switches SW1 to SW4, and a main circuit. The power supply control circuit (pulse width converter) PSC generates a pulse width signal for turning on / off the switch M1.

The signal comparing circuit SCC includes a first full-wave rectifier circuit REC1 for converting an output AC signal input to the feedback terminal SP into a pulsating signal, and an oscillator P for generating a rectangular wave signal VPG.
G, a sine wave signal VSG obtained by filtering the rectangular group signal VPG.
, A second full-wave rectifier circuit REC2 that converts the output sine wave signal VSG of the filter FIL into a pulsating signal, and the voltages of the output signals VD1 and VR1 of both full-wave rectifier circuits REC1 and REC2. Error amplifier A that compares
MP1.

The polarity control circuit PCN compares the output signal VSG of the filter FIL with the reference voltage Voff to generate a pulse signal having a duty ratio of approximately 50%, as a voltage comparator COMP1 as pulse conversion means, and the voltage comparator COMP1. COMP
First and second inverters INV for inverting the output signal of
1, INV2 and its inverters INV1, INV
2 comprises resistors RP1 and RP2 for guiding the output signal to the polarity control terminals PS1 and PS2.

The power supply control circuit PSC, which functions as a pulse width conversion unit, includes an error amplifier AMP2 for comparing the output signal VSI of the signal comparison circuit SCC with a reference voltage Vref and amplifying the error component, a ramp generator ROSC, and its ramp. Output signal VCT of wave generator ROSC and error amplifier AMP2
A voltage comparator CMP2 which compares the output signal VER of the ramp wave generator ROSC0 to output a comparison signal VPW, a voltage comparator CMP3 which compares the output signal VCT of the ramp generator ROSC0 with the signal VDT and outputs a comparison signal VDW, and both signals VPW. , VDW to drive the main switch M1
It is formed from a main switch drive circuit DRV that outputs DR.

The operation of the control circuit unit CONT will be described below with reference to FIG.
This will be described using the operation waveforms shown in FIG. Signal comparison circuit SCC
, The rectangular wave signal VP generated by the rectangular wave oscillator PG
The frequency of G is approximately 16 Hz, which is equal to the frequency of the ringing signal. This rectangular wave signal VPG is filtered by a filter FIL.
, The filter FIL causes the signal VS to be substantially sinusoidal.
G is output. Since this filter FIL is used to remove harmonic components of the input rectangular wave signal, it can be applied to either a low-pass filter or a band-pass filter.

In the polarity control circuit PCN, the sinusoidal signal VSG is applied to the voltage comparator COMP1. The voltage comparator COMP1 is configured such that the voltage of the signal VSG applied to the positive input terminal is equal to the voltage Voff applied to the negative input terminal.
Since the logic signal "1" is output when the voltage is higher than the voltage, and "0" is output when the voltage is lower, the average voltage of the sinusoidal signal VSG is set as the voltage Voff. Is inverted by the inverter INV1 is VPS
1, and a signal obtained by further inverting the signal by the inverter INV2 becomes a rectangular wave signal having a polarity like VPS2. These rectangular wave signals VPS1, VPS2
Are in anti-phase relationship and are led to polarity control terminals PS1 and PS2 via resistors RP1 and RP2, respectively.

In the signal comparison circuit SCC, the sine wave signal VSG is also applied to the full-wave rectifier REC2,
Here, the reference pulsating wave signal VR1 is formed, and the differential amplifier A
Applied to the negative input terminal of MP1. On the other hand, the feedback terminal S
The AC signal VRG (Vo) output between the terminals RGP and RGG of the DC / AC converter is applied to P. This signal VRG is full-wave rectified by the full-wave rectifier REC1 to become a signal VD1, which is applied to the positive input terminal of the error amplifier AMP1. The error amplifier AMP1 amplifies the difference voltage between the voltages applied to the positive and negative input terminals,
A signal VSI is applied to the input terminal SI of the power supply control circuit PSC.

Therefore, the output signal VSI of the error amplifier AMP1 is a signal representing an error between the output signal VRG of the DC / AC converter and the reference pulsating wave signal VR1.

The signal VSI input to the input terminal SI of the power supply control circuit PSC is input to the negative input terminal of the error amplifier AMP2. A reference voltage Vref generated by a reference voltage generator is applied to a positive input terminal of the error amplifier AMP2. This reference voltage Verf is a DC voltage that is substantially constant even if the temperature or the power supply voltage fluctuates. The output voltage VER of the error amplifier AMP2 inverts and amplifies the signal VSI at the input terminal SI, and guides it to the positive input terminal of the voltage comparator CMP1. Note that the DC voltage VDT is applied to the positive input terminal of the voltage comparator CMP3.

Since the output signal (high-frequency triangular signal or sawtooth signal) VCT of the ramp generator ROSC0 is applied to the negative input terminals of both voltage comparators CMP2 and CMP3, one output of the voltage comparator CMP2 is positive. When the input voltage VER of the input terminal is lower than the triangular wave signal VCT, the logic signal is “0” (duty ratio 0%).
When the duty ratio (100%) is within the amplitude range of the triangular wave signal VCT, the ramp generator ROS has a duty ratio corresponding to the level of the input voltage VER of the positive input terminal.
A C0 triangular wave signal or a pulse signal having the same frequency as the sawtooth wave is output. The other voltage comparator CMP3 operates similarly in response to the fixed input voltage VDT.

These two voltage comparators CMP2, CMP2
The output signals VPW and VDW of No. 3 are input to the drive circuit DRV. Therefore, the pulse signal VDR having a smaller duty ratio of the output signals VPW and VDW is output to the drive output terminal DR.

Here, since the fixed voltage VDT is applied to the positive input terminal of the voltage comparator CMP3, this voltage VDT sets the maximum duty ratio of the pulse signal output to the drive output terminal DR.

As is clear from the above, the power supply control circuit P
SC inverts and amplifies signal VSI at terminal SI,
The lower the signal VSI, the larger the duty ratio is, and the pulse signal VDR with the maximum duty ratio is restricted is formed and output from the drive output terminal DR. This drive output terminal DR is applied to the gate terminal of the main switch M1 shown in FIG. 5, and the duty ratio of the main switch M1 increases when the voltage applied to the input terminal SI is low, and decreases when the voltage applied to the input terminal SI is high. Is controlled.

In this embodiment, although the reference voltage Vref is applied to the positive input terminal of the error amplifier AMP2 of the power supply control circuit PSC, if this connection can be cut off, the signal comparison circuit SCC full-wave rectifier R
The error amplifier AMP1 can be omitted by connecting the output signal VD1 of EC1 to the negative input terminal of the error amplifier AMP2 and connecting the output signal VR1 of the full-wave rectifier REC2 to the positive input terminal of the error amplifier AMP2.

With the above configuration, the main switch M1 shown in FIG. 5 performs a switching operation by applying the pulse voltage VDR to its gate terminal, thereby generating a voltage in the winding L2 of the transformer T1. Pulse voltage EL2
Is rectified by the diode D1, smoothed by the smoothing capacitor C2, appears on the capacitor C2 as a pulsating wave signal EC2, and the pulsating wave signal EC2 is 1 at the polarity reversing unit PSW.
The polarity is inverted every cycle, and the signal is output from the terminals RGP and RGG to the load as a sinusoidal ringing signal. This sinusoidal ringing signal has a constant voltage irrespective of load fluctuation, power supply fluctuation and the like.

Fourth Embodiment FIG. 8 is a diagram showing a configuration of a control circuit unit CONT according to a fourth embodiment as a reference example of the present invention, and FIG. 9 is a time chart of the operation. Here, in particular, the signal comparison circuit SCC
It has features. This signal comparison circuit SCC is formed by an error amplifier AMP3, an inverting amplifier INVA, and a multiplexer (signal switching means) MPX. The polarity control circuit PCN and the power supply control circuit PSC have the same configuration and the same operation as those shown in FIG.

The operation will be described below with reference to the time chart shown in FIG. The ringing signal output from the output terminal RGP of the DC / AC converter is applied to the feedback input terminal SP, and is introduced to the positive input terminal of the error amplifier AMP3. The output signal VSG of the filter FIL is a reference sine wave signal of approximately 16 Hz as described above, and this signal is applied to the negative input terminal of the error amplifier AMP3.

As a result, in the error amplifier AMP3, the difference voltage between the ringing signal and the reference sine wave signal is detected and amplified, and the signal VDP is formed. The inverting amplifier INVA is a linear amplifier having a voltage gain of 1 and a phase difference of 180 degrees. The signal VDP and the output signal VDN of the inverting amplifier INVA are input to the multiplexer MPX.

A signal VPS2 is input as a control signal from the polarity control circuit PCN to the multiplexer MPX. When the signal VPS2 is "1", the signal VDP is obtained. When the signal VPS2 is "0", the signal VDP is outputted. Signal VDN is selected and transmitted to input terminal SI of power supply control circuit PSC. That is, the inverting amplifier INVA and the multiplexer MPX output the output signal VD of the error amplifier AMP3.
P is full-wave rectified. Therefore, the pulsating wave signal VSI obtained by full-wave rectifying the signal VDP is input to the feedback input terminal SI of the power supply control circuit PSC.

The pulsating wave signal VSI input to the input terminal SI of the power supply control circuit PSC drives the main switch M1 as in the case of the third embodiment, whereby the secondary winding of the transformer T1 is driven. A pulse voltage EL2 is generated on the line L2,
This is rectified by the diode D1 and the smoothing capacitor C2
The pulsating wave signal EC2 is formed at the first stage, and is formed into a sinusoidal ringing signal by the polarity reversing unit PSW.

The third embodiment is characterized in that the pulsating wave signal VSI is formed after the difference voltage between the ringing signal and the reference sine wave signal is amplified and transmitted to the input terminal SI of the power supply control circuit PSC. Unlike the configuration, the filter R
EC1 and REC2 become unnecessary, and the number of components can be reduced.

[Fifth Embodiment] FIG. 10 is a diagram showing a configuration of a control circuit unit CONT according to a fifth embodiment of the present invention.
FIG. 11 is a time chart of the operation. In the third and fourth embodiments, the DC / AC converter continuously generates a ringing signal. Since the resistor RL serving as a load is connected via the switches SW1 to SW4, there is no problem if the switches SW1 to SW4 are turned on while the ringing signal is at a low voltage, but a high voltage is output. When the switch is turned on in the state, D
When the input current of the C / AC converter is rapidly increased and a power supply having a high internal resistance such as a battery is used as the DC power supply Ei,
There is a problem that the power supply voltage temporarily drops and adversely affects peripheral circuits.

The fifth embodiment of the present invention is designed to prevent such a phenomenon. In the present embodiment, the configuration of the polarity control circuit PCN is such that the output of the ringing signal is controlled by an external start signal. The configurations of the switching amplifier SWA, the polarity inverting unit PSW, and the signal comparison circuit SCC are the same as those described above. Third, it is the same as the fourth embodiment.

In FIG. 10, the polarity control circuit PCN
Sine wave signal VSG of signal comparison circuit SCC and reference voltage Vof
f1 and a voltage comparator COMP1 for comparing f
A first flip-flop circuit FF1, which receives the output signal CKA of the OMP1 as a clock, a NAND gate G1,
G2 and resistors RP1 and RP2.

The power supply control circuit PSC has a third functional configuration.
As in the fourth embodiment, the main switch drive circuit DRV is provided with a new control terminal EN, and when "1" is applied to this terminal EN, the voltage comparator CM
A pulse signal V for driving the main switch M1 corresponding to the logical product of the output signals VPW and VDW of P2 and CMP3.
DR is output from the output terminal DR. When "0" is applied, the signal VDR output to the output terminal DR is always "0", and the main switch M1 does not perform a switching operation.

The first flip-flop circuit FF1 is an edge-triggered flip-flop circuit, and changes the signal of the clock terminal CK from "0" with the reset terminal R and the preset terminal PR set to "1". When changed to “1”, the data “DT” given to the data terminal DT is taken in, the data “DT” is output to the output terminal QN, and the data “DT” is inverted to the inverted output terminal QI. And output the data. When "0" is given to the preset terminal PR, the output terminal QN becomes "1" and the inverted output terminal QI becomes "0". When "0" is given to the reset terminal R, the output terminal QN becomes "0". In addition, the inverted output terminal QI becomes "1", and at this time, the function of the signal input to the clock terminal CK functions so as to be ignored.

The terminal RST of the polarity control circuit PCN is connected to the DC power supply terminals INP, IP of the DC / AC converter of the present invention.
A start signal input terminal for initializing the apparatus when DC power is supplied to NG, and by applying "0" to this terminal RST and "1" to the start terminal RNG, the first Output terminal QN of the flip-flop circuit FF1
Is set to "1" and the inverted output terminal QI is set to "0".
Thereafter, “1” is applied to the terminal RST.

The inverted output terminal QI of the first flip-flop circuit FF1 is connected to one input terminal of the NAND gates G1 and G2 and the output terminal PSE. Also,
The output of the NAND gate G1 is connected to the other input terminal of the NAND gate G2 and connected to the polarity control terminal PS1 via the resistor PR1, and the output terminal of the NAND gate G2 is connected to the polarity control terminal PS2 via the resistor PR2. I have.

The above initialization (RST = "0", RNG
= "1"), the output terminal PSE outputs "0", and the polarity output terminals PS1 and PS2 output "1". Therefore, in this initialized state, the signal at the terminal EN of the power supply control circuit PSC becomes “0”, so that the main switch drive circuit DRV is not driven, the main switch M1 is turned off, and the four polarity inverting parts PSW Switches SW1 to S
W4 is turned on, the voltage VRG between the output terminals RPG and RGN becomes approximately 0 V, and no ringing signal is output.

In the voltage comparator CMP1, when the sinusoidal signal VSG applied to the positive input terminal is higher than the reference voltage Voff applied to the negative input terminal, the logic signal "1" is set to the low voltage. In this case, since the logic signal "0" is output as the clock signal CKA, if the average voltage of the sine-wave signal VSG is set as the reference voltage Voff, the clock signal CKA becomes a rectangular wave signal. This clock signal CKA is applied to the terminal CK of the flip-flop circuit FF1 and the other input terminal of the first NAND gate G1.

Now, when the activation terminal RNG changes from “1” to “0”, when the signal CKA changes from “0” to “1” after the activation terminal RNG changes to “0”, the flip-flop FF1 Changes to “1”. Therefore, the output VSP1 of the NAND gate G1 is "0".
In addition, the output VPS2 of the NAND gate G2 becomes "1",
The polarity control terminals PS1 and PS2 are “0” and “1”, respectively.
Then, the output terminal PSE changes to "1". Therefore, the switches SW2 and SW4 of the polarity reversing unit PSW are turned on, the switches SW1 and SW3 are turned off, and the main switch driving circuit DRV of the power supply control circuit PSC is connected to the terminal E.
Since N becomes "1", the main switch M1 starts switching, and a signal for a positive half cycle is output between the output terminals RGP and RGG.

Next, when the signal CKA changes from "1" to "0", the output signal VPS1 of the NAND gate G1 becomes "1".
In addition, the output VPS2 of the NAND gate G2 changes to “0”, and the polarity control terminals PS1 and PS2 respectively change to “1”,
The switch SW1 of the polarity reversal unit PSW is inverted to “0”.
Since the switch SW3 is turned on and the switches SW2 and SW4 are turned off, a signal for a negative half cycle is output between the output terminals RGP and RGG. Thus, the output of the sinusoidal ringing signal is started.

If the activation signal RNG changes from "0" to "1" while the ringing signal is being output, when the signal CKA subsequently changes from "0" to "1",
The output terminal QI of the flip-flop circuit FF1 changes to "0". Accordingly, the output signals VSP1 and VSP2 of the NAND gates G1 and G2 both become "1", so that both the polarity control terminals PS1 and PS2 also become "1", and the switches SW1 to SW4 of the polarity reversing unit PSW are turned on. At the same time, the output terminal PSE becomes "0", the main switch drive circuit DRV of the power supply control circuit PSC stops operating, the signal VDR of the terminal DR becomes "0", the main switch M1 stops the switching operation, and the ringing is performed. The output of the signal is stopped.

The polarity control circuit PCN enables the ringing signal to be controlled by the start signal, and starts to output the ringing signal from approximately 0 V and stops at approximately 0 V. Since no voltage is applied, a phenomenon that the input current sharply increases with the activation of the ringing signal does not occur.

[Sixth Embodiment] FIG. 12 is a diagram showing a configuration of a control circuit unit CONT according to a sixth embodiment of the present invention.
FIG. 13 is a time chart of the operation. When semiconductor switches having a PNPN structure such as a thyristor or a triac are used as the switches SW1 to SW4 for driving the load RL, if a DC current is superimposed on a ringing signal and flows through these switches, these switch elements In some cases, the switch is not turned off even if the drive signal to the switch is removed.

Therefore, as a condition for turning off these PNPN elements, the element current needs to be equal to or less than a current value called a holding current. Since the state in which the element current should be reduced to the holding current or less is required after the control signals for these PNPN elements are stopped, the ringing signal is further continuously output, and the voltage applied to the PNPN elements becomes approximately 0V. It is necessary to form a state.

In the sixth embodiment, even after the start signal for controlling the ringing signal is stopped, one more
The present invention relates to a configuration for continuously outputting a periodic ringing signal.

This embodiment relates to the configuration of the polarity control circuit PCN of the control circuit unit CONT. In the control circuit unit CONT, the configuration of the signal comparison circuit SCC is the same as that of the third to fifth embodiments. The power supply control circuit PSC is the same as that of the fifth embodiment. Also, the polarity control circuit PC
Among N, the same components as those shown in FIG. 10 are denoted by the same reference numerals. Here, the second flip-flop circuit FF2 is connected to the polarity control circuit PCN shown in FIG.
Has been added.

This second flip-flop circuit FF2
The clock signal CKA is applied to the CK terminal, the terminal R is connected to the reset terminal RST, the terminal DT is connected to the inverted output terminal QI of the flip-flop circuit FF1, the terminal PR is connected to the output terminal QN of the flip-flop circuit FF1, and the output terminal QN
Are connected to one input terminal of the NAND gates G1 and G2. The clock signal CKA is applied to the other input terminal of the NAND gate G1.

As in the fifth embodiment, the terminal RST of the polarity control circuit PCN is used to initialize the apparatus when DC power is supplied to the DC power supply terminals INP, ONG of the apparatus. This is a start signal input terminal.
When "0" is applied to ST and "1" is applied to start terminal RNG, output terminals QN and QI of flip-flop circuit FF1 are output.
Are "1" and "0", respectively, and the flip-flop circuit F
The output terminal QN of F2 is set to "0". Thereafter, “1” is applied to the terminal RST.

By this initialization, the output terminal PSE becomes "0", and the polarity output terminals PS1 and PS2 both become "1".
Will be output. Therefore, in this initialized state, the main switch M1 is turned off, the switches SW1 to SW4 of the polarity reversing unit PSW are turned on, and the output terminal RG
P and RGG become almost 0 V, and a state where no ringing signal is output is obtained.

The rectangular wave signal CKA is generated on the output side of the voltage comparator CMP1 as described above. This signal CKA
Is the terminal C of both flip-flop circuits FF1 and FF2
K is applied to the other input terminal of the NAND gate G1.

Now, when the activation terminal RNG changes from "1" to "0", when the signal CKA changes from "0" to "1" after the activation terminal RNG has changed to "0", the flip-flop is turned off. The output terminals QN and QI of the circuit FF1 change to "0" and "1", respectively. Since the output terminals QN and QI of the flip-flop circuit F11 are connected to the PR terminal and the DT terminal of the second flip-flop circuit FF12, respectively, the terminal QN of the first flip-flop circuit FF11 becomes "0". Accordingly, the second flip-flop circuit FF12 is preset, and its terminal QN changes to “1” and the terminal QI changes to “0”.

Therefore, the polarity control terminals PS1, PS2
Changes to "0" and "1", and the output terminal PSE changes to "1". Therefore, the switches SW2 and SW4 of the polarity reversing unit PSW are turned on, and the switches SW1 and SW3 are turned off. The main switch drive circuit D of the power supply control circuit PSC
Since the terminal EN of the RV becomes “1”, the main switch M1 starts the switching operation, and the output terminals RGP,
A half cycle of positive polarity is output between RGG.

Next, the clock signal CKA changes from "1" to "1".
When it changes to “0”, the polarity control terminals PS1 and PS2 are inverted to “1” and “0”, respectively, and the switches SW1 and SW3 of the polarity inversion unit PSW are turned on, and the switches SW
2. Since SW4 is turned off, the output terminal R
A half cycle of negative polarity is output between PG and RGG. Thus, the output of the sinusoidal ringing signal is started.

When the ringing signal is being output,
When the signal at the terminal RNG changes from “0” to “1”, and when the signal CKA subsequently changes from “0” to “1”, the output terminals QN and QI of the flip-flop FF1 are “1” and “I”, respectively. 0 ". Here, the preset state of the second flip-flop FF2 ends because the terminal PR has changed from “0” to “1”, but the terminal CK has already changed to “1”. QI does not change. Therefore, the output of the ringing signal is continued.

Next, the clock signal CKA becomes "0" again.
When it changes to "1", the output terminals QN and QI of the flip-flop circuit FF2 change to "0" and "1" because the input terminal DT is "0" at this time. Therefore, the output terminal PSE becomes "0", the polarity control terminals PS1 and PS2 both become "1", the switches SW1 to SW4 are turned on, and the main switch drive circuit DRV of the power supply control circuit PSC stops operating. The signal VDR at the terminal DR is “0”
And the main switch M1 stops the switching operation,
The output of the ringing signal is stopped.

That is, the polarity control circuit PCN of the sixth embodiment starts outputting the ringing signal by setting the start signal of the start terminal RNG to “0”, and sets the start signal to “1”. Thus, the ringing signal for at least one cycle is continuously output.

Since the operation is performed as described above, the output of the ringing signal is started from 0 V at the time of starting, and the output is stopped with the output voltage at 0 V at the time of stopping. Further, since the ringing signal is continuously output for one cycle after removing the drive signals of the switches SW1 to SW4, the voltage applied to the switches SW1 to SW4 during that period is substantially zero.
V, and there is a state where the switch element current is substantially 0. Even if a PNPN element is used for the switches SW1 to SW4, it can be reliably turned off.

[Seventh Embodiment] FIG. 14 is a diagram showing a configuration of a control circuit unit CONT according to a seventh embodiment of the present invention. Here, a part of the function of the control circuit unit CONT is realized by using a microcontroller MCU. here,
The power supply control circuit section PSC is the same as that described in the fifth and sixth embodiments. Signal comparison circuit SCC
Is a single full-wave rectifier circuit REC1 and an error amplifier AMP.
It is composed of 1. The polarity control circuit PCN includes a central processing unit C
PU, storage unit MEM, input / output unit PORT, timer unit TI
It comprises a known miro controller MCU composed of M and D / A converters DAC, and resistors PR11 and PR12.

The terminal A0 of the input / output unit PORT is for inputting a start signal RNG. The terminals A1 and A2 are for outputting polarity control signals, and are connected to the polarity control terminals PS1 and PS2 via resistors PR1 and PR2, respectively. The terminal A3 is connected to the terminal EN of the power supply control circuit PSC via the terminal PSE. The D / A converter DAC is a circuit that converts digital information into an analog signal, outputs digital information to an output port, and converts the digital information into an analog signal using, for example, a ladder-type resistor network (ladder network). . In the present embodiment, the D / A converter DAC is used for forming the reference pulsating wave signal VR1.

The operation of the microcontroller MCU is controlled by a program recorded in the storage unit MEM. The storage unit MEM stores information on the reference pulse wave. Furthermore, a counter for operation control (DADR,
DCNT) and flags (UDFLG, PFLG, SF)
LG, HFLG, DFLG, OFLG)
Is set to

DADR is an address counter for reading pulsating wave information, DCNT is a counter for continuous operation, and UDLFG
Is a flag for up / down control of the address counter DADR, PFLG is a polarity flag, SFL
G is a ringing request flag, HFLG is a maximum value / minimum value hold flag, DFLG is an information read flag, OF
LG is a flag indicating that data is being read.

When power is supplied to the microcontroller MCU and the microcontroller is started, the interruption time interval T0 of the timer unit TIM is set, and the terminals A1 and A2 of the input / output unit PORT are set.
Is set to "1", the terminal A3 is set to "0", and a counter and a flag for operation control are initialized (0 and "0" are set). As a result, both "1" are applied to the polarity control terminals PS1 and PS2 of the polarity control circuit PCN.
Since "0" is output to E, the operation of the power supply control circuit PSC is stopped.

When an interrupt signal INT0 is generated, OF
If LG is “1”, processing (1) is performed, and HFLG
Is "1" and DADR is 0, the operation (2) is performed. Next, the process (3) is performed, and the process for one interrupt is completed.

Processing (1) If the content of DADR is 0, if PFLG is "0", "0" and "1" are respectively applied to terminals A1 and A2,
When FLG is "1", "1" and "0" are set to terminals A1 and A2, respectively. Next, the terminal A3 is set to “1” and the PFLG is inverted. Here, the power control circuit P
The SC starts operation.

Next, the waveform data WAVE of the storage unit MEM is
, And reads the contents of the contents of the DADR from the D / A conversion unit DAC. Further, when HFLG is "0" and UD
If FLG is "0", 1 is added and stored in the contents of DADR, and if the content is NR-1 (maximum value), "1" is set in HFLG and UDFLG.

If HFLG is "0" and UDFLG is "1", 1 is subtracted from the content of DADR and stored. If the content is 0, HFLG is set to "1", and
DFLG is set to “0” and the contents of PFLG are inverted. If HFLG is "1", HFLG is set to "0". That is, HFLG is used to hold the contents of the DADR when the contents of the DADR are 0 or NR-1, and to accurately output the waveform data.

Process (2) If SFLG is "0" and DFLG is "0", DF
If LG is set to "1" and SFLG is "0" and DFLG is "1", terminals A1 and A2 of the input / output unit PORT are set.
Is set to "1", the terminal A3 is set to "0", and the counter and flag for operation control are initialized (0 and "0" are set). Thereby, the polarity control terminal P of the polarity control circuit PCN
“1” is output to both S1 and PS2, the operation returns to the initial state, and the output of the ringing signal is stopped.

Processing (3) Activation terminal RN connected to terminal A0 of input / output unit PORT
The state of G is checked, and if different from the previous state, a value Nchat is set in DCNT. If the state does not change, DCN is set.
1 is subtracted from the content of T and stored, and if the content of DCNT is 0, the state is inverted and set to SFLG. At this time, if SFLG is "1" (a request to start outputting a ringing signal), OFLG is set to "1" and DFL is set to "1".
G is set to “0”.

Therefore, in the seventh embodiment,
Every time an interrupt signal is generated in the timer device TIM, the read address for the storage device MEM is changed from the first (address 0) of the storage address of the reference pulsating wave information to N by DADR.
The operation of increasing the number in the order of (th address NR-1), or N
Since the operation of decreasing from the first to the first is performed and this operation is repeated alternately, the reference pulsation wave information read from the storage device MEM is converted into an analog signal by the DAC and is generated as the reference pulsation wave signal VR1. Further, at the time of reading by the DADR, a signal indicating the polarity is output from the terminals A1 and A2 and applied to the terminals SP1 and SP2,
The switches SW1 to SW4 are switch-controlled.

Further, since the DCNT is configured to recognize the start / stop of the ringing signal when the state of the start terminal RNG is continuous for Nchat times, malfunction due to noise included in the signal can be prevented. DADR
Is increased or decreased by one in the range of 0 to NR-1, so that the waveform data need only be prepared for 1/4 period of the sine wave, and the amount of information in the storage unit MEM can be reduced.

The output period T1 is the period T of the interrupt signal INT0.
0 and the number NR of waveform data, T1 = 4 × NR1
Because of the relationship of × T0, for example, when NR is 64, the output signal frequency can be set to 16 Hz by setting T0 to about 0.245 ms.

With this configuration, when the start terminal RNG is "1", the output terminal PSE is "0" and the main switch M1 of the switching amplifier SWA is turned on.
0 stops the switching operation, and the polarity control terminals PS1,
Since both PS2 are "1", the four switches SW1 to SW4 of the polarity reversing unit PSW are in the ON state, and the output signal (ringing signal) is 0.

When the activation terminal RNG becomes "0",
The output terminal PSE becomes “1” and the switching amplifier SW
The main switch M1 of A starts the switching operation and outputs the reference pulsating wave signal VR1, so that the pulsating wave signal is output from the switching amplifier SWA and the polarity control terminal PS
1 and PS2 output "1" and the other outputs "0" every half cycle of the sine wave. Therefore, the four switches SW1 to SW4 of the polarity reversing unit PSW are controlled to be in the on / off state, and the sine wave is output. A wavy output signal (ringing signal) is output.

Further, after this, the activation terminal RNG becomes "0".
, The output is continued for at least one cycle after the change, and the same operation as described in the fifth embodiment can be performed.

In the control circuit unit CONT of the present embodiment,
The use of the microcontroller MCU has an advantage that the number of parts can be reduced.

[Eighth Embodiment] FIG. 15 is a diagram showing a DC / AC converter according to an eighth embodiment. In particular, the control circuit unit CONT includes light emitting diodes PC1D and PC3D.
And a terminal RS2 connected to a common connection point of the light emitting diodes PC2D and PC4D.
Is provided. FIG. 16 shows the control circuit unit CONT.
The following shows a specific circuit.

In the DC / AC converter of each of the above-described embodiments, when the DC / AC converter is operated in a no-load state or a light-load state in which the load RL is not connected between the output terminals RGP and RGG, the output signal is output. There is a phenomenon that distortion increases. Therefore, when used in such a no-load state or a light-load state, it is necessary to connect a pseudo load resistor between the output terminals RGP and RGG, and there is a problem of an increase in power consumption. The present embodiment proposes a configuration that does not require a pseudo load resistance.

The cause of the waveform distortion in the output signal is that the pulse voltage generated in the secondary winding L2 of the transformer T1 is rectified by the diode D1 and smoothed by the smoothing capacitor C2 to form a pulsating wave signal. This is because if the amount of charge of the smoothing capacitor C2 via the diode D1 is larger than the amount of discharge of the load RL, the voltage of the smoothing capacitor C2 tends to increase only. As a result, the power supply control circuit PS
Even if C sets the duty ratio of the main switch M1 to 0,
A normal pulsation waveform may not be obtained. This is noticeable in the case of no load. Therefore, when outputting a ringing signal in a no-load state, it is understood that it is necessary to connect a resistor between the output terminals RGP and RGG in advance.

In FIG. 16, DLC is a pseudo load control circuit newly provided. The signal comparison circuit SCC and the polarity control circuit PCN are the same as those described in the third to sixth embodiments. The power supply control circuit PSC also has the third
To the sixth embodiment, but the output signal VER of the error amplifier AMP2 is led to a newly provided terminal ER.

In the pseudo load control circuit DLC, a diode DD1 and a resistor RD2 connected in series are connected to a differential amplifier AM.
The error signal VER of the terminal ER is connected to the negative input terminal of the terminal ER via the resistor RD1, and the voltage VL is applied to the positive input terminal. The output of the differential amplifier AMP4 is supplied to a terminal R via a resistor RD3, via diodes DD2 and DD3.
It is connected to S1 and RS2. The diode DD1 is
This is an element for adding the voltage dropped by the diodes DD2 and DD3 to the output voltage of the differential amplifier AMP4 in advance.

FIG. 17 shows the relationship between the error signal VER and the output VPW of the voltage comparator CMP2 of the power supply control circuit PSC.
Output V of ramp generator ROSC of power supply control circuit PSC
For the CT, a signal having a waveform whose voltage changes in proportion to time, such as a triangular wave signal or a sawtooth signal, is used. here,
A description will be given using a triangular wave signal as an example. Since the ramp signal VCT and the error signal VER are connected to the positive and negative input terminals of the voltage comparator CMP2, respectively, the output of the voltage comparator CMP2 is "1" when VER> VCT, It is "0" when VER <VCT.

Therefore, the operation is such that the pulse width is narrow when the error signal VER is low, and wide when the error signal VER is high, like the signal VPW in FIG. The duty ratio is a ratio between the pulse width and the cycle of the output signal VPW. Error signal V
FIG. 18 shows the relationship between the ER size and the Deute ratio. The duty ratio is proportional to the voltage of the error signal VER in a range where the error signal VER is higher than the voltage VL and lower than the voltage VH, but is 0% when the error signal VER is lower than VL and 100 when the error signal VER is higher than VH.
%. These voltages VH and VL are
Corresponds to the maximum voltage and the minimum voltage of the ramp signal VCT shown in FIG.

Here, the error signal VER is a signal obtained by amplifying and inverting the difference voltage VSI between the ringing signal VSG formed by the error amplifier AMP1 of the signal comparison circuit SCC and the reference pulsating wave signal VR1. Therefore, the error signal VER
Is a high voltage means that the ringing signal VRG is lower than the reference pulsating wave signal VR1, and acts to increase the duty ratio to increase the output voltage. Also, the fact that the error signal VER is at a low voltage means that
This means that the ringing signal VRG is higher than the reference pulsating signal VR1, and acts to reduce the duty ratio to reduce the output voltage.

In particular, when the voltage of the error signal VER is lower than the voltage VL, the duty ratio is 0 and the switching operation of the main switch M1 is stopped. Even if a pseudo load resistor is connected, the DC / AC converter does not consume any new power. In addition, it means that the voltage of the ringing signal VRG is higher as the error signal VER is lower than the voltage VL, and it can be seen that a load proportional to the difference voltage between the voltage VL and the error signal VER should be connected.

The pseudo load control circuit DLC shown in FIG. 16 is a circuit for detecting and amplifying a voltage corresponding to a difference voltage between the voltage VL and the error signal VER as described above. The error signal VER is guided to the negative input terminal of the differential amplifier AMP4.
The output of P4 becomes a high voltage, and operates such that the pseudo load current output via the resistor RD3 increases. On the other hand, when the error signal VER is higher than the voltage VL, the output of the differential amplifier AMP3 becomes substantially 0 V, and the resistor RD
The pseudo load current output via 3 is substantially zero.

The pseudo load current output via the terminals RS1 and RS2 is supplied to the photocoupler of the polarity reversing unit PSW. Is in the ON state, and the light emitting diode for turning on each switch is provided with the control circuit unit CON.
A current is supplied from one of the T polarity control terminals PS1 and PS2.

If the switches SW2 and SW4 are turned on, the current flowing to the light emitting diodes PC1D and PC3D is 0, so that the pseudo load current supplied to the terminal RS1 flows to the light emitting diode PC3D. The light does not flow in the opposite direction to the light emitting diode PC1D. Therefore,
A current flows through the path from one end GP of the smoothing capacitor C2 to the switch SW2 to the switch SW3 to the other end GN of the smoothing capacitor C2, and acts to lower the voltage EC2 of the smoothing capacitor C2.

The magnitude of the current flowing through this path is a current corresponding to the above-described error signal VER, and although the voltage of the ringing signal VRG decreases, the pseudo load supplied from the terminal RS1 before the voltage decreases too much. The current decreases to zero.

[0144] Since the configuration and operation are performed as described above, when a load having a sufficient magnitude is connected between the output terminals RGP and RGG, the polarity inversion unit PSW acts only on the polarity inversion.
When the load is light or no load, the control circuit CON
The pseudo load current of T acts so that a current flows through the switch in the off state of the polarity reversing unit PSW (the switch is controlled to an intermediate state between on and off), so that in a state where a steady load is connected. And the output waveform distortion under light load and no load can be reduced.

[0145]

[0146]

As described above, according to the present invention, a main pulsating wave signal corresponding to a waveform obtained by full-wave rectification of a sine wave signal is generated in a switching amplifier, so that a parasitic capacitance around a transformer, which is one factor of power consumption, is generated. Can be reduced, the transformer can also use two windings, and the polarity reversing part can be constituted by a switch element. Therefore, loss is reduced, power consumption can be reduced, and power conversion efficiency can be increased.

When the start signal is set for starting, the output of the AC output signal starts from 0 V, and when the start signal is set for stopping, the output stops at 0 V. No voltage is applied. Further, when set to stop, the AC output signal can be continued for one cycle or more, and in this case, when a PNPN element is used as the switch element, it can be reliably turned off.

When the duty of the pulse width conversion means is 0,
Alternatively, when the load is close to zero and there is no load or light load, the switch whose polarity inversion unit is off is turned on and a pseudo load is added, so that output distortion can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a DC / AC converter according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram of the device of FIG.

FIG. 3 is a block diagram of a DC / AC converter according to a second embodiment.

FIG. 4 is an operation waveform diagram of the device of FIG. 3;

FIG. 5 is a circuit diagram of a DC / AC converter according to a third embodiment.

6 is a block diagram of a control circuit unit of the device shown in FIG.

FIG. 7 is an operation waveform diagram of the device according to FIGS. 5 and 6;

FIG. 8 is a block diagram of a control circuit unit of a DC / AC converter according to a fourth embodiment.

9 shows an operating waveform diagram of the device according to FIG.

FIG. 10 is a block diagram of a control circuit unit of a DC / AC converter according to a fifth embodiment.

FIG. 11 is an operating waveform diagram of the device according to FIG. 10;

FIG. 12 is a block diagram of a control circuit unit of a DC / AC converter according to a sixth embodiment.

FIG. 13 is an operating waveform diagram of the device according to FIG.

FIG. 14 is a block diagram of a control circuit unit of a DC / AC converter according to a seventh embodiment.

FIG. 15 is a circuit diagram of a DC / AC converter according to an eighth embodiment.

16 is a block diagram of a control circuit unit of the device shown in FIG.

FIG. 17 is an explanatory diagram of a pulse width conversion operation.

FIG. 18 is a characteristic diagram showing a relationship between an error signal and a duty ratio.

FIG. 19 is a circuit diagram of a conventional DC / AC converter.

20 is a circuit diagram of the amplifier of the device of FIG.

21 is a waveform diagram of the output voltage of the device of FIG.

[Explanation of symbols]

PSC: power supply control circuit, RGA: amplifier, SWA: switching amplifier, PSW: polarity inversion unit, CONT: control circuit unit, SCC: signal comparison circuit, PCN: polarity control circuit, PSC: power supply control circuit (pulse width conversion circuit ), DL
C: pseudo load control circuit.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-32263 (JP, A) JP-A-5-76179 (JP, A) JP-A-8-33355 (JP, A) JP-A-8-333 331855 (JP, A) JP-A-7-143756 (JP, A) JP-A-8-214554 (JP, A) JP-A-6-9384 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 7/48 H02M 3/28

Claims (6)

(57) [Claims] An AC power is generated on a secondary side of the transformer by switching a supplied DC power by a main switch on a primary side of a transformer, and the AC power is rectified and smoothed to substantially provide a full sine wave. a polarity inversion unit having a switching amplifier for generating midrib flow wave signal corresponding to the wave rectified waveform, the switching element for generating an AC output signal by the polarity inverting the midrib flow wave signal every period, a full-wave rectifier A reference pulsation wave signal that generates a waveform reference pulsation wave signal
Signal generation means, full-wave rectification of the output signal of this device and return pulsation
Return pulsating wave signal generating means for generating a wave signal, the reference pulse
Difference signal corresponding to the difference between the pulsating wave signal and the return pulsating wave signal
Detecting means for generating the error signal, and a signal level of the error signal
A pulse that generates a high-frequency pulse with a duty ratio according to the
A DC / AC converter having a width conversion means , and a control circuit section for driving the main switch on / off by the high frequency pulse. 2. The DC / AC converter according to claim 1,
AndThe reference pulsating wave signal generating means of the control circuit unit is provided with a sine wave signal.
Signal generation means, and the output signal of the sine wave signal generation means
And a full-wave rectifier for rectifying the sine.
Duty ratio synchronized with the output signal of the
Pulse conversion means for generating a pulse of about 50%; The polarity inverting section corresponding to the output signal of the pulse converting means;
To control the polarity reversal of the main pulsating wave signal in
Was  A DC / AC converter characterized by the above-mentioned. 3. The DC / AC converter according to claim 2,
AndThe reference pulsating wave signal generating means, Full-wave sine wave signal
N pulses for a half cycle of the reference pulsating wave signal waveform formed by flowing
Storage device storing the reference pulsation wave information, and the storage device
The read address for the reference pulsating wave information is stored in the storage address.
First reading means for increasing from the first to Nth
And a read address for the storage device. Less than the above criteria
Decrease in order from Nth to 1st of storage address of pulse wave information
The second reading means for reducing
Continuation operation and read operation by the second read means
Repetition means to repeat the operation alternately, and at predetermined time intervals
The first or second reading means when an interrupt signal is generated.
Converts the reference pulsation wave information read in the step into an analog signal
Digital / analog converting and generating reference pulse wave signal
Replace with another reference pulsating wave signal generating means equipped with a converting means
And The pulse conversion means, At the time of reading by the first reading means and at the time of reading by the second
Means for outputting polarity information at the time of reading by the reading means
And the first information reading by the second reading means.
Later, when the polarity information is “1”, it is set to “0”,
A polarity reversing means for reversing to "1" when it is "0"
Replaced with another pulse conversion means provided,  A DC / AC converter characterized by the above-mentioned. 4. The DC / AC converter according to claim 2 , wherein when the start signal is set for starting, the pulse conversion operation is performed.
The edge of the pulse obtained by the stage is detected later.
The DC / AC conversion operation is performed by operating the control circuit unit.
When the start signal is set for stop,
Edge of pulse obtained by pulse conversion means is detected afterwards
When the main switch is controlled to be inactive by
Both switch elements of the polarity reversing unit are turned on.
A DC / AC conversion device comprising a start / stop control means for setting . 5. The DC / AC converter according to claim 4, wherein said start / stop control means controls said start signal to stop.
When the pulse is obtained by the pulse conversion means,
When an even number of edges are detected thereafter, the main switch is detected.
Control the switch to non-operation and switch the polarity inverting section.
A DC / AC converter operable to set all of the switch elements to an ON state . 6.A DC / A according to any one of claims 1 to 5.
In the C converter, The polarity inverting unit is obtained from the switching amplification unit.
The main pulsating wave signal Output to output terminal with polarity
A first switch group and the main pulsating wave signal are inverted in polarity.
A second switch group for outputting to the output terminal, The duty ratio of the pulse width conversion means is 0 or close to 0
Ratio detection means for detecting that The duty ratio is 0 or 0 by the duty ratio detecting means.
Is detected, the first or second is detected.
Of the switches that are currently off,
At least one switch is controlled to an intermediate state between ON and OFF.
To A DC / AC converter characterized by the above-mentioned.