JP3288298B2 - Absolute phase detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute phase detecting circuit for detecting an absolute phase of a synchronous pattern or a burst pattern detected from a digital phase modulation signal.

[0002]

2. Description of the Related Art In a digital phase modulation system, data transmission is performed by changing the phase of a carrier at equal intervals. In BPSK (two-phase shift keying), the phase is changed to 0 degrees and 180 degrees, and the phase is changed to 1,0.
Is assigned, as shown in FIG.
One bit of data can be transmitted per baud. QPSK
45 degrees, 135 degrees, 1 phase shift keying
80, 225 and 315 degrees phases 00, 01, 1
By assigning 1 and 10, 2 bits of data can be transmitted per baud as shown in FIG. Similarly, in 8PSK (8 phase shift keying), as shown in FIG. 7C, 3 bits of data can be transmitted with 8 phases per baud.

As a related prior art, Japanese Patent Laid-Open No.
There is a "digital angle modulation signal demodulation circuit" described in JP-A-341034 and a "phase modulation signal demodulation method" described in JP-A-8-317005.

[0004]

Input data of the digital phase modulator [0006] is assumed to have a pattern as shown in FIG. After the synchronization pattern 21, the data 22 and the burst pattern 26 alternately follow. Sync pattern and burst pattern are BPSK, data is BPSK, QPSK or 8
When modulated by PSK and carrier reproduction is performed by 8PSK, the carrier is π / 4 × n (n = 0, 1,.
Lock to 8 phases of 7). When a BPSK pattern exists at, for example, 0 degree as viewed from the 8PSK carrier, the signal points are distributed within a predetermined circle. However , 8PSK
Even if the carrier is locked at 45 and 315 degrees,
There is a high possibility that the same BPSK pattern as in the case where the PSK carrier is locked at the position of 0 degrees is detected. As described above, the same BPSK pattern is detected with respect to the phases of a plurality of carriers, and it is difficult to determine the correct phase of the carrier by determining the detected BPSK pattern.

The present invention provides an absolute phase detection circuit for stably detecting the absolute phase of a detected synchronization pattern or burst pattern even when data transmitted by a digital phase modulation method is spread at a low C / N. Its purpose is to

[0006]

An absolute phase detection circuit according to the present invention inputs an in-phase component and a quadrature component detected from a digital phase modulation signal, and calculates an angle of a vector on a phase plane formed by the in-phase component and the quadrature component. A demapping means for detecting an angle range to which the angle range belongs and outputting an angle detection signal corresponding to the angle range; and detecting the synchronization pattern for each angle range by inputting the angle detection signal and detecting a synchronization pattern for each angle range. A synchronous pattern detecting means for outputting a signal; and a frequency counting means for detecting an absolute phase by counting the frequency of the synchronous pattern detection signal for each angle and outputting an absolute phase signal.

Further, the absolute phase detecting circuit according to the present invention
The absolute phase detection circuit further includes a synchronization establishment determining unit that determines synchronization based on the synchronization pattern detection signal, and outputs a synchronization establishment signal when synchronization is established. An establishment signal is also used for the counting.

Further, the absolute phase detection circuit according to the present invention
An in-phase component and a quadrature component detected from the digital phase modulation signal are input, an angle range to which an angle of a vector on a phase plane formed by the in-phase component and the quadrature component belongs is detected, and an angle detection signal corresponding to the angle range is detected. A demapping means for outputting, an input of the angle detection signal, a burst pattern detection means for detecting a burst pattern for each angle range and outputting a burst pattern detection signal for each angle range, And a frequency counting means for detecting an absolute phase by counting the frequency and outputting an absolute phase signal.

Further, the absolute phase detection circuit according to the present invention
In the above-described absolute phase detection circuit, further, a synchronization pattern detection unit that receives the angle detection signal, detects a synchronization pattern for each angle range, and outputs a synchronization pattern detection signal for each angle range, And a synchronization establishment determining unit for outputting a synchronization establishment signal when synchronization is established, wherein the frequency counting means also uses the synchronization establishment signal for the counting.

Further, the absolute phase detection circuit according to the present invention
In the above absolute phase detection circuit, the demapping means includes a plurality of comparators and a logic gate for logically synthesizing outputs of the plurality of comparators.

Furthermore, the absolute phase detection circuit according to the present invention
In the above-described absolute phase detection circuit, the frequency counting means includes a counter for each synchronization pattern detection signal in each angle range, a comparison means for detecting that the count value of the counter has reached a predetermined value, And an encoder for encoding the absolute phase based on the output of

Further, the absolute phase detection circuit according to the present invention
In the above-described absolute phase detection circuit, the synchronization pattern detection unit includes a shift register that converts an angle detection signal for each angle range from serial to parallel, and a unit that compares an output of the shift register with the synchronization pattern. It is characterized by.

Further, the absolute phase detection circuit according to the present invention
In the above-described absolute phase detection circuit, the burst pattern detection unit includes a shift register that converts an angle detection signal for each angle range from serial to parallel, and a unit that compares an output of the shift register with the burst pattern. It is characterized by.

[0014]

In FIG. 1, I and Q data are 8PSK (8-phase shift keying) and QPSK (4
Phase shift keying) and data transmitted by a plurality of modulation schemes of BPSK (two-phase shift keying) and include a synchronization pattern modulated by the BPSK modulation scheme. I is the in-phase component and Q is the quadrature component. As shown in FIG. 2, the demapping unit 1 according to the angle range
When the coordinate indicated by Q is in the range where 1 in FIG. 2A is mapped, the angle detection signal of 0 degree is set to 1 and
If it is out of the range, it is set to 0 and output. Similarly, FIG.
(B) When the 1 is within the mapping range, the 45 ° angle detection signal is set to 1 and output, and when it is outside the range, it is set to 0.
2 (c), the 90 ° angle detection signal is set to 1 when it is in the mapping range, and is set to 0 when it is out of the range. The angle detection signal of 135 degrees is set to 1 when it is in the range where 1 is mapped, and is output as 0 when it is out of the range. The synchronization pattern detection unit 2 is provided with 0 degree, 45 degree, 90 degree,
Synchronization pattern matching is detected for the 135-degree angle detection signal, and 0-degree, 45-degree, 90-degree, and 135-degree synchronization pattern detection signals are output. 0 degree, 45 degree, 90 degree,
The coincidence of the inverted synchronization pattern is detected for the 135-degree angle detection signal, and the detection is performed at 180 degrees, 225 degrees, and 270 degrees, respectively.
And outputs a synchronous pattern detection signal of 315 degrees. The logical sum of these synchronization pattern detection signals is calculated by a logical sum gate and input to the synchronization establishment determining unit 4. The synchronization establishment determining unit (flywheel) 4 detects the temporal position of the synchronization pattern based on the output of the OR gate, and if synchronization pattern detection signals of the same phase are continuous, the synchronization pattern counting unit 3
To activate (High) the synchronization establishment signal to be output to. The synchronization pattern counting unit 3 has 0, 45, 90,
A counter is provided for each of the 135 °, 180 °, 225 °, 270 °, and 315 ° synchronous pattern detection signals, and the corresponding synchronous pattern detection signal is generated at the synchronous pattern detection timing indicated by the synchronization establishment signal. When activated, each counter is incremented. When the count value of any one of the eight counters reaches a predetermined value, the increment of all the counters is stopped. It determines that the angle of the counter whose count value has reached the predetermined value is the absolute phase, and outputs an absolute phase signal containing the information.

A logic circuit that combines a synchronization establishment signal and a synchronization pattern detection signal inside a synchronization gate, a synchronization establishment determination unit 4 and a synchronization pattern counting unit 3 for obtaining a logical sum of the synchronization pattern detection signal is an absolute circuit. This is for improving the reliability of the phase signal, and is not necessarily required.

[0016]

[Embodiment 1] Embodiment 1 will be described with reference to FIG.

The angle range demapping unit 1 includes size comparison circuits 8, 9, 10, and 11, logic inversion gates, and AND gates. The size comparison circuit 8 detects that I is a negative number, and 9 detects that Q is negative,
The magnitude comparison circuit 10 detects that Q is smaller than -I,
The magnitude comparison circuit 11 detects that Q takes a value smaller than I. 0 °, 45 °, 90 ° created by combining these results with a logical inversion gate and a logical AND gate
Angle detection signal of 135 degrees, the synchronous pattern detection unit 6
output to a.

The synchronous pattern detection unit 2 a includes a shift register 12 a to 12 d, synchronous pattern detection comparator 13a~1
3d, and includes inverted sync pattern detection comparators 14a to 14d. The synchronization pattern detection comparator 13a detects a synchronization pattern and outputs a 135-degree synchronization pattern detection signal in response to input of 135-degree data, and the inversion synchronization pattern detection comparator 14a outputs a 135-degree data input signal. Then, the inverted synchronization pattern is detected and a 315-degree synchronization pattern detection signal is output. Similarly, the synchronous pattern detection comparator 1
3b is a 45-degree synchronization pattern detection signal, the inverted synchronization pattern detection comparator 14b is a 225-degree synchronization pattern detection signal, the synchronization pattern detection comparator 13c is a 90-degree synchronization pattern detection signal, and the inverted synchronization pattern detection comparator 14c is 2
The 70-degree synchronization pattern detection signal, the synchronization pattern detection comparator 13d outputs a 0-degree synchronization pattern detection signal, and the inverted synchronization pattern detection comparator 14d outputs a 180-degree synchronization pattern detection signal. These synchronization pattern detection signals are output to the synchronization pattern counting section 3.

The synchronous pattern counter 3 is a logical product gate 1 for controlling the counter 16 and an enable signal of the counter.
A logic circuit comprising 5, 19, 17 and an inverted output OR gate 20, and an absolute phase signal encoder circuit 18 are provided.
Note that the output of the AND gate 17 is also input to the absolute phase information encoder 18. AND gate 17 is counter 1
The inverted output OR gate 20 detects that the count value of the counter 16 has reached the maximum value by calculating the logical product of all the bits of the output of the counter 6 and the inverted output OR gate 20 has reached the maximum value. Detect that. The absolute phase signal encoder 18 is a circuit that determines and encodes which phase has detected the most synchronization pattern, and outputs the determination result as an absolute phase signal.

Next, the operation will be described.

In FIG. 3, the data I and Q input to the demapping unit 1 based on the angle range are a synchronization pattern 21 modulated by BPSK as shown in FIG. 4 and the following data 22 of BPSK, QPSK and 8PSK. And has a frame structure with a constant period.

Demapping unit 1 based on the angle range shown in FIG.
Is a circuit for demapping the "range where 1 is mapped" in FIG. 2 as 90 degrees. Size comparison circuit 8, 9, 10, 1
1 to detect that I takes a negative value, Q
Takes a negative value, detects that Q is smaller than -I, and detects that Q is smaller than I. The result is Q
When <-I and Q <I, 1 is output as 0-degree data, and otherwise 0 is output. I <0 and Q <0
In this case, 1 is output as 45-degree data, and otherwise, 0 is output. When Q <-I and Q <I, 1 is output as 90-degree data, and otherwise, 0 is output.
When I <0 and Q <0, 1 is output as 135-degree data, and otherwise 0 is output. The data demapped at each of these angles is sent to the synchronization pattern detection unit 2.
output to a.

Table 1 shows the magnitude comparison circuits 8, 9, 10, 11
Indicate conditions for outputting 1 for data having a value of 1 at each angle.

[0024]

[Table 1] In the synchronous pattern detection unit 2a, each angle detection signal is input to the shift registers 12a to 12d, and converts from serial to parallel. Synchronous pattern detection comparators 13a to 13
d indicates that the synchronization pattern detection signal is 1 when the parallel-converted angle detection signal matches the synchronization pattern 21 in FIG.
And outputs the inverted synchronous pattern detection comparators 14a to 14a.
Each of 4d sets the synchronous pattern detection signal to 1 and outputs it when the parallel converted angle detection signal matches the inverted synchronous pattern 21. Each angle (0 degree, 45 degree, 9
0 degree, 135 degree, 180 degree, 225 degree, 270 degree, 31
The sync pattern detection signal (5 degrees) is input to the sync pattern counting unit 3.

The synchronization pattern counting section 3 has a counter 16 for the synchronization pattern detection signal of each angle, and each of the counters 16 detects when a pattern is detected at the synchronization pattern detection timing indicated by the synchronization establishment signal. Incremented. The AND gate 17 takes the AND of all the bits of the output of the counter 16 to obtain the counter 16.
Is detected to have reached the maximum value, and when any one of them has reached the maximum value, the increment is stopped by inactivating the enable signal of the counter 16.
When the increment stops, the angle corresponding to the counter 16 whose counter value has reached the maximum value is the absolute phase.

Embodiment 2 Embodiment 2 will be described with reference to FIG.

The format of the input data I and Q in FIG. 5 is the same as that shown in FIG.
And a burst pattern 26 modulated by BPSK is inserted at a predetermined position in the frame. The synchronization pattern detector 2b simultaneously detects the synchronization pattern and its inversion and the burst pattern and its inversion for the data at each angle, and outputs the synchronization pattern detection result to the synchronization establishment determiner 4.
To enter. The synchronization establishment determining unit 4 establishes synchronization and outputs a synchronization establishment signal to the synchronization pattern counting unit 3. In this way, the number of detections of the pattern transmitted by the BPSK modulation method inserted at a predetermined position in the frame is counted, and the number of times of detection of the synchronous pattern is compared with the first embodiment in which the number of detections of the synchronization pattern is counted. This has the effect of reducing time.

[Embodiment 3] In Embodiments 1 and 2,
Although the angle range of the demapping unit 1 based on the angle range is π / 2, by changing this to π / 4, ± π / 4
Can be further reduced.

[0029]

As described above, according to the present invention,
Even when data is spread at low C / N, the synchronization pattern or burst pattern detected at the shifted phase is obtained by demapping the synchronization pattern or burst pattern of BPSK to have a certain angle range instead of the 180 degree range. Since the phase shift of the pattern can be detected in a predetermined angle unit (45 ° unit in the embodiment), the phase shift can be used to correct or control the detection phase of the synchronization pattern or the burst pattern, or to modulate by QPSK or 8PSK. It is possible to control the demodulation of the data that has been performed.

If the absolute phase is detected, the absolute phase signal can be continuously detected by resetting the counter 16 after sampling the absolute phase signal by a sampling circuit (not shown).

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an absolute phase detection circuit according to an embodiment of the present invention.

FIG. 2 is a phase plan view for explaining the operation of the demapping unit according to the angle range of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an absolute phase detection circuit according to the first embodiment of the present invention.

FIG. 4 is a format diagram of data input to the absolute phase detection circuit of FIG. 1 or 2;

FIG. 5 is a block diagram illustrating a configuration of an absolute phase detection circuit according to a second embodiment of the present invention.

FIG. 6 is a format diagram of data input to the absolute phase detection circuit of FIG. 5;

FIG. 7 is a phase plan view for explaining a phase modulation signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Demapping part according to an angle range 2 Synchronization pattern detection part 3 Synchronization pattern counting part 4 Synchronization establishment judgment part

Claims (8)

(57) [Claims] 1. An in-phase component and a quadrature component detected from a digital phase modulation signal are input, and an angle range to which an angle of a vector on a phase plane formed by the in-phase component and the quadrature component belongs is detected to correspond to the angle range. A demapping unit that outputs a detected angle detection signal, a synchronization pattern detection unit that receives the angle detection signal, detects a synchronization pattern for each angle range, and outputs a synchronization pattern detection signal for each angle range, Frequency counting means for detecting the absolute phase by counting the frequency of each angle of the detection signal and outputting the absolute phase signal. 2. The absolute phase detection circuit according to claim 1, further comprising: a synchronization establishment determining unit that determines synchronization establishment based on the synchronization pattern detection signal and outputs a synchronization establishment signal when synchronization is established. An absolute phase detection circuit, wherein the frequency counting means also uses the synchronization establishment signal for the counting. 3. An in-phase component and a quadrature component detected from a digital phase modulation signal are input, and an angle range to which an angle of a vector on a phase plane formed by the in-phase component and the quadrature component belongs is detected and corresponds to the angle range. A demapping unit that outputs a detected angle detection signal; a burst pattern detection unit that receives the angle detection signal, detects a burst pattern for each angle range, and outputs a burst pattern detection signal for each angle range; Frequency counting means for detecting the absolute phase by counting the frequency of each angle of the detection signal and outputting the absolute phase signal. 4. A synchronous pattern according to claim 3, further comprising: inputting said angle detection signal, detecting a synchronization pattern for each angle range, and outputting a synchronization pattern detection signal for each angle range. Detecting means for determining synchronization establishment based on the synchronization pattern detection signal, and a synchronization establishment determination unit for outputting a synchronization establishment signal at the time of synchronization establishment, wherein the frequency counting means also includes the synchronization establishment signal in the counting. An absolute phase detection circuit characterized by being used. 5. The absolute phase detection circuit according to claim 1, wherein said demapping means comprises:
An absolute phase detection circuit comprising: a plurality of comparators; and a logic gate for logically combining outputs of the plurality of comparators. 6. The absolute phase detection circuit according to claim 1, wherein said frequency counting means includes a counter for each synchronization pattern detection signal in each angle range and a count value of said counter. And an encoder for encoding the absolute phase based on the output of the comparing means. 7. The absolute phase detection circuit according to claim 1, wherein said synchronization pattern detection means includes: a shift register for converting an angle detection signal for each angle range from serial to parallel; and an output of said shift register. And means for comparing the synchronization pattern with the synchronization pattern. 8. The absolute phase detection circuit according to claim 3, wherein said burst pattern detection means includes a shift register for converting an angle detection signal for each angle range from serial to parallel, and an output of said shift register. Means for comparing with a burst pattern.