JP3287461B2 - Variable length code decoding method and apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital signal processing for performing variable length coding based on the regulations of MPEG and the like, and more particularly to a variable length code decoding method and apparatus for decoding variable length codes.

[0002]

2. Description of the Related Art In general, in an image and audio compression encoding apparatus, an input time-domain signal is subjected to an orthogonal transform,
For example, after transforming into a coefficient in the frequency domain by discrete cosine transform and quantizing, the code is assigned. In this code allocation, in order to improve the compression efficiency, variable-length coding that changes the code length according to the probability of occurrence frequency is often performed. Examples of compression methods include ISO / IEC (Internat
ional Standard Organization / International Electrot
Chemical Commission) MP defined by 13818-7
EG-2 / AAC (Moving Picture Experts Group-Pha
se 2 / Advanced Audio Coding).

[0003] Decompression of a compressed signal requires an operation of converting a variable-length coded bit string into a decoded word.
An example of a variable-length code decoding device is disclosed in Japanese Patent Application Laid-Open No. 9-307456.
No., published in Japanese Unexamined Patent Publication No.

FIG. 5 is a diagram showing a configuration of a variable-length code decoding device described in the above publication. This variable-length code decoding device includes:
Control unit 499, register file 500, selector 50
1, selector 502, priority encoder 503,
It comprises a barrel shifter 504, an ALU 505, a selector 506, and a data RAM 507. This hardware configuration is a configuration in which a priority encoder 503 and a barrel shifter 504 are added to a data path section in a general-purpose microcomputer. The decoding operation of a variable-length code is performed by executing a microprogram describing the processing contents. Is achieved. Although not explicitly shown in FIG. 5,
A variable code bit string is input through signal lines input to both the priority encoder 503 and the ALU 505.

[0005] In the figure, a priority encoder 503 detects the length of a bit sequence in which a certain logical value continues from the beginning of a variable-length code bit sequence. Here, a bit string that is a continuation of a certain logical value is called a run. Data RA
M507 stores a decoded word corresponding to the bit string following the run. The number of bits of the address of the data RAM 507 is equal to the maximum length of the bit string following the run. To obtain a decoded word, the ALU 505 and the barrel shifter 504 output from the data RAM 507 the bit pattern of the variable-length code bit string cut out by the number of bits of the bit string following the run as an address.

FIG. 2 is a diagram showing an example of a variable length code in MPEG-2 / AAC. The operation of the conventional variable-length code decoding device shown in FIG. 5 will be described in detail with reference to the example shown in FIG. In the notation of a code value, a value enclosed by "" is a binary number, and a value enclosed by "" is a decimal number. In the example of the variable length code shown in FIG. 2, the length of the logic "1" is the run length, and the maximum length of the bit pattern after the logic "0" in which the logic "1" is inverted is the code number 7 to 10 and the code number Since it is 4 bits of 13 to 15, the data RAM 507
Is as shown in FIG.

In FIG. 6, the run length is the length of logical "1" following the head of the bit string, and the bit pattern is a 4-bit code pattern following the run. The dashed line shown in the bit pattern of FIG. 6 is the actual variable-length code bit string from the upper part to the dashed line part, and additional bits for adjusting the bit length after the dashed line part. Assuming that the input variable-length code bit string is “101111000”, the run length “1” is detected by the priority encoder 503 and a partial table of “1” in the data RAM 507 is specified. In the partial table, 4-bit "0111", which is the maximum length of the bit pattern following the run, is given as an address, and the decoded word "3" can be obtained from the table.

As is apparent from FIG. 6, in the conventional variable length code decoding apparatus, the data RAM for the table for obtaining the decoded word uses L as the maximum bit pattern length of all the variable length code words. In this case, the number of words is (2 to the power of L) × run length.

In Huffman coding, multi-dimensional coding may be used instead of one-dimensional coding. In this case, one decoded word corresponds to a plurality of quantization coefficients. M
In the example of PEG-2 / AAC, one decoded word corresponds to two or four quantization coefficients. In one example, the decoded word A and the quantization coefficients w, x, y, z have the following relationship.

A = w × 27 + x × 9 + y × 3 + z The values of the quantization coefficients w, x, y and z are 0, 1, or 2. Therefore, from the decoded word A, the quantization coefficient w,
In order to obtain x, y, and z, the following division calculation is required. 	 w = A ^ 27 ... remainder B 	 x = B ^ 9 ... remainder C 	 y = C ^ 3 ... remainder D 	 z = D Decoding as in the above equation To find four quantization coefficients from word A, three divisions must be performed.

[0011]

In a conventional variable length code decoding apparatus, a table is constituted by the maximum length of a portion called a bit pattern excluding a run length connected by the same logical value from the beginning of a variable length code word. The table must be prepared for the number of run lengths. For example, in the case of a conversion table of amplitude information (scale factor) used in MPEG-2 / AAC, which is an international standard for audio coding, the maximum length of a bit pattern is 6, and the type of run length is 20. In this case, the capacity of the data RAM required for the table is (2 6) × 20 = 1280 words. The minimum required capacity of the table is equivalent to the number of decoded words, and the number of decoded words of the scale factor is 121.
More than twice the table capacity is required. For this reason, there is a problem that the capacity of the data RAM required for the table for obtaining the decoded word must be increased.

Further, in the conventional variable-length code decoding apparatus, it is assumed that all codewords are converted and operated by detecting the run length, and the variable-length code consisting of only the same logical value from the head is converted. Therefore, when a run length is detected and decoded, a variable length code consisting only of the same logical value from the beginning, such as “111111”, sets the run length to “0”. By detecting, correct conversion and decoding cannot be obtained, and a malfunction may occur.

Further, the decoded word of MPEG-2 / AAC is:
Since two or four coefficients are superimposed, there is a problem that a remainder operation must be performed on the decoding result.

(Object of the Invention) It is an object of the present invention to provide a variable length code decoding method and apparatus capable of reducing the capacity of a decoding table memory for obtaining decoded words.

Another object of the present invention is to provide an MPEG-2 / AA
In variable length code decoding of audio coding such as C,
It is an object of the present invention to provide a variable-length code decoding method and apparatus capable of reducing the amount of calculation required for remainder calculation.

[0016]

A variable length code decoding method according to the present invention is directed to a variable length code decoding method for decoding a variable length code bit sequence consisting of a run of the same logical value continuing from the head and a bit sequence following the run. A primary decoding table memory in which a specific bit string following a run is stored in advance for each run length as a reference code, and a code number of the reference code (reference address) is stored; And a secondary decoding table memory storing words (for example, a multidimensional code), detects a run length of the input variable-length code bit string, and, based on the run length, a corresponding reference code and a corresponding reference code from the primary decoding table memory. The code number of the reference code is output, and the difference between the reference code and the code of the bit string following the run of the input variable-length code bit string, and the code number of the reference code Calculating the code number of al the input variable length code bit string, and outputs the decoded word from said second decoding table memory based on the calculated the code number. The primary decoding table memory of the variable length code decoding method stores a reference code, a code number and a bit length of the reference code in the same code length unit of a code of a bit string following a run, and stores the input variable length. The calculation of the code number of the code is performed by searching for the original reference code by extracting the bit sequence following the run of the input variable-length code bit sequence by the bit length of the reference code and comparing it with the reference code, and using the reference code. It is characterized in that it is calculated.

A variable-length code decoding apparatus according to the present invention decodes a variable-length code bit string consisting of a run of the same logical value continuing from the beginning and a bit string following the run. A priority encoder (100 in FIG. 1) for detecting a run length more;
A primary decoding table memory that outputs a specific code of the same code length unit of a code following a run as a reference code using the run length and the output of the controller as an address, and outputs a code number and a bit length of the reference code. (10 in FIG. 1)
2) a bit mask shifter (101 in FIG. 1) for cutting out a bit string of a variable length code bit string based on the run length and the bit length of the reference code output from the primary decoding table memory; An arithmetic unit for calculating the code number of the input variable-length code bit string from the difference between the reference code and the reference code (the subtractor 103 in FIG. 1);
105), a secondary decoding table memory (104 in FIG. 1) that outputs a decoded word using the code number of the input variable-length code bit string as an address, and a primary decoding table memory based on the difference between the code of the bit string and the reference code. And the controller (104 in FIG. 1) which outputs the switching address of

The arithmetic unit includes a first subtractor for comparing the code of the bit string output from the bit mask shifter with the reference code output from the primary decoding table memory, and a primary decoding table. A second subtractor for subtracting the output of the first subtractor from the reference code (reference address) output from the memory can be used. Then, the controller can be configured to switch the address of the primary decoding table memory according to the sign of the output of the first subtractor.

[0019] Further, when the output value of the priority encoder is larger than a predetermined value for the variable-length code bit string composed of only codes of the same logical value, the controller decodes the secondary decoding table memory. Input
Forcibly switching to an address corresponding to a decoded word of a code bit string composed of only codes of the same logical value.

[0020] The secondary decoding table memory is characterized in that a multidimensional code is directly stored as a decoded word. Further, the secondary decoding table memory stores the number of words equal to the number of decoded words.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Explanation of Configuration) Next, an embodiment of a variable length code decoding method and apparatus according to the present invention will be described with reference to FIGS.
This will be described in detail with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of the present invention. This embodiment includes a priority encoder 100, a bit mask shifter 101, a primary decoding table memory 102, a subtractor 103, a controller 104, a subtractor 105, and a secondary decoding table memory 106. The operation of the circuit in the embodiment shown in FIG. 1 is based on the characteristic of the variable length code described below.

FIG. 2 is a diagram showing a variable length code. Looking at the variable length code shown in FIG. 2, it can be seen that the code length is almost determined by the run length. For example, when the run length is 1, the code length is 4, and when the run length is 2, the code length is 5 or 6.
It is. In the latter case, the 3-bit bit string following the run is based on “001” in code number 6 and “0”.
01 ", the code length is 5 when the value is equal or smaller, and the code length is 6 when the value is larger than" 001 ".
It is.

The variable length codes in FIG. 2 are arranged with numbers (code numbers) in ascending order of value (variable length code value). The difference between variable length code values and the difference between code numbers are equal. Therefore, a reference code (also referred to as a reference code) is obtained by referring to the table from the run length, and the code number (also referred to as a reference address) of the reference code is added to the difference between the reference code and the variable-length code value, thereby performing decoding. The code number (also called an address) of a word can be determined.

Next, the basic operation of each section of this embodiment shown in FIG. 1 will be described.

The priority encoder 100 detects a run length following the same logical value from the beginning from the input variable length code bit string 11 and outputs an encoded value 12. For example, a continuous value of "1" is detected by the priority encoder. Assuming that a variable length code bit string of “110...” Is input, the priority encoder outputs an encoded value “2”.

The primary decoding table memory 102 stores a run length of a variable-length code bit string, a reference code stored in advance for each bit length following the run, a bit length of the reference code, and a code number (reference address). The reference code 14 corresponding to the run length and the bit length 16 of the reference code 14 corresponding to the run length are used as an address with the value obtained by adding the encoded value 12 output from the priority encoder 100 to the offset address 13 output from the controller 104. And outputs a signal of a reference address 15 serving as a reference for calculating an address of the secondary decoding table memory in which the code number (address) of the input variable-length code bit string and its decoded word are stored.

The bit mask shifter 101 converts the variable length code bit string 11 into a priority encoder 100
Upper bits are discarded by the number of the encoded values 12 output, and a signal 17 in which a bit string having a bit length of 16 is extracted from the bit string following the run of the variable-length code bit string 11 is output. The subtractor 103 subtracts the code value of the signal 17 output from the bit mask shifter from the reference code 14 output from the primary decoding table memory 102, and outputs a difference signal 18.

If the difference signal 18 of the subtractor 103 is negative, the controller 104 changes the offset address 13 given to the primary decoding table memory, and again has a bit length longer than that of the primary decoding table memory. Large reference code 1
4, reference address 1 for secondary decoding table memory 106
5 and the bit length 16 of the reference code 14 are read. Thus, the controller 104 repeats the above operation until the signal 18 from the subtractor 103 becomes a positive number including 0.

If the signal 18 from the subtractor 103 is a positive number including 0, the subtractor 105 outputs a secondary decoding table memory 106 output from the primary decoding table memory 102.
The value of the signal 18 output from the subtractor 103 is subtracted from the reference address 15 for calculation, to calculate the code number of the variable-length code bit string, and to provide the calculated code number as the address 20 of the input secondary decoding table memory 106.

The controller 104 monitors the output 12 of the priority encoder 100 in case that the input variable-length code bit sequence 11 to be converted is a code composed of all runs, When it is detected that the code is composed of a run, the address 2
0 is invalidated, and a predetermined address 19 for the secondary decoding table memory 106 in which the decoded word of this code is stored is output.

The secondary decoding table memory 106 outputs a decoded word corresponding to the corresponding address based on the address 20 from the subtractor 105 or the address 19 from the controller 104. For example, when a multi-dimensional quantization coefficient is required as a decoded word as in MPEG-2 / AAC, 2
The next decoding table memory 106 stores the result of the remainder operation in advance, and outputs a quantized coefficient.

The operation described above is the basic operation in the variable length code decoding device shown in FIG. Next, a more detailed operation of each section of the present embodiment will be described with reference to FIGS. FIG. 3 is a diagram showing the contents of the primary decoding table memory based on the variable length code shown in FIG. As shown in FIG. 3, the primary decoding table memory stores a reference code, a code length, and a code number in association with each variable length code run length. Here, the reference code indicates a code for comparing the magnitude with the bit string following the run, the code length indicates the bit length of the reference code, and the code number indicates the reference address of the secondary decoding table memory.

In the primary decoding table memory, those having the same run length but different subsequent code lengths are respectively stored in the first decoding table memory.
.. Are stored in another group as a column, a second column,..., And the maximum value within the same code length is stored as the reference code in this example.

More specifically, in FIG. 2, the variable length codes having run lengths 2 from code numbers 5 to 10 are divided into code lengths 5 and 6. In this case, the first reference code is “001” excluding the run of code number 6 “11001”.
This reference code “001” is stored in the first column of FIG. 3, and when the value obtained by subtracting the output of the bit mask shifter 101 from this reference code is a positive number including 0, that is, the input variable length code When the code length is 5, the value of the result of the subtraction is further subtracted from the code number (reference address) 6 to calculate the address of the secondary decoding table memory 106.

When the value obtained by subtracting the output of the bit mask shifter 101 from the reference code "001" is negative, that is,
If the code length of the input variable length code is not 5, 1
The comparison with the reference code “0111” described in the second column of the next decoding table memory is performed to determine the address of the secondary decoding table memory 106.

As described above, the first column of the primary decoding table memory shown in FIG. 3 holds information corresponding to the run lengths of all the variable length codewords. Further, when a plurality of code lengths exist for the same run length, information corresponding to the second column is held. In the example of the variable length codeword shown in FIG. 2, since there are a plurality of code lengths in the run lengths 2 and 3, the primary decoding table memory has 2 columns × 4 types of information as shown in FIG.

FIG. 4 is a diagram showing the contents of the secondary decoding table memory when multidimensional variable length coding is considered. The code number is the address of the secondary decoding table memory, and the quantization coefficients 3 to 0 are multidimensional quantization coefficients. As described above, in the present invention, when a code corresponds to a multidimensional quantized coefficient, the result of the remainder operation is stored in advance in the secondary decoding table memory.

Next, the operation of the present embodiment shown in FIG. 1 when the input variable length code bit sequence 11 includes "110101..." As an example of the bit sequence composed of the variable length code shown in FIG. An example will be specifically described.

The priority encoder 100 detects the first “11” as the run length following the higher-order bit, and outputs the run length “2” to the signal line 12. The primary decoding table memory 102 has the table information shown in FIG.
The controller 104 first outputs an offset address designating the first column in response to the input of the run length “2”. The primary decoding table memory 102 outputs the reference code “001”, the code length “3”, and the code number “6” of the run length “2” stored in the first column. In the bit mask shifter 101, the run length “2” is input and the input variable-length code bit string 1
The upper two bits of 1 are discarded, a bit string “010” having a code length “3” is extracted from the bit string following the run, and a signal 17 is output. In the subtractor 103, the reference code “00”
The output “010” of the bit mask shifter is subtracted from “1”.

Since the result of the subtractor 103 becomes 1-2 = −1 and becomes negative, the controller 104 switches the offset address 13 of the primary decoding table memory 102 and switches the second column of the primary decoding table memory 102. Is specified. The primary decoding table memory 102 outputs the reference code “0111” corresponding to the run length “2” in the second column, the code length “4”, and the code number “10” as the reference address. The bit mask shifter 101 discards the upper two bits of the input variable-length code bit string according to the run length “2”, extracts a bit string “0101” having a code length “4” from the bit string following the run, and outputs a signal 17. The subtractor 103 subtracts the bit string “0101” from the reference code “0111”,
"2" is output. Since “2” is a positive number, the subtracter 105 calculates the value “8” obtained by subtracting the output “2” of the subtractor 103 from the code number “10” output from the primary decoding table memory 102 as a secondary value. Output as an address of the decoding table memory 106. In the secondary decoding table memory 106,
The decoded word "10" corresponding to the address "8" or the remainder operation result "0""1""0""1" is output.

In the above embodiment, the subtraction between the reference code and the output of the bit mask shifter is set such that the bit width of the subtraction is variable according to the bit length of the reference code.
If the result of the subtraction in 03 does not change, the number of bits may be set to be equal to or longer than the bit length of each reference code, for example, may be fixed to the maximum bit length of the reference code. Further, in the above-described embodiment, the run is truncated in the operation by the bit mask shifter. However, the bit string corresponding to the run is replaced with a logical value “0”, and the reference code and the output of the bit mask shifter are subtracted. May be increased. Alternatively, in the operation by the bit mask shifter, an input variable-length code bit string of (run length + code length) bits is extracted without truncating the run, and the logical value “1” of the run length is subtracted by the subtractor 103. Subtraction from the reference code added to the upper bits may be performed.

Further, regarding the operation of the controller 104, the output 1 of the subtractor 103 for subtracting the signal 17 from the reference code 14
An example has been shown in which the subsequent operation is controlled in a case where 8 is positive including 0 and a case where the output is positive when the output 18 is positive. It is also possible to make a change so that the subsequent operation is controlled in the negative case including 0.

[0044]

According to the variable length code decoding method and apparatus of the present invention, the capacity of the secondary decoding table memory is reduced by comparing the reference code with the code obtained by mask-shifting the input variable length code bit string. Since it is sufficient to prepare only the capacity corresponding to the same number as that described above, there is an effect that the storage capacity required for the conversion table can be significantly reduced.

According to the present invention, in the case of a decoded word requiring a remainder operation, the result of the remainder operation is stored in advance in the secondary decoding table memory, so that MPEG-2 / AA
Since the remainder operation in C or the like can be eliminated, there is an effect that the circuit scale can be reduced.

Further, according to the present invention, the output of the priority encoder is monitored by the controller, and when a code having the same logical value is detected, the address of the secondary decoding table memory is supplied from the controller. By obtaining a decoded word, there is also an effect that even if a variable-length code bit string composed of the same logical value is input from the beginning, an error can be generated and the word can be normally converted into a decoded word.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of a variable length code according to the present invention.

FIG. 3 is a diagram showing contents of a primary decoding table memory of the present invention.

FIG. 4 is a diagram showing the contents of a secondary decoding table memory according to the present invention.

FIG. 5 is a block diagram showing a conventional variable-length code decoding circuit of the present invention.

FIG. 6 is a diagram showing the contents of a table according to a conventional example of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 priority encoder 101 bit mask shifter 102 primary decoding table memory 103, 105 subtractor 104 controller 106 secondary decoding table memory 11 input variable-length code bit string signal 12 encode output signal of priority encoder 100 13 offset address signal 14 reference code signal 15 Code number signal 16 Code length signal 17 Bit string signal 18 Output signal of subtracter 103 19 Secondary decoding table memory 10 from controller 104
6 address signal 20 Secondary decoding table memory 10 from subtractor 105
6 address signal 499 control unit 500 register file 501, 502, 506 selector 503 priority encoder 504 barrel shifter 505 ALU 507 data RAM

Claims (8)

(57) [Claims] 1. A variable-length code decoding method for decoding a variable-length code bit string consisting of a run of the same logical value continuing from the head and a bit string following the run, comprising: Using a primary decoding table memory storing a code number of the reference code and a secondary decoding table memory storing a code number of an input variable length code bit string and a decoded word, an input variable length code is stored. Detecting the run length of the bit string and outputting a corresponding reference code and a code number of the reference code from the primary decoding table memory based on the run length;
The code number of the input variable-length code bit sequence is calculated from the difference between the reference code and the code of the bit sequence following the run of the input variable-length code bit sequence, and the code number of the input variable-length code bit sequence is calculated based on the calculated code number. A variable length code decoding method comprising: outputting a decoded word from a next decoding table memory. 2. The primary decoding table memory stores the reference code, a code number of the reference code, and a bit length in the same bit length unit of a bit string following a run, and stores a code number of an input variable-length code bit string. Is calculated by extracting the bit string following the run of the input variable-length code bit string by the bit length of the reference code, comparing with the reference code, searching for the corresponding reference code, and calculating using the reference code. 3. The variable length code decoding method according to claim 1, wherein: 3. If the detected run length is longer than a predetermined value, the corresponding decoding from the secondary decoding table memory is performed using a code number determined in advance as an input variable length code consisting of only codes of the same logical value. 3. The variable length code decoding method according to claim 2, wherein words are output. 4. A priority encoder for detecting a run length from an input variable-length code bit sequence in a variable-length code decoding device for decoding a variable-length code bit sequence consisting of a run of the same logical value continuing from the head and a bit sequence following the run. Primary decoding for outputting a specific code of the same code length unit of a code following the run as a reference code using the run length and the output of the controller as an address, and outputting a code number and a bit length of the reference code. A table memory, a bit mask shifter that cuts out the bit sequence from a variable-length code bit sequence based on the run length and the bit length of the reference code output from the primary decoding table memory, and a code of the bit sequence and the reference code. An arithmetic unit for calculating the code number of the input variable-length code bit string from the difference between A secondary decoding table memory that outputs a decoded word using the code number of the long code bit string as an address, and the controller that outputs a switching address of a primary decoding table memory based on the code of the bit string and the reference code. A variable-length code decoding device characterized by the above-mentioned. 5. The primary decoding table memory stores a plurality of sets of reference codes, numbers of the reference codes, and bit length information for inputs having the same run length, and the controller stores the plurality of sets of storage addresses. 5. The variable length decoding device according to claim 4, wherein switching between the variable length decoding devices is performed. 6. The controller according to claim 1, wherein when the output value of the priority encoder is larger than a predetermined value, the controller sets an address to the secondary decoding table memory as a variable-length code bit string composed of only codes having the same logical value. 5. The variable length decoding device according to claim 4, wherein the address is forcibly switched to an address corresponding to the decoded word. 7. The variable length code decoding apparatus according to claim 4, wherein a multidimensional code is stored as a decoded word in said secondary decoding table memory. 8. The variable length decoding device according to claim 4, wherein the number of words in said secondary decoding table memory is equal to the number of decoded words.