JP2001043067A - Arithmetic unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make an operation with high calculation accuracy performable even when data are extremely large or small in the case of arithmetically processing the data of a floating point form in the arithmetic processing part of a fixed point form. SOLUTION: When reading the data of the floating point form for one block into a RAM 40, to which series of operation including the operation of data are applied, as one block, a maximum value (r) of an index part is found within that block by an index part comparator 20 and an index part maximum value register 21. With the maximum value (r) as a common index part, a mantissa part is shifted by an ALU 60 so that the index part of all data in the block can be equal to the common index part (r). After shift processing, the mantissa part is handled as data of the fixed point form and prescribed operation is performed by using the ALU 60. After the end of the prescribed operation, bit shift is performed by using the common index part (r) and the final arithmetic result of the fixed point form is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for performing an arithmetic operation in a fixed-point format, and in particular, to a DSP (Digital).
The present invention relates to an audio decoding process using a signal processor.

[0002]

2. Description of the Related Art Conventionally, a DSP has been used as a means for performing processing such as a filter operation on time-series data such as images and sounds. The DSP is an arithmetic device having an architecture suitable for digital signal processing, and performs arithmetic processing according to a program (operation algorithm). DS
Since P can easily change the algorithm by changing programs and can realize a plurality of functions with one piece of hardware, P is widely used in digital consumer equipment and the like that require high performance and low cost.

[0003] Such a DSP generally operates on data in a fixed-point format. Since the arithmetic processing in the fixed-point format is simpler than that in the floating-point format, the configuration of the arithmetic circuit unit such as the ALU can be simplified.

FIG. 10 is a diagram showing a configuration of an arithmetic unit including an ALU for performing a general fixed-point arithmetic operation.

As shown in FIG. 1, the arithmetic unit comprises a program counter 01, a program memory 02, a command decoder 03, a general-purpose register 30, and a RAM 40.
, Data selectors 50 and 51, and an ALU 60.

[0006] The program counter 01 sequentially supplies the address of the operation processing command (instruction) to be executed to the program memory 02. The program memory 02 supplies the operation processing command stored at the address supplied from the program counter 01 to the command decoder 03.

The command decoder 03 decodes the input operation processing command and supplies a control signal corresponding to the operation processing command to the operation device.

The general-purpose register 30 is a register for storing data to be processed by the ALU 60, data of a calculation result, and the like.

The RAM 40 is a data storage unit having a larger capacity than the general-purpose register 30, and has a predetermined number (for example, 1).
024 data).

The data selector 50 selects an output of the ALU 60 or an input from the external bus 70 based on the control signal, and inputs the selected signal to the RAM 40 or the general-purpose register 30.

The data selector 51 selects data to be subjected to arithmetic processing from the RAM 40 or the general-purpose register 30 according to the control signal, and outputs the selected data to the ALU 60.

The ALU 60 performs arithmetic processing, such as addition, subtraction, multiplication, and bit shift operation, on the k-bit data represented in the fixed-point format input from the data selector 51 in accordance with the control signal. Outputs the calculation result.

The arithmetic unit generally reads one block of k-bit fixed-point format data from the external bus 70 into the RAM 40, and processes the data of the one block in accordance with the program in the program memory 02. I do.

However, some of the arithmetic processing performed by such an arithmetic device may require processing of input data in a floating-point format.

For example, ISO / IEC 13818-7 (hereinafter referred to as MPEG-2
In the decoding of AAC, the MPEG-2 AAC stream is first subjected to entropy decoding using Huffman coding, and this data is subjected to inverse quantization using an inverse quantization table, thereby obtaining frequency data in floating-point format. Get.

Then, PCM (Pulse Code Modulation) data is obtained from the frequency data by inverse fast Fourier transform. In order for this processing to be performed by a fixed-point arithmetic device, it is necessary to convert frequency data in a floating-point format into data in a fixed-point format.

FIG. 11 is a diagram showing a data representation in a floating-point format. As shown in the figure, the data includes a mantissa part (m bits) for storing a normalized numerical value and an exponent part (n bits) for storing an exponent. Since the mantissa part stores the normalized data, the decimal point position exists on the right side of the sign bit.

FIG. 12 shows a data representation in a fixed-point format. In this case, the data is not normalized, and the decimal point is located j bits away from the sign bit, as shown in FIG.

The conversion from the floating-point format having the above configuration to the fixed-point format is performed by converting a predetermined fixed-point format decimal point position and a value stored in the exponent part of each data in the floating-point format. This is performed by shifting the mantissa of each data in the floating-point format based on the data.

[0020]

At this time, the data of the mantissa may be lost due to the bit shift. For example, when the exponent part of the input floating-point format data is very large or very small, most of the data of the mantissa part is lost due to the bit shift to the left or right.

As described above, the conversion from the floating-point format to the fixed-point format may reduce the number of significant digits and degrade the calculation accuracy.

An object of the present invention is to provide an arithmetic unit capable of converting a floating-point format to a fixed-point format while minimizing the reduction in the number of significant digits.

[0023]

An arithmetic unit according to the present invention includes an arithmetic processing unit that performs an operation on data represented in a fixed-point format, a storage unit that stores a block composed of a plurality of data, An exponent maximum value for interpreting k-bit data stored in the storage unit as floating-point data having an m-bit mantissa and an n-bit exponent, and detecting a maximum value r of an exponent of data in the block. And converting each data in the block into a floating-point format represented by a set of a maximum value r of the exponent part and a mantissa part. The arithmetic processing unit performs arithmetic processing, converts each data into a fixed-point format based on the maximum value r before terminating a predetermined arithmetic processing on the data in the block and outputting the data to the outside. And wherein the door.

In this case, the exponent part maximum value detection unit includes an exponent part comparator and an exponent part maximum value register for storing data output by the exponent part comparator. The value of the exponent part of the data interpreted as the data in the decimal point format may be compared with the value of the exponent part maximum value register, and the larger one may be output.

The apparatus further comprises a maximum absolute value detecting section for interpreting an output of the arithmetic processing section as data in a fixed point format and detecting a maximum absolute value in the block, and executing addition / subtraction to the data in the block. Prior to, using the maximum absolute value to determine whether there is a possibility of overflow, as a result of the determination, if there is a possibility of overflow, shift each data in the block to the right You may.

Further, in this case, the maximum absolute value detector includes an absolute value comparator and a maximum absolute value register for storing data output by the absolute value comparator, and the absolute value comparator has a fixed value. Compare the absolute value of the data interpreted as decimal point format data and the value of the maximum absolute value register,
The larger one may be output.

The maximum absolute value detector includes an OR circuit and a most significant bit register for storing 1-bit data output from the OR circuit. The OR circuit has a fixed-point format. The logical sum of the most significant bit of the absolute value of the data interpreted as data and the value of the most significant bit register may be output.

The same register may be used as the maximum absolute value register and the exponent part maximum value register in a time-sharing manner, or the same register may be used as the maximum absolute value register and the exponent part maximum value register. A part of the general-purpose register provided in the device may be used.

An audio decoder according to the present invention includes the above-described arithmetic unit, and performs a decoding process of obtaining floating-point frequency coefficient data of a mantissa part m bits and an exponent part n bits from compression-encoded audio data; A process of obtaining k-bit fixed-point format audio data output from the frequency coefficient data is performed.

According to the operation method of the present invention, the maximum value r of the exponent part is detected for data in a block composed of a plurality of data in floating-point format, and each data in the block is converted to the exponent part. The data is converted to a floating-point format represented by a set of a maximum value r and a mantissa, and the mantissa of the converted data is subjected to arithmetic processing in a fixed-point format. Before completion of the arithmetic processing and output to the outside, each data is converted into a fixed-point format based on the maximum value r.

In this case, the maximum value r of the exponent part
Detect the maximum absolute value of the mantissa part of the data converted to be a floating-point format represented by a set of a mantissa and a mantissa, and execute the addition / subtraction for the data in the block, using the maximum absolute value. It may be determined whether or not there is a possibility of overflow, and as a result of the determination, if there is a possibility of overflow, each data in the block may be shifted to the right.

Further, in this case, when the maximum absolute value is larger than a predetermined value, it may be determined that there is a possibility of overflow, and when the most significant bit of the maximum absolute value is 1, It may be determined that there is a possibility of overflow.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, a first embodiment of the present invention will be described.

FIG. 1 is a diagram showing a first arithmetic unit according to the present invention.

As shown in the figure, the arithmetic unit includes a program counter 01, a program memory 02, a command decoder 03, an absolute value comparator 10, a maximum absolute value register 11, an exponent part comparator 20, , An exponent maximum value register 21, a general-purpose register 30, a RAM 40, data selectors 50 and 51, and an ALU 60.

Among the constituent elements, the program counter 0
1, the program memory 02, the command decoder 03, the general-purpose register 30, the RAM 40, the data selector 50, the data selector 51, and the ALU 60 are the same as those in the arithmetic device shown in FIG.

The absolute value comparator 10 includes a data selector 50
Is interpreted as fixed-point format data, the absolute value thereof is compared with the value of the maximum absolute value register 11, and the larger one is output to the maximum absolute value register 11. The maximum absolute value register 11 is a register that holds k-bit data output from the absolute value comparator 10.

The exponent part comparator 20 includes a data selector 50
Is interpreted as floating-point data having m bits of mantissa and n bits of exponent, and the n bits of the exponent and the value of the exponent maximum value register 21 are compared. Output to the value register 21. The exponent part maximum value register 21 stores n
This register holds bit data.

FIG. 2 is a diagram showing a configuration of the absolute value comparator 10. As shown in FIG.

As shown in the figure, the absolute value comparator 10
Data selector 100, subtractor 110, and absolute value converter 12
0. The absolute value converter 120 is a data selector 5
The absolute value a of the data given from 0 is output. The subtracter 110 subtracts the value b of the maximum absolute value register 11 from the value a output from the absolute value converter 120, and outputs the obtained a-b sign bit to the data selector 100. When the output of the subtractor 110 is 0, that is, when a> b, the data selector 100 selects a. When the output of the subtractor 110 is 1, that is, when a <b, b is selected. Select and output. Therefore, the larger one of a and b is output from the absolute value comparator 10.

FIG. 3 is a diagram showing the configuration of the exponent part comparator 20.

As shown in the figure, the exponent part comparator 20
It includes a data selector 200 and a subtractor 210. The subtractor 210 subtracts the value b of the exponent part maximum value register 21 from the n-bit exponent part a given from the data selector 50, and converts the obtained a-b sign bit into the data selector 2
Output to 00. The data selector 200 includes the subtractor 21
When the output of 0 is 0, that is, when a> b, a is selected, and when the output of the subtractor 210 is 1, that is, a
When <b, b is selected and output. Therefore, a
The larger one of b and b is output from the exponent comparator 20.

FIG. 4 is a diagram showing the flow of data processing in this embodiment. The data processing here is performed in the RAM 4
This is a block operation process for performing a predetermined operation process including an operation between data on one block of data read into 0.

First, a block of floating-point data represented by m bits of mantissa and n bits of exponent is read into the RAM 40 from the main memory or the like via the external bus 70 and the data selector 50 (step S101). At this time, each data is also supplied to the exponent comparator 20 at the same time. The exponent part comparator 20 compares the n-bit exponent part of each data with the n-bit value stored in the exponent part maximum value register, and outputs the larger data to the exponent part maximum value register 21. . The n-bit data output from the exponent part comparator 20 is written to the exponent part maximum value register 21 at the same timing as the corresponding data is written to the RAM 40.

If the exponent part maximum value register 21 is initialized (for example, to 0) before the reading of the block data is started, when the reading of all the data in the block into the RAM 40 is completed, the exponent part maximum value register 21 is initialized. The value register 21 stores the maximum value r of the exponent part in the input block. Therefore, after the reading of the block data is completed, the largest exponent r in the block is detected with reference to the exponent maximum value register 21 (S102).

Since the present arithmetic unit is provided with the exponent part comparator 20, data input and detection of the exponent part maximum value r can be executed at the same time, and the number of steps is significantly larger than when the same comparison processing is performed by software. Can be reduced.

Next, the ALU which performs the operation in the fixed-point format
In order to perform the arithmetic processing at 60, a process of converting the input floating-point format data of the mantissa part m bits and the exponent part n bits to fixed-point format data is performed (step S1).
03).

For this purpose, first, the bit shift amount when performing the bit shift processing on the mantissa is calculated. Conventionally, the shift amount when performing the bit shift process on the mantissa part is determined by the difference between the decimal point position in the fixed-point format and the value of the exponent part.
The value of the exponent part of each data is subtracted from the maximum value r of the exponent part in the block obtained in 102, and the difference is used as the shift amount of the mantissa part.

Next, each data in the block is shifted according to the bit shift amount calculated as described above. This shift processing is performed by the ALU 60. By this processing, all data in the block is represented by a common exponent r and a corresponding mantissa. Thereafter, the data of the mantissa is interpreted as a fixed-point format, and the ALU 60 performs an arithmetic process.

In the shift processing by the ALU 60,
Each shifted data is stored in the RAM 40 and supplied to the absolute value comparator 10. Absolute value comparator 1
0 compares the absolute value of each data with the value stored in the maximum absolute value register 11 and outputs the larger data to the maximum absolute value register 11. The data output from the absolute value comparator 10 is written to the maximum absolute value register 11 at the same timing as the corresponding data is written to the RAM 40.

If the maximum absolute value register 11 is initialized (for example, to 0) before the shift processing of the block data is started, when the shift processing of all data in the block is completed, the maximum absolute value register 11 is reset. Stores the maximum absolute value of the data in the block. Therefore, the maximum absolute value in the block can be detected by referring to the maximum absolute value register 11 after the shift processing of the block data is completed. The maximum absolute value is used in a process for preventing an overflow described later.

Since the present arithmetic unit is provided with the absolute value comparator 10, it is possible to detect the maximum value of the absolute value at the same time as the arithmetic processing such as the bit shift processing. , Can greatly reduce the number of steps.

Next, various arithmetic processings are performed on the data in the block by the program stored in the program memory (step S104).

During the operation, the ALU 60
Is stored in the RAM 40 and supplied to the absolute value comparator 10. Therefore, when all data in a block is updated by a series of arithmetic processing, the maximum absolute value register 11 stores the maximum absolute value in the block.

When all the arithmetic processing is completed, the external bus 7
Before outputting to 0, for all data in the block,
Bit shift is performed according to the common exponent part r so that the decimal point position of the data becomes equal to the final fixed point format decimal point position (step S105). By this process, all data in the block is converted into the final k-bit fixed-point format.

In the present embodiment, the mantissa part of each data in the block is shifted in accordance with the maximum value r of the exponent part to suppress the shift amount.
Overflow may occur during the arithmetic processing. For this reason, when addition and subtraction are performed during the arithmetic processing in step S104, processing for preventing overflow is performed.

FIG. 5 is a diagram showing the flow of the addition / subtraction processing in this embodiment.

First, before performing addition / subtraction processing on all the data in the block, the value of the maximum absolute value register 11 is referred to determine whether or not the maximum absolute value of the data in the block is equal to or greater than a predetermined value. Is determined (step S201). As a result, when the value of the maximum absolute value register 11 is equal to or larger than a predetermined value, it is determined that overflow may occur as a result of addition and subtraction, and all data is shifted right by one bit before performing addition and subtraction processing. The shift is performed (step S202). Also, by shifting all data one bit to the right, the decimal point position of the mantissa data is shifted one bit to the left.
The value of the common exponent r in the block is increased by 1 (step S203). Then, the mantissa after the shift is interpreted as k-bit fixed-point format data, and an operation is performed on the data in the block (step S204).

As described above, by performing the bit shift processing according to the value of the maximum absolute value of the data in the block before performing the operation in block units, it is possible to prevent the occurrence of overflow.

As described above, according to the present embodiment, before performing various arithmetic processing, the bit shift performed at a time before the operation is performed as compared with the conventional method in which the number of significant digits is reduced by performing a bit shift at a time. By minimizing the shift amount,
The mantissa of each data in the block is minimized. As a result, the number of significant digits of data on which various arithmetic processing is performed is increased, and the calculation accuracy is improved.

Further, since the arithmetic circuit unit (ALU) can be configured in a fixed-point system, it can be configured more easily than an arithmetic unit that handles all data in a floating-point format.

Also, the detection of the maximum absolute value in the block and the detection of the maximum value of the exponent part are realized by simple hardware, so that the detection processing can be executed in parallel with the arithmetic processing and the like, and the detection processing is realized by software. The processing time can be greatly reduced as compared with the case where the processing is performed.

Next, a second embodiment of the present invention will be described.

FIG. 6 is a diagram showing a configuration of the second arithmetic unit according to the present invention.

As shown in the figure, the present arithmetic unit differs from the arithmetic unit shown in FIG. 1 in an absolute value comparator 10a and a maximum absolute value register 11a, and the others are the same. Therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted.

The maximum absolute value register 11a is a register having a bit width of 1 bit. Absolute value comparator 10a
Outputs the logical sum of the output of the maximum absolute value register 11a and the MSB of the absolute value of the output of the ALU 60 to the maximum absolute value register 11a.

In the first embodiment, if the maximum absolute value of data in a block is equal to or more than a predetermined value in order to prevent overflow due to addition and subtraction, it is determined that there is a risk of overflow and all data in the block is replaced by one bit. Right shift.

On the other hand, in the present embodiment, if at least one data whose absolute value MSB is 1 is included in the block, it is determined that there is a risk of overflow, and before the addition / subtraction processing is performed, Each data in the block is shifted right.

In this case, in the first embodiment, the bit width of the maximum absolute value register 11 required k bits is set to MS
Only one bit for storing B is required. Further, the absolute value comparator 10 can be constituted by a logical sum instead of a value comparator. Therefore, the circuit is simplified and the circuit scale can be reduced as compared with the arithmetic device shown in FIG.

Next, a third embodiment of the present invention will be described.

FIG. 7 is a diagram showing a configuration of a third arithmetic unit according to the present invention. This arithmetic unit focuses on the fact that the maximum absolute value register 11 and the exponent part maximum value register 21 are not used at the same time, and uses the maximum absolute value register 11 as the exponent part maximum value register 21 in a time-sharing manner.
The purpose is to share the registers and reduce the circuit scale.

As shown in the figure, the present arithmetic unit is different from the arithmetic unit shown in FIG.
In that a data selector 52 is provided in place of the above, and the other is the same. Therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted. The changed parts will be described below.

The data selector 52 outputs the output from the absolute value comparator 10 and the exponent part comparator 20 according to the selection control signal.
Select one of the outputs from
Output to 1. The selection control signal is switched according to, for example, the operation mode of the arithmetic device.

The data selector 52 outputs the output of the exponent part comparator 20 to the maximum absolute value register 11 when reading the data block in the floating point format into the RAM 40. Thus, when the reading of the block data into the RAM 40 is completed, the maximum absolute value register 11 stores
This means that the maximum value r of the exponent part of the data in the block is stored.

When the mantissa part is bit-shifted to the right by the difference between the maximum value r of the exponent part in the block and the value of the exponent part of each data, the data selector 52 sets the absolute value comparator 10
Is output to the maximum absolute value register 11. As a result, when the shift processing of the block data is completed, the maximum absolute value of the data in the block is stored in the maximum absolute value register 11.

The other operations of the arithmetic unit are the same as those of the arithmetic unit described above.

Next, a fourth embodiment of the present invention will be described.

FIG. 8 is a diagram showing the configuration of the fourth arithmetic unit according to the present invention. This arithmetic unit uses a specific register in the general-purpose register 30 as a maximum absolute value register and an exponent part maximum value register.

As shown in the figure, the present arithmetic unit differs from the arithmetic unit shown in FIG. 1 in that a data selector 53 is provided instead of eliminating the absolute value register 11 and the exponent maximum value register 21. The other points are the same.
Therefore, the same portions are denoted by the same reference numerals and description thereof will be omitted. The changed parts will be described below.

The data selector 53 includes a data selector 5
Output of 0, output of absolute value comparator 10, exponent part comparator 20
Is selected by the selection control signal, and the general-purpose register 3
Output to 0.

When calculating the maximum value r of the exponent part of the data in the block, the data selector 53 uses the exponent part comparator 20
Is output to a specific register in the general-purpose register 30 assigned to the exponent maximum value register. When obtaining the maximum absolute value of the data in the block, the output of the absolute value comparator 10 is output to a specific register in the general-purpose register 30 assigned to the maximum absolute value register.

Other operations of the present arithmetic unit are the same as those of the arithmetic unit described above.

In the present arithmetic unit, by placing the maximum absolute value register and the exponent part maximum value register in the general-purpose register 30, the maximum absolute value register and the exponent part maximum value register are required when addition / subtraction is not performed in the arithmetic processing. If not, the circuit is reduced by using it as a general-purpose register.

Next, an audio decoder using the present invention will be described.

FIG. 9 is a diagram showing an example of an audio decoder using the arithmetic unit according to the present invention. In the figure, the configuration of the arithmetic unit 90 is the same as that of the arithmetic unit described above.

In this case, as shown in the figure, the program memory 02 stores a program 0 for performing entropy decoding processing.
4 and a program 05 for performing inverse fast Fourier transform.

The compressed and encoded audio data 80 for one frame is decoded by the program 04 for performing entropy decoding processing into frequency coefficient data 81 for one frame having m-bit mantissa and n-bit exponent, respectively. You. Here, by treating the frequency coefficient data 81 for one frame as one block, as described in the above embodiment, a common exponent r is obtained in the block, and the exponents of all data in the block are The mantissa is shifted to the right so as to be r, and thereafter, the mantissa is handled as k-bit fixed-point data.

The data is decoded using the program 05 for performing the inverse fast Fourier transform. When the addition / subtraction is performed in the middle, the operation is performed according to the maximum absolute value register while performing the bit shift so as not to cause the overflow, as described in the above embodiment. After the completion of the inverse fast Fourier transform, all the data in the block is shifted based on the common exponent part r in the block, and the audio data 82 in the k-bit fixed point format is output.

In this embodiment, one audio frame is regarded as one block, and each data given in the floating-point format is bit-shifted and operated based on the maximum value of the exponent part in one block. Since loss of significant digits is suppressed as compared with the case where a bit shift is performed at a time and conversion is performed to a fixed-point format to perform an operation, a highly accurate audio output can be obtained.

[0091]

As described above in detail, according to the present invention, in a device for performing an operation on input data in a floating-point format, conversion from a floating-point format to a final fixed-point format is performed stepwise. Thereby, the calculation accuracy can be improved. Furthermore, by managing the maximum absolute value in the block, it is possible to prevent overflow.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first arithmetic unit according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of an absolute value comparator 10.

FIG. 3 is a block diagram showing a configuration of an exponent part comparator 20.

FIG. 4 is a flowchart illustrating a flow of a block calculation process.

FIG. 5 is a flowchart illustrating a flow of an addition / subtraction process.

FIG. 6 is a block diagram showing a configuration of a second arithmetic unit according to the present invention.

FIG. 7 is a block diagram showing a configuration of a third arithmetic unit according to the present invention.

FIG. 8 is a block diagram showing a configuration of a fourth arithmetic unit according to the present invention.

FIG. 9 is a diagram illustrating an example of an audio decoder to which the present invention has been applied.

FIG. 10 is a block diagram illustrating a configuration of a conventional arithmetic device.

FIG. 11 is a diagram showing a data representation in a floating-point format.

FIG. 12 is a diagram showing a data representation in a fixed-point format.

[Explanation of symbols]

 Reference Signs List 10 absolute value comparator 11 maximum absolute value register 20 exponent part comparator 21 exponent part maximum value register

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Taku Nakamura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Multimedia System Development Division, Hitachi, Ltd. (72) Inventor Hiroaki Shirane Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa 292 Hitachi Image Information System Co., Ltd. (72) Eiji Yamamoto Inventor 5-2-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term (reference) 5B022 AA00 BA01 BA02 CA01 CA03 CA04 CA07 DA02 DA06 FA05 FA06

Claims (11)

[Claims] 1. An arithmetic processing unit for performing an operation on data represented in a fixed-point format, a storage unit for storing a block composed of a plurality of data, and k-bit data stored in the storage unit. Mantissa m
Bit, exponent part interpreted as n-bit floating point data, and the maximum value r of the exponent part of the data in the block
And converting each data in the block to a floating-point format represented by a set of a maximum value r of the exponent part and a mantissa. For the mantissa part of the subsequent data, the arithmetic processing is performed by the arithmetic processing unit, and before the predetermined arithmetic processing for the data in the block is completed and output to the outside, based on the maximum value r,
An arithmetic unit for converting each data into a fixed-point format. 2. The exponent part maximum value detection unit includes: an exponent part comparator; and an exponent part maximum value register that stores data output by the exponent part comparator. 2. The arithmetic unit according to claim 1, wherein the value of the exponent part of the data interpreted as the format data is compared with the value of the exponent part maximum value register, and the larger one is output. 3. A maximum absolute value detecting unit for interpreting an output of the arithmetic processing unit as data in a fixed-point format and detecting a maximum absolute value in the block, performing addition and subtraction on data in the block. Prior to the above, it is determined whether or not there is a possibility of overflow using the maximum absolute value, and as a result of the determination, if there is a possibility of overflow, each data in the block is shifted to the right. The arithmetic device according to claim 1 or 2, wherein 4. The maximum absolute value detector includes: an absolute value comparator; and a maximum absolute value register that stores data output by the absolute value comparator, wherein the absolute value comparator has a fixed-point format. 4. The arithmetic unit according to claim 3, wherein an absolute value of the data interpreted as data is compared with a value of the maximum absolute value register, and a larger one is output. 5. The maximum absolute value detection unit includes: a logical sum circuit; and a most significant bit register that stores 1-bit data output from the logical sum circuit, wherein the logical sum circuit has a fixed-point format. 4. The arithmetic unit according to claim 3, wherein a logical sum of the most significant bit of the absolute value of the data interpreted as data and the value of the most significant bit register is output. 6. The arithmetic unit according to claim 4, wherein the same register is used as the maximum absolute value register and the exponent part maximum value register by time division. 7. An arithmetic unit according to any one of claims 1 to 6, wherein floating-point frequency coefficient data having a mantissa part of m bits and an exponent part of n bits is obtained from compression-encoded audio data. An audio decoder comprising: a decoding process for obtaining; and a process for obtaining k-bit fixed-point format audio data output from the frequency coefficient data. 8. A maximum value r of an exponent part of data in a block composed of a plurality of data in a floating-point format
And converts each data in the block into a floating-point format represented by a set of the maximum value r of the exponent part and the mantissa, and fixes the mantissa of the converted data. Perform arithmetic processing in a decimal point format, and before performing predetermined arithmetic processing on data in the block and outputting the data to the outside, based on the maximum value r,
An arithmetic method characterized by converting each data into a fixed-point format. 9. Detecting a maximum absolute value of a mantissa of data converted into a floating-point format represented by a set of a maximum value r of the exponent and a mantissa, and adding / subtracting the data in the block Prior to the execution of the above, it is determined whether or not there is a possibility of overflow using the maximum absolute value. If the result of the determination is that there is a possibility of overflow, each data in the block is shifted to the right. The method according to claim 8, wherein: 10. The method according to claim 9, wherein when the maximum absolute value is larger than a predetermined value, it is determined that there is a possibility of overflow. 11. The method according to claim 9, wherein when the most significant bit of the maximum absolute value is 1, it is determined that there is a possibility of overflow.