JP3285627B2 - Monolithic integrated circuit with built-in power sequence - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monolithic integrated circuit having a built-in power supply sequence circuit.

[0002]

2. Description of the Related Art Conventionally, a GaAs FET (gallium arsenide FE) has been used.
TMIC) (Microwave Monolithic Integra)
ted the Circuit: In a microwave monolithic IC) amplifier or the like, for applying a gate voltage Vg of the gate bias of the FET to its use - Voltage V _-) and for applying a drain voltage Vd + voltage V ₊ of the two Power supply is used. In order to operate the MMIC, a sequence in which a gate voltage Vg is first applied to a gate and then a drain voltage Vd is applied to a drain (a sequence for preventing a drain voltage from being applied earlier than a gate voltage). In order to stop the operation of the MMIC, it is necessary to first turn off the drain voltage Vd and then turn off the gate voltage Vg (a sequence for preventing the gate voltage from being stopped before the drain voltage is applied). ) Was needed. Therefore, it is necessary to provide a power supply sequence circuit for executing this sequence outside the amplifier separately from the amplifier.

[0003]

Generally, the external power supply sequence circuit is composed of a low-frequency transistor, a zener diode, an operational amplifier and the like, so that its size becomes large. Therefore, the amplifier itself has M
Although the MIC can greatly reduce the size, the external dimensions of the power supply sequence circuit and the amplifier cannot be reduced due to the external power supply sequence circuit.

The present invention has been made in view of such a problem, and an object of the present invention is to reduce the size of an apparatus constituted by a monolithic integrated circuit by incorporating a power supply sequence circuit in the monolithic integrated circuit itself. It is in.

[0005]

FIG. 1 is an explanatory view of the principle according to the present invention. The monolithic integrated circuit with a built-in power supply sequence of the present invention is provided on a chip of the monolithic integrated circuit.
A sequence field effect transistor 11 is formed together with a function field effect transistor 12 that performs a required function. The sequence field effect transistor 11 has a large drain current Idss ₁₁ for sequence operation and pinches off when a gate voltage is applied. And a drain voltage application power supply is connected to the sequence field effect transistor 11 and the function field effect transistor 12 via the resistor 13 via the resistor 13, respectively. Gate G
Is connected to the gate bias power supply side of the functional field effect transistor 12.

The above-mentioned field effect transistor for sequence is formed by the same process as the field effect transistor for function, and at this time, the gate width of the field effect transistor for sequence is made sufficiently larger than the gate width of the field effect transistor for function. Thus, a large drain current for the sequence operation can be provided.

Further, a plurality of sequence field effect transistors can be formed in the same process and the same pattern shape as the function field effect transistor, and these can be connected in parallel to obtain a large drain current for sequence operation. .

The drain and the gate of the sequence field effect transistor can be terminated by a terminating resistor.

[0009]

First, when the voltage of the power supply for drain voltage application 14 is applied, a large drain current Idss ₁₁ for sequence operation flows through the field effect transistor 11 for sequence, thereby causing a large voltage drop in the resistor 13 to cause a functional voltage drop. The drain voltage applied to the field effect transistor 13 becomes almost zero. Next, when the voltage of the gate bias power supply 15 is applied, the sequence field effect transistor 1 is turned on.
1 is in a pinch-off state, and the drain current Idss ₁₁ for the sequence operation is cut off. Therefore, a large voltage drop in the resistor 13 is eliminated, and the drain voltage is applied to the functional field-effect transistor 12. Thereby, a sequence at the time of applying power is realized.

If the drain and the gate of the sequence field effect transistor are terminated by a terminating resistor, occurrence of oscillation can be prevented.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a monolithic integrated circuit with a built-in power supply sequence as an embodiment of the present invention. In this embodiment, the present invention is applied to a GaAs-FET-MMIC amplifier.

In FIG. 2, 1 is a field effect transistor (FET) for realizing a sequence, and 2 is M
This is a field-effect transistor that constitutes an MIC amplifier or the like. The + side power supply voltage V ₊ is for supplying a power supply voltage to the amplifier field effect transistor 2, and the − side power supply voltage V ₋ is for supplying a gate bias power supply voltage to the field effect transistor 2. Things. The + side power supply voltage V ₊ is applied to the drains D of the field effect transistors 1 and 2 via the resistor R3. The negative side power supply voltage V _- is applied to the gate G of the field effect transistor 1 and the gate voltage V is applied to the gate G of the field effect transistor 2 via a bias circuit including resistors R1 and R2.
It is applied as g _2.

The field effect transistor 1 for the sequence is formed together with the field effect transistor 2 on the chip of the MMIC. The field effect transistor 1 to a gate source voltage V _- is configured to be sufficiently pinched off when is applied. It has a large drain current Idss ₁ and has a gate voltage Vg ₁
= When 0 is made to be the drain voltage of the field effect transistor 2 substantially 0V by flowing a large drain current Idss ₁ to the field effect transistor 1. As described above, the field effect transistor 1 for sequence is further provided in the chip of the GaAs-FET-MMIC circuit.
Is not particularly expensive and the size is not so large.

The operation of this embodiment will be described below.
First, when operating a circuit, the power supply voltage V _- applying the power supply voltage V ₊ before applying. At this time, since the gate G of the field effect transistor 1 0V is applied through a resistor R1, R2, the drain current Idss ₁ flows through the field effect transistor, if the drain current Idss ₁ is sufficiently large, The voltage drop across the resistor R3 increases and the drain voltage V applied to the field effect transistor 2 increases.
d ₂ becomes substantially to 0V.

Next, the power supply voltage V _- is applied to the gate G of the field effect transistor 1. This power supply voltage V _- is also applied to the gate G of the field effect transistor 2 via the resistance voltage dividers R1 and R2. The supply voltage V _- field effect transistor 1 by the applied its drain current Idss ₁ = 0, and the thus the voltage drop across the resistor R3 is reduced in a pinch-off state, predetermined through the power supply voltage V ₊ is resistor R3 is applied to the drain D of the field effect transistor 2 is the drain voltage Vd _2.

Therefore, focusing on the field effect transistor 2 for an amplifier, first, the gate voltage Vg ₂ is applied,
Subsequently, a sequence in which the drain voltage Vd ₂ is applied is realized, and it is possible to prevent the drain voltage from being applied before the gate voltage.

The above is the operation when the power supply voltage is applied to the amplifier. When the application of the power supply voltage is stopped, a sequence is applied according to the same principle. That is, the power supply voltage V _- when stopping the application of a large drain current Idss ₁ flows gate voltages Vg ₁ of the field effect transistor 1 is turned 0V, become thereby a drain voltage Vd ₂ approximately 0V field effect transistor 2 . In this case, regarding the field effect transistor 2, the gate voltage Vg ₂ and the drain voltage Vg ₂
The stop of the application of d ₂ is almost simultaneous, so that the gate voltage Vg ₂
Sequence to prevent that by applying stop gate voltage Vg ₂ before applying stop can be realized.

In the circuit of the above-described embodiment, the field effect transistor 1 does not need to be manufactured by a process different from that of the field effect transistor 2 for an amplifier. To increase the drain current Idss ₁ of the field effect transistor 1, The gate width Wg _{2 is set} to the gate width Wg of the field effect transistor 2.
_It should just be big enough for ₂ . Alternatively, as shown in FIG. 3, by arranging a plurality of field effect transistors ₁₁ to 1 _n having the same process and the same FET pattern as the field effect transistor 2 for the amplifier in parallel, the total drain current thereof can be reduced. What is necessary is just to make it large and use it as a field effect transistor for sequences.

In implementing the present invention, various modifications other than those described above are possible. For example, FIG. 4 shows an embodiment in which oscillation of the field effect transistor 1 for sequence can be prevented. That is, the drain D of the field effect transistor 1 is connected to the capacitor C2 and the resistor R5 (=
50Ω), its gate G is grounded via a capacitor C1 and a resistor R4 (= 50Ω), and its drain D is connected to a resistor R3 via an inductance L2. An inductance L1 is inserted between R1 and R2 and the gate G. The power supply voltage V _- is applied to the gate G via the inductance L3. In this case, the drain D and the gate G of the field-effect transistor 1 are each terminated by 50Ω with respect to the AC signal, thereby preventing occurrence of oscillation.

In the above embodiment, basically, one field effect transistor 1 for a sequence is provided for one field effect transistor 2 for an amplifier. However, the present invention is not limited to this. One sequence field effect transistor is provided for a plurality of amplifier field effect transistors, and this sequence field effect transistor realizes the power supply voltage application sequence of the amplifier field effect transistors collectively. It may be configured.

[0021]

As described above, according to the present invention, since the power supply sequence circuit can be built in the monolithic integrated circuit itself, the size of the monolithic IC amplifier can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory view of the principle according to the present invention.

FIG. 2 is a diagram showing a monolithic integrated circuit with a built-in power supply sequence as one embodiment of the present invention.

FIG. 3 is a diagram showing another embodiment of the present invention.

FIG. 4 is a diagram showing still another embodiment of the present invention.

[Explanation of symbols]

1, 1 ₁ to 1 _n Field effect transistor for sequence 2 Field effect transistor for amplifier R1 to R5 Resistors C1, C2 Capacitors L1 to L3 Inductance

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H03F 1/52 (72) Inventor Haruki Nishida 1015 Ueodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shin Watanabe Fujitsu Co., Ltd. (72) Inventor Masayoshi Ikuno 1-25-2, Goshodori, Hyogo-ku, Kobe-shi, Hyogo Prefecture Fujitsu Ten Co., Ltd. (56) References JP-A Sho 56- 121332 (JP, A) JP-A-62-109112 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8234 H01L 21/822 H01L 27/06 311 H01L 27/088 H03F 1/52 H01L 29/80 H02J 1/00 308

Claims (4)

(57) [Claims] 1. A field effect transistor for performing a required function on a chip of a monolithic integrated circuit.
To form a sequence field effect transistor (11), which has a large drain current for sequence operation and is pinched off when a gate voltage is applied,
A drain voltage application power supply (14) is connected to the drain of the field effect transistor for sequence and the drain of the field effect transistor for function via a resistor (13), respectively, and the gate of the field effect transistor for sequence is connected to the function. Power supply for gate bias of field effect transistor (1
5) A monolithic integrated circuit with a built-in power supply sequence configured to be connected to the side. 2. The sequence field-effect transistor is formed by the same process as the function field-effect transistor, and the gate width of the sequence field-effect transistor is larger than the gate width of the function field-effect transistor. 2. The monolithic integrated circuit with a built-in power supply sequence according to claim 1, wherein the monolithic integrated circuit has a large drain current for sequence operation. 3. A plurality of field effect transistors for sequence are formed in the same process and the same pattern shape as the field effect transistors for function, and these are connected in parallel to obtain a large drain current for sequence operation. A monolithic integrated circuit with a built-in power supply sequence according to claim 1. 4. The monolithic integrated circuit with a built-in power supply sequence according to claim 1, wherein a drain and a gate of said sequence field effect transistor are terminated by a terminating resistor.