JP3284758B2 - IC package - Google Patents

IC package

Info

Publication number
JP3284758B2
JP3284758B2 JP12766894A JP12766894A JP3284758B2 JP 3284758 B2 JP3284758 B2 JP 3284758B2 JP 12766894 A JP12766894 A JP 12766894A JP 12766894 A JP12766894 A JP 12766894A JP 3284758 B2 JP3284758 B2 JP 3284758B2
Authority
JP
Japan
Prior art keywords
solder
package
connection terminal
base member
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP12766894A
Other languages
Japanese (ja)
Other versions
JPH07335780A (en
Inventor
一久 小澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Enplas Corp
Original Assignee
Enplas Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Enplas Corp filed Critical Enplas Corp
Priority to JP12766894A priority Critical patent/JP3284758B2/en
Publication of JPH07335780A publication Critical patent/JPH07335780A/en
Application granted granted Critical
Publication of JP3284758B2 publication Critical patent/JP3284758B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、プリント基板に対する
半田付け状態を容易に確認することのできるICパッケ
ージに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC package capable of easily confirming a soldered state on a printed circuit board.

【0002】[0002]

【従来の技術】ICパッケージには種々のタイプのもの
があるが、プリント基板への自動装着の観点から、これ
までQFP型のICパッケージが多く用いられてきた。
然しながら近年、これに代わってBGA(Ball Grid Ar
ray )型のICパッケージが注目を集め始めている。そ
のBGA型ICパッケージの一例を図7で説明する。多
層基板製のベース板1の上面に、ICチップ、ICモジ
ュールなどの封止されたIC本体2が装着されており、
ベース板1の下面には多数のボール状の接続端子3が設
けられている。このICパッケージをプリント基板に接
合する場合には、図のようにプリント基板4の電極部
(ランド)4aにスクリーン印刷等によってクリーム半
田を塗布し、その上に上記接続端子3を載せてからリフ
ロー炉を通し、半田付けを行う。ところが、このような
ICパッケージは、種々の要因によって、ベース板1が
反り返ったり、接続端子3の形成にばらつきが生じたり
して、接続端子3の先端をすべて同一面に揃えることが
難しい。又、ベース板1の反り返りはリフロー炉内で生
じることもある。更に、場合によっては、プリント基板
4が反り返り、電極部4aの高さにばらつきを生じるこ
ともあった。そのため、ICパッケージをプリント基板
に接合するに際し、すべての接続端子の半田付けを完全
に行うことができない場合があった。
2. Description of the Related Art There are various types of IC packages. From the viewpoint of automatic mounting on a printed circuit board, a QFP type IC package has been often used so far.
However, in recent years, BGA (Ball Grid Ar
ray) type IC packages are starting to attract attention. An example of the BGA type IC package will be described with reference to FIG. A sealed IC body 2 such as an IC chip or an IC module is mounted on an upper surface of a base plate 1 made of a multilayer substrate.
Many ball-shaped connection terminals 3 are provided on the lower surface of the base plate 1. When this IC package is bonded to a printed board, cream solder is applied to the electrode portions (lands) 4a of the printed board 4 by screen printing or the like as shown in the figure, and the connection terminals 3 are placed thereon, and then reflowed. Solder through the furnace. However, in such an IC package, due to various factors, the base plate 1 warps or the formation of the connection terminals 3 varies, so that it is difficult to align all the tips of the connection terminals 3 on the same plane. In addition, warping of the base plate 1 may occur in a reflow furnace. Further, in some cases, the printed circuit board 4 may be warped, causing variations in the height of the electrode portions 4a. Therefore, when connecting the IC package to the printed circuit board, it may not be possible to completely solder all the connection terminals.

【0003】[0003]

【発明が解決しようとする課題】従来は、上記のように
半田付けが不十分なとき、接続端子がベース板の下側に
あるため、それを外観上から検知することが極めて困難
であった。そのため確実に確認を行うためには軟X線装
置などを使用せざるを得なかったが、そのような装置は
何れも高価であり、しかも軟X線装置の場合にはX線が
人体に有害であることから、装置の取扱いに十分な注意
を要する等の問題があった。
Conventionally, when the soldering is insufficient as described above, the connection terminals are located below the base plate, and it is extremely difficult to detect them from the appearance. . For this reason, a soft X-ray device had to be used to ensure confirmation, but such a device is expensive, and in the case of a soft X-ray device, X-rays are harmful to the human body. Therefore, there is a problem that sufficient care must be taken in handling the device.

【0004】本発明は、上記のような問題点に鑑みてな
されたものであり、その目的とするところは、上記のよ
うにICを装着したベース部材の一つの面に複数の接続
端子を配置したICパッケージにおいて、プリント基板
との半田付けの確認を外観上から容易に行うことのでき
るICパッケージを提供することである。
The present invention has been made in view of the above problems, and has as its object to dispose a plurality of connection terminals on one surface of a base member on which an IC is mounted as described above. An object of the present invention is to provide an IC package in which soldering with a printed circuit board can be easily confirmed from the appearance in the IC package.

【0005】[0005]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明においては、ICチップやICモジュール
を装着したベース部材の一方の面に外部回路等と接続す
るための複数の接続端子を配置したICパッケージにお
いて、前記ベース部材におけるICチップやICモジュ
ールなどの装着されていない位置に、内部に半田を充填
した管状の接続端子を、他方の面から前記ベース部材を
貫通し、その先端が前記ベース部材の前記一方の面へ
き出るようにして装着する。
In order to achieve the above object, according to the present invention, a plurality of connection terminals for connecting an external circuit or the like to one surface of a base member on which an IC chip or an IC module is mounted. In an IC package in which a tubular connection terminal filled with solder is passed through the base member from the other surface at a position where the IC chip or IC module or the like is not mounted on the base member, Are mounted so that they protrude from the one surface of the base member .

【0006】[0006]

【作用】プリント基板の電極部にクリーム半田を塗布
し、上記の構成をしたICパッケージを、その接続端子
の先端がクリーム半田に接触するようにして載置する。
この状態でリフロー炉へ入れると、クリーム半田と、接
続端子の内部に充填されていた半田とが溶ける。クリー
ム半田が溶けると接続端子の先端部外側に盛り上がる
が、このとき接続端子の内部の半田はその一部が外側に
流出する。そのため接続端子の反対側においては、半田
の端面が移動し接続端子の端面との間にギャップが生じ
る。リフロー炉から取り出した後、このギャップを目視
するか又は周知の外観検査装置によって観察することに
より、接続端子が半田によってプリント基板の電極部に
接合されたかどうかを確認する。
The cream solder is applied to the electrode portion of the printed circuit board, and the IC package having the above configuration is placed so that the ends of the connection terminals are in contact with the cream solder.
When the solder is put into the reflow furnace in this state, the cream solder and the solder filled in the connection terminals are melted. When the cream solder melts, it rises to the outside of the tip of the connection terminal. At this time, a part of the solder inside the connection terminal flows out to the outside. Therefore, on the opposite side of the connection terminal, the end face of the solder moves and a gap is generated between the end face of the connection terminal and the solder. After taking out from the reflow furnace, the gap is visually checked or observed by a known visual inspection device to confirm whether the connection terminal is joined to the electrode portion of the printed board by soldering.

【0007】[0007]

【実施例】本発明を、図1乃至図3に示した実施例に基
づき具体的に説明する。図1は本発明のICパッケージ
の一例を示す斜視図であり、図2は図1のA−A線断面
図である。図3はICパッケージとプリント基板との接
合部を示す要部拡大断面図であり、(a)はリフロー炉
で加熱する前の状態を示し、(b)は加熱後の状態を示
している。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described with reference to the embodiments shown in FIGS. FIG. 1 is a perspective view showing an example of the IC package of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. 3A and 3B are enlarged cross-sectional views of a main part showing a joint between the IC package and the printed circuit board . FIG. 3A shows a state before heating in a reflow furnace, and FIG. 3B shows a state after heating.

【0008】ベース板1の上面中央部にはIC素子2a
を合成樹脂等で封止したICチップ2が搭載されてい
る。ベース板1は、セラミック,シリコン,ガラス,若
しくは合成樹脂で作られており、通常はこれに一層若し
くは多層の配線パターンが設けられているが、図2及び
図3においては一層の場合の配線パターン1aを示して
いる。又、ベース板1にはICチップ2の入出力端子と
なる接続端子5が取付けられている。この接続端子5は
銅又は銅合金製であって、管状をしており、その貫通孔
5aの中には半田6が充填されている。この半田6はフ
ラックスを含まない半田であってもフラックスを含んだ
ヤニ入り半田であっても構わない。この接続端子5は外
形が砲弾の形をしており、僅かにテーパが付いている。
従って、この接続端子5をベース板1に取付けるために
は、ベース板1の上面側から接続端子5を圧入し、パタ
ーン1aと接続端子5とを接触状態にする。両者の接触
関係を良好にするために予め接続端子5の外周面に金メ
ッキを施しても構わない。
An IC element 2a is provided at the center of the upper surface of the base plate 1.
Is mounted with an IC chip 2 sealed with a synthetic resin or the like. The base plate 1 is made of ceramic, silicon, glass, or a synthetic resin, and is usually provided with a single-layer or multi-layer wiring pattern. In FIGS. 2 and 3, a single-layer wiring pattern is used. 1a is shown. A connection terminal 5 serving as an input / output terminal of the IC chip 2 is attached to the base plate 1. The connection terminal 5 is made of copper or a copper alloy, has a tubular shape, and has a through hole 5 a filled with solder 6. The solder 6 may be a solder containing no flux or a solder containing flux. The connection terminal 5 has a shell-shaped outer shape and is slightly tapered.
Therefore, in order to attach the connection terminal 5 to the base plate 1, the connection terminal 5 is press-fitted from the upper surface side of the base plate 1 to bring the pattern 1 a into contact with the connection terminal 5. Gold plating may be applied to the outer peripheral surface of the connection terminal 5 in advance in order to improve the contact relationship between the two.

【0009】次に、図3を用いて、上記のICパッケー
ジをプリント基板に接合する場合について説明する。
尚、図3においてはレジストのコーティング層の図示が
省略されている。プリント基板4には銅箔で形成された
配線パターンの電極部4aが形成されている。先ず、こ
の電極部4aにスクリーン印刷法によりクリーム半田7
を塗布する。次に上記のICパッケージを、自動装着機
等によりプリント基板4上に載置する。その状態が図3
(a)に示されている。クリーム半田7は通常、厚さが
0.1mmから0.7mm位であり、この状態においては接
続端子5の先端は電極部4aには接していない。又、ク
リーム半田7は粘性があるので、ICパッケージを載置
したとき、すべての接続端子5の先端部が同一面上に揃
っていなくても、その差が許容差内にあるとすれば、I
Cパッケージを載置する際、ICパッケージが僅かにク
リーム半田7に食い込むことにより、すべての接続端子
5がクリーム半田7に接触するようになる。
Next, a case where the above IC package is bonded to a printed circuit board will be described with reference to FIG.
In FIG. 3, illustration of the resist coating layer is omitted. The printed circuit board 4 has an electrode portion 4a of a wiring pattern formed of copper foil. First, cream solder 7 is applied to the electrode portion 4a by screen printing.
Is applied. Next, the above-mentioned IC package is mounted on the printed circuit board 4 by an automatic mounting machine or the like. Fig. 3
This is shown in FIG. The cream solder 7 usually has a thickness of about 0.1 mm to 0.7 mm, and in this state, the tip of the connection terminal 5 is not in contact with the electrode portion 4a. Also, since the cream solder 7 is viscous, even if the tips of all the connection terminals 5 are not aligned on the same surface when the IC package is mounted, if the difference is within the tolerance, I
When the C package is placed, all the connection terminals 5 come into contact with the cream solder 7 because the IC package slightly bites into the cream solder 7.

【0010】このようにICパッケージを載置した後、
プリント基板4をリフロー炉へ入れて加熱する。クリー
ム半田7が溶け出すと、クリーム半田に含有しているフ
ラックスの作用で接続端子5の先端部の濡れ性をよくし
電極部4aと接続端子5の間にフィレットが形成され盛
り上がる。この過程で電極部4aの外周部のクリーム半
田がフィレット部に引き寄せられると共に、貫通孔5a
の下端近傍のクリーム半田も同様にして引き寄せられ
る。従って貫通孔5aの中にあって溶融した半田6が下
方へ移動し、その上端面6aと接続端子5の上端面との
間に差が生じる。その状態が図3(b)に示されてい
る。
After placing the IC package in this manner,
The printed circuit board 4 is placed in a reflow furnace and heated. When the cream solder 7 melts, the wettability of the tip of the connection terminal 5 is improved by the action of the flux contained in the cream solder, and a fillet is formed between the electrode portion 4a and the connection terminal 5 to swell. In this process, the cream solder on the outer peripheral portion of the electrode portion 4a is drawn to the fillet portion and the through-hole 5a
Is also drawn in the same manner. Accordingly, the molten solder 6 in the through hole 5a moves downward, and a difference is generated between the upper end surface 6a and the upper end surface of the connection terminal 5. This state is shown in FIG.

【0011】他方、ICパッケージやプリント基板は、
製造後における外部からの熱や力などによって変形する
ことがあり、またクリーム半田の厚さが均一に塗布され
ない場合もある。このようなことが原因となり、ICパ
ッケージをプリント基板に載置したとき、一部の接続端
子5の先端がクリーム半田7の表面に接触しない場合が
ある。そのような場合には電極部4aと接続端子5の接
合が行われないのは勿論である。この場合、貫通孔5a
内の半田6は、リフロー炉内で加熱されたとき溶融する
が、貫通孔5aの直径が小さいため、溶融した半田6が
接続端子5の下方へ垂れ下がることはない。従って、そ
の場合には半田6の上端面6aは接続端子5の上端面と
同一面上にあり、下降しない。
On the other hand, IC packages and printed circuit boards
The solder may be deformed by heat or force from the outside after manufacturing, and the thickness of the cream solder may not be applied uniformly. For this reason, when the IC package is mounted on the printed circuit board, the ends of some of the connection terminals 5 may not contact the surface of the cream solder 7 in some cases. In such a case, it is needless to say that the connection between the electrode portion 4a and the connection terminal 5 is not performed. In this case, the through hole 5a
The inner solder 6 is melted when heated in the reflow furnace, but since the diameter of the through hole 5a is small, the melted solder 6 does not hang down below the connection terminal 5. Therefore, in that case, the upper end surface 6a of the solder 6 is on the same plane as the upper end surface of the connection terminal 5, and does not descend.

【0012】このようにしてリフロー炉内で半田付けが
行われた後、プリント基板をリフロー炉内から取り出
し、検査を行う。前記したように、接合が行われた場合
には接続端子5の上端面と半田6の上端面6aに差が生
じており、接合が行われなかった場合にはそれらの間に
差が生じていないため、ICパッケージの上方から目視
することによってその接合状態を容易に確認することが
できる。又、この検査を自動的に行う場合には、画像処
理技術を用いた周知の外観検査装置によって容易に確認
することが可能である。
After the soldering in the reflow furnace in this way, the printed circuit board is taken out of the reflow furnace and inspected. As described above, a difference occurs between the upper end surface of the connection terminal 5 and the upper end surface 6a of the solder 6 when joining is performed, and a difference occurs between them when joining is not performed. Therefore, the bonding state can be easily confirmed by visually observing the IC package from above. When this inspection is performed automatically, it can be easily confirmed by a well-known visual inspection device using an image processing technique.

【0013】又、上記の接合状態を色で確認できるよう
にすれば、その効果が一段と大きくなる。そのようにす
る場合の一例としては、図3(a)において接続端子5
の上端面に、半田6の上端面6aも含めて、金メッキを
施すようにすればよい。このようにすると、接合が行わ
れて半田6の上端面6aが下降するとき、金が半田6内
に溶け込み拡散してしまう。そのため、接続端子5の上
端面は金色で、半田6の上端面6aは半田色となり、は
っきりと確認することができる。他方、接合が行われな
い場合には、半田6の上端面6aにおいて、金は半田に
溶け込まず、半田内からの気泡跡を残して全体として金
色を維持している。又、金以外の物質であったとして
も、半田と反応して半田内に溶け込む性質を有し、且つ
半田とは全く異なる色の物質であれば、予め接続端子5
の上端面と半田6の上端面6aとに薄くコーティングし
ておくことにより、金の場合と同じ効果を得ることがで
きる。
Further, if the above-mentioned bonding state can be confirmed by color, the effect is further enhanced. As an example of such a case, the connection terminal 5 in FIG.
May be gold-plated, including the upper end surface 6 a of the solder 6. In this way, when the joining is performed and the upper end surface 6a of the solder 6 descends, the gold melts into the solder 6 and diffuses. Therefore, the upper end surface of the connection terminal 5 is gold, and the upper end surface 6a of the solder 6 is solder color, which can be clearly confirmed. On the other hand, when the joining is not performed, on the upper end surface 6a of the solder 6, the gold does not dissolve in the solder, and the gold remains as a whole except for the trace of bubbles from inside the solder. Even if it is a substance other than gold, if it has a property of reacting with the solder and melting into the solder and having a color completely different from that of the solder, the connection terminal 5
And the upper end surface 6a of the solder 6 is thinly coated, whereby the same effect as in the case of gold can be obtained.

【0014】また、半田6と接続端子5の界面に滑り易
いペースト状の物質、例えばワックスなどを塗布してお
くと、接合時に、半田の上端面6aの下降をスムーズに
し、また貫通孔5a外への半田6の流出量も大きくな
り、上端面6aの検出が容易となる。
If a slip-like paste-like substance, such as wax, is applied to the interface between the solder 6 and the connection terminal 5, the upper end surface 6a of the solder can be smoothly lowered at the time of joining, and the outside of the through hole 5a can be formed. The amount of the solder 6 flowing out to the upper surface also increases, and the detection of the upper end surface 6a becomes easy.

【0015】尚、上記の実施例においては接続端子5の
外形を砲弾型にしたが、本発明の接続端子は円筒形にし
ても角筒形にしても差し支えなく、要は管状をしてさえ
いればよい。又、ベース板1への取付けは圧入によらず
導電性接着剤や半田メッキによっても構わない。更に、
本発明は図4に示す第二の実施例のように複数のICチ
ップ2を搭載したICパッケージ(MCM型パッケー
ジ)として実施することもできるし、図5に示す第三の
実施例のようにICパッケージの放熱効果を得るため
に、接続端子5の長さを長く形成しても差し支えない。
In the above embodiment, the outer shape of the connection terminal 5 is a shell shape. However, the connection terminal of the present invention may be cylindrical or rectangular, and in other words, even if it is tubular. I just need to be. Further, the attachment to the base plate 1 may be performed by a conductive adhesive or solder plating instead of press-fitting. Furthermore,
The present invention can be implemented as an IC package (MCM type package) in which a plurality of IC chips 2 are mounted as in the second embodiment shown in FIG. 4, or as in the third embodiment shown in FIG. In order to obtain the heat radiation effect of the IC package, the length of the connection terminal 5 may be increased.

【0016】図6は、ベース部材1の下面中央にICチ
ップ2を搭載した場合を示す側面図で、ICチップ2の
周囲に、接続端子5が多数配置されている。このよう
に、ベース部材1の同一面上にICチップ2と接続端子
5を配置してもよい。また、場合によっては、ベース部
材1の両面にICチップ2を搭載してもよい。
FIG. 6 is a side view showing a case where the IC chip 2 is mounted at the center of the lower surface of the base member 1. A large number of connection terminals 5 are arranged around the IC chip 2. As described above, the IC chip 2 and the connection terminal 5 may be arranged on the same surface of the base member 1. In some cases, the IC chips 2 may be mounted on both sides of the base member 1.

【0017】[0017]

【発明の効果】上記のように本発明は、ICを装着した
ベース部材の一つの面に複数の接続端子を配置したタイ
プのICパッケージであるにも拘らず、プリント基板へ
の半田付けの確認を外観上から容易に行うことができる
という効果がある。又、半田を充填した接続端子の端面
に予め金メッキなどを施しておくことにより、色の差に
よっても確認することが可能となる。
As described above, according to the present invention, the soldering to the printed circuit board is confirmed in spite of an IC package in which a plurality of connection terminals are arranged on one surface of a base member on which the IC is mounted. Can be easily performed from the appearance. In addition, by preliminarily applying gold plating or the like to the end surfaces of the connection terminals filled with the solder, it is possible to confirm even by the color difference.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のICパッケージの一例を示す斜視図で
ある。
FIG. 1 is a perspective view showing an example of an IC package of the present invention.

【図2】図1のA−A線断面図である。FIG. 2 is a sectional view taken along line AA of FIG.

【図3】図1及び図2に示したICパッケージとプリン
ト基板との接合部を示す要部拡大断面図であり、(a)
はリフロー炉で加熱する前の状態を示し、(b)は加熱
後の状態を示している。
FIG. 3 is an enlarged sectional view of a main part showing a joint between the IC package shown in FIGS. 1 and 2 and a printed board;
Shows a state before heating in a reflow furnace, and (b) shows a state after heating.

【図4】第二の実施例の斜視図である。FIG. 4 is a perspective view of a second embodiment.

【図5】第三の実施例の一部断面説明図である。FIG. 5 is a partially sectional explanatory view of a third embodiment.

【図6】第四の実施例の一部断面説明図である。FIG. 6 is a partially sectional explanatory view of a fourth embodiment.

【図7】従来例の説明図である。FIG. 7 is an explanatory diagram of a conventional example.

【符号の説明】[Explanation of symbols]

1 ベース板 1a 配線パターン 2 ICチップ 2a IC素子 4 プリント基板 4a 電極部 5 接続端子 5a 貫通孔 6 半田 7 クリーム半田 DESCRIPTION OF SYMBOLS 1 Base plate 1a Wiring pattern 2 IC chip 2a IC element 4 Printed circuit board 4a Electrode part 5 Connection terminal 5a Through hole 6 Solder 7 Cream solder

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H01L 23/12 Continuation of front page (58) Field surveyed (Int.Cl. 7 , DB name) H01L 23/12

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 ICを装着したベース部材の一方の面に
外部回路等と接続するための複数の接続端子を配置した
ICパッケージにおいて、前記ベース部材におけるIC
の装着されていない位置に、内部に半田を充填した管状
の接続端子を、他方の面から前記ベース部材を貫通し、
その先端が前記ベース部材の前記一方の面へ突き出るよ
うに装着したことを特徴とするICパッケージ。
1. An IC package in which a plurality of connection terminals for connecting to an external circuit or the like are arranged on one surface of a base member on which the IC is mounted.
At a position where is not attached, a tubular connection terminal filled with solder inside, penetrates the base member from the other surface ,
An IC package , wherein a tip of the IC package is mounted so as to protrude to the one surface of the base member .
【請求項2】 前記接続端子の先端形状が徐々に細くな
るように形成されていることを特徴とする請求項1に記
載のICパッケージ。
2. The IC package according to claim 1, wherein a tip of the connection terminal is formed so as to be gradually thinned.
【請求項3】 前記接続端子は前記ベース部材に導電性
接着剤で装着されていることを特徴とする請求項1又は
2に記載のICパッケージ。
3. The IC package according to claim 1, wherein the connection terminal is mounted on the base member with a conductive adhesive.
【請求項4】 前記接続端子は、前記ベース部材への装
着前に、その外周面に導電性メッキが施されていること
を特徴とする請求項1又は2に記載のICパッケージ。
4. The IC package according to claim 1, wherein the connection terminal is provided with conductive plating on an outer peripheral surface thereof before being attached to the base member.
【請求項5】 前記接続端子の内部において、前記接続
端子と前記半田との界面に滑り易いペースト状の物質が
塗布されていることを特徴とする請求項1乃至4の何れ
かに記載のICパッケージ。
5. The IC according to claim 1, wherein a slip-like paste substance is applied to an interface between the connection terminal and the solder inside the connection terminal. package.
【請求項6】 前記半田がフラックスを含んだ半田であ
ることを特徴とする請求項1乃至5の何れかに記載のI
Cパッケージ。
6. The method according to claim 1, wherein the solder is a solder containing a flux.
C package.
【請求項7】 前記接続端子の前記外部回路等と接続す
る側とは反対側の端面に、半田と異なる色をしており且
つ半田に溶解する物質をコーティングしたことを特徴と
する請求項1乃至6の何れかに記載のICパッケージ。
7. The method of claim 1, characterized in that it has the the end surface opposite to the side where it is connected to an external circuit or the like, coated with a substance that dissolves in the solder and has a color different from that of solder of the connecting terminal 7. The IC package according to any one of claims 1 to 6 .
JP12766894A 1994-06-09 1994-06-09 IC package Expired - Fee Related JP3284758B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12766894A JP3284758B2 (en) 1994-06-09 1994-06-09 IC package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12766894A JP3284758B2 (en) 1994-06-09 1994-06-09 IC package

Publications (2)

Publication Number Publication Date
JPH07335780A JPH07335780A (en) 1995-12-22
JP3284758B2 true JP3284758B2 (en) 2002-05-20

Family

ID=14965773

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12766894A Expired - Fee Related JP3284758B2 (en) 1994-06-09 1994-06-09 IC package

Country Status (1)

Country Link
JP (1) JP3284758B2 (en)

Also Published As

Publication number Publication date
JPH07335780A (en) 1995-12-22

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