JP3281818B2 - Variable delay line circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay line circuit for delaying an input signal in accordance with external control data and outputting the delayed signal, and more particularly to an ASIC such as a gate array.
The present invention relates to a variable delay line circuit realized by (application-specific IC).

[0002]

2. Description of the Related Art VGA (Video Graphics Array) output from a personal computer or the like to a monitor device
When a video signal conforming to a standard such as SVGA, which is a signal output standard compatible with VGA, or SVGA, which is a signal output standard compatible with VGA, is taken into an external liquid crystal monitor, etc., the video is output at a pixel frequency corresponding to each signal output standard. It may be necessary to sample the signal.

In this case, if the phase between the sampling clock and the video signal is not optimally adjusted, the video signal cannot be accurately sampled, and the sampling causes the video signal to have a jitter or a change in signal amplitude level. Symptoms may appear.

Therefore, in order to adjust the phase between the sampling clock and the video signal, a variable delay line circuit that can change the delay amount of an input signal in accordance with an external control signal is required.

FIG. 5 is a schematic block diagram showing the entire configuration of a conventional variable delay line circuit 500. Variable delay line circuit 5
00 includes a delay circuit group 501 and a decode circuit 502.

The delay circuit group 501 receives an input signal IN to be delayed and outputs a plurality of delay signals having different delay times.

The decode circuit 502 includes a delay circuit group 501
, And selects and outputs a target delay signal based on delay amount designation data UX given from the outside.

The delay circuit group 501 includes cascaded inverter circuits A _{1 to} A _N. Each of the inverter circuits A _{1 to} A _N delays the input signal for a certain period and outputs the delayed signal. During this period, each of the inverter circuits A ₁ -A
Same for _N. The inverter circuit A ₁ receives the input signal IN
Receiving an input, and outputs to the inverter circuit A _2. Each of the inverter circuits A _{3 to} A _N receives at its input the output of the preceding inverter circuit A _{2 to} A _N-1 . Further, the outputs of the inverter circuits A _{1 to} A _N are input to the decode circuit 502 in parallel.

Next, the operation of the variable delay line circuit 500 will be described. The first-stage inverter circuit A _1, the input signal I
When N is input, the input signal IN is output as a delayed signal delayed for a certain period. This delayed signal, will be transmitted while being delayed by the sequential inverter circuit A ₂ to A _N.

The decode circuit 502 decodes the delay amount designating data UX input from the outside, and selects _one of the delay signals output from the inverter circuits A _{1 to} A _N.
Select and output the desired delay signal.

Therefore, by changing the delay designation data UX, a delay signal OUT obtained by delaying the input signal IN by an arbitrary time can be obtained.

However, variable delay line circuit 500
In the configuration of ( _1), the inverter circuit A ₁
~A due drift variations and delay characteristics of the performance of the _N and the like, when the delay amount of the delay signal OUT is finally output significantly deviates from the prescribed value is generated.

[0013] For example, taking the case where the variable delay line circuit 500 by the gate array as an example, the delay amount of the inverter circuit A ₁ to A _N are caused generally (standard delay × Kt × Kv × Kp ).

Here, Kt, Kv, and Kp are a temperature coefficient, a voltage coefficient, and a process coefficient for the delay amount of each of the delay circuits A _{1 to} A _N , respectively.

The temperature coefficient Kt takes a value of about 0.90 to 1.13 with respect to a change of the external environment temperature of -20 to + 75 ° C., and a change of the power supply voltage of 4.50 to 5.50 V with respect to the change.
The voltage coefficient Kv changes to a value of about 1.09 to 0.93. Then, with respect to process fluctuation (for example, daily fluctuation), the process coefficient Kp is set to 1.0 at normal time,
Approximately 0.6 when the fluctuation is minimum, and about 1.4 when the fluctuation is maximum.
To the value of.

Based on the variation of each of these coefficients, the variation of the delay amount of the variable delay line circuit formed on the cell of the same gate array is 25 ° C. even if there is no process variation. When the temperature changes from ° C. to 75 ° C., the power supply voltage increases by about 13%, and when the power supply voltage is changed from 5.0 volts to 4.5 volts, the power supply voltage increases by about 9%.

Further, when the factor of the process coefficient Kp is added to this variation, the variation of the delay amount between cells of each gate array may be twice or more at the maximum.

[0018]

That is, even when the configuration of the conventional variable delay line circuit 500 shown in FIG. 5 is realized on an ASIC, the delay line circuits A _{1 to} A _N constituting the circuit are also provided.
It is difficult to accurately obtain the target delay amount due to the influence of variations in characteristics such as characteristics and drift of the delay characteristics.
It is difficult to adopt.

In order to solve this problem, variable delay line circuits 600, 700 and 8 shown in FIGS.
00 has been proposed (Japanese Patent Application No. 8-102633),
Not yet known.

FIG. 6 is a schematic block diagram showing the entire configuration of the variable delay line circuit 600. 6, the variable delay line circuit 600 includes a signal generating circuit 10, a signal delay circuit 11, a delay amount detecting circuit 18, a control circuit 50, a waveform complementing circuit 13, and switching circuits 14 and 15.

The signal delay circuit 11 delays the input signal IN by a predetermined time in accordance with external control and outputs the delayed signal.

The signal delay circuit 11 includes a delay circuit group 16
Variable delay line circuit 5 shown in FIG.
It has the same configuration as 00.

The signal generation circuit 10 generates a reference signal M for monitoring the amount of delay of the signal delay circuit 11 and various control pulses.

The signal generation circuit 10 includes a crystal oscillation circuit 20 for generating an internal clock signal, and a reference signal generation circuit 19 for generating a reference signal M based on the internal clock signal.

The delay amount detecting circuit 18 includes a signal delay circuit 11
, The number of stages in the delay circuit group 16 necessary for delaying the reference signal M by a predetermined time is detected and output as reference data R.

The switching circuit 14 receives the input signal IN and the reference signal M, and selectively inputs either one to the signal delay circuit 11.

The waveform complementing circuit 13 receives the input signal IN and outputs an interpolation signal of a predetermined level.

Switching circuit 15 receives the outputs of signal delay circuit 11 and waveform complementing circuit 13 and selectively outputs one of the signals.

The control circuit 50 includes an arithmetic unit 51 and a switching circuit 12. Arithmetic unit 51 receives delay amount designation data CNT and reference data R input from the outside, and outputs control data DX. The switching circuit 12 switches between the reference data R and the control data DX to output to the signal delay circuit 11.

The selection circuit 17 selects and outputs one of a plurality of signals output from the delay circuit group 16 based on the control data DX.

The computing unit 51 corrects the delay amount designation data CNT based on the reference data R to obtain the control data DX.

More specifically, the control data DX (i) is given by the following equation. DX (i) = CNT × R (i) / N (1) Here, R (i) is reference data obtained in the i-th measurement, and the reference signal M is delayed by a certain period T. , N indicates the total number of delay circuits in the delay circuit group 16, and DX (i) indicates the number of delay circuits in the delay circuit group 16 using the i-th reference data R (i). The obtained control data DX is shown.

From the equation (1), the delay time of the input signal IN is expressed by the following equation. DTX (i) = Δdi × CNT × R (i) / N (2) Here, Δdi indicates the average delay time of each delay circuit of the delay circuit group 16 at the i-th measurement time.

By the way, the following equation (3) holds between T and Δdi and R (i).

T = Δdi × R (i) (constant value) (3) Therefore, using equation (3), equation (2) takes the following value.

DTX (i) = CNT × T / N (4) = K1 (constant value) (5) That is, the value of equation (4) does not depend on Δdi. Therefore, the delay time of the input signal IN can take a constant value irrespective of the variation of the delay time of each delay circuit of the delay circuit group 16.

That is, the variable delay line circuit 600 detects the influence of the variation and the drift of the characteristics of the delay circuit group 16 using the reference signal M, and outputs the reference data R, which is the result, of the delay amount with respect to the input signal IN. The above-mentioned problem is solved by reflecting it in the control.

FIG. 7 is a schematic block diagram showing the entire configuration of the variable delay line circuit 700.

In FIG. 7, the same portions as those of variable delay line circuit 600 shown in FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.

Variable delay line circuit 700 differs from variable delay line circuit 600 shown in FIG.
1 in that a signal delay circuit 21 is included.

The signal delay circuit 21 includes a delay circuit group 22 and
A selection circuit 23 that receives the outputs of the delay circuit group 22 in parallel;
Selection circuit 2 also receiving the output of delay circuit group 22 in parallel
4 is included. The selection circuit 23 selects one of a plurality of signals output from the delay circuit group 22 based on the reference data R received from the delay amount detection circuit 18 and outputs the selected signal to the delay amount detection circuit 18. The selection circuit 24 controls the control data DX
, One of a plurality of signals output from the delay circuit group 22 is selected and output.

Here, the control data DX is calculated by the arithmetic unit 51. FIG. 8 is a schematic block diagram showing the entire configuration of the variable delay line circuit 800.

8, the same parts as those of variable delay line circuit 700 shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

Variable delay line circuit 800 differs from variable delay line circuit 700 shown in FIG.
1 in that a signal delay circuit 31 is included.

The signal delay circuit 31 includes a delay circuit group 26 receiving an input signal IN, a delay circuit group 27 receiving a reference signal M as an input, a selection circuit 24 for selecting an output of the delay circuit group 26, and a delay circuit group. Selection circuit 23 for selecting the output of 27
And

Here, the control data DX for controlling the delay amount of the input signal is calculated by the arithmetic unit 51 similarly to the variable delay line circuit 600 and the variable delay line circuit 700.

As described above, the variable delay line circuits 600 and 7
00 and 800 detect variations and drifts in characteristics in the delay circuit groups 16, 22, 26 and 27,
This is reflected in the control of the delay amount for the input signal IN.

However, in an actual operation situation, not only the delay circuit group but also the selection circuit 17, the switching circuits 12, 14, 15 and the like in FIG. A delay also occurs in an input buffer (not shown) that takes in the input signal IN, an output buffer that transmits a delay signal to a subsequent circuit, and the like (hereinafter, referred to as an initial delay). In addition, the delay amount based on the initial delay is not constant and varies.

Therefore, even if the influence of the variation and the drift of the characteristics of the delay circuit group is suppressed, the variation of the initial delay occurring in the circuits other than the delay circuit group is added to the target delay signal without any change. There has been a problem that the signal delay time varies.

Therefore, the present invention has been made to solve the above-described problem, and has as its object to configure a variable delay line circuit in addition to delay variations caused by a delay circuit group. An object of the present invention is to realize a variable delay line circuit capable of performing a high-precision variable delay operation by suppressing variations in delay caused by various circuits.

Another object of the present invention is to provide an inexpensive AS.
An object of the present invention is to provide a variable delay line circuit capable of realizing a highly accurate delay also in an IC.

[0052]

A variable delay line circuit according to a first aspect of the present invention is a variable delay line circuit for delaying an input signal by a predetermined time in accordance with delay amount designation data received from the outside and outputting it as a delay signal. Receiving the delay amount designation data,
Control means for outputting corresponding control data; receiving a reference signal, delaying and outputting the reference signal in accordance with the reference data, and delaying the input signal in response to the control data in accordance with the control data. A delay unit that generates and outputs a signal; and a delay detection unit that receives a signal obtained by delaying the reference signal output from the delay unit, updates and outputs the reference data such that the reference signal is delayed by a predetermined time, and outputs the signal. The control means receives the reference data and the amount of offset delay from the outside, and updates the control data so that the input signal is delayed by a predetermined time in accordance with the delay amount designation data.

A variable delay line circuit according to a second aspect is the variable delay line circuit according to the first aspect, wherein the delay means switches between an input signal and a reference signal at a predetermined timing and outputs the input signal and the reference signal. Means, a plurality of delay circuit groups connected in cascade, which sequentially receive and output the output of the first switching means, and the outputs of the delay circuit groups are received in parallel, and a reference signal is based on reference data. Selecting means for selecting and outputting any one of the outputs, and selecting and outputting any one of the outputs based on the control data for the input signal; Receiving a signal obtained by delaying the signal, detecting the number of stages of a delay circuit required to delay the reference signal for a predetermined time, and outputting the reference data as reference data; The amount of delay A multiplying means for multiplying an output of the adding means by a proportional coefficient; and an arithmetic means for generating control data by subtracting an offset delay amount from an output of the multiplying means, and delaying the proportional coefficient by delaying the reference data. The value is divided by the total number of stages in the circuit.

The variable delay line circuit according to claim 3 is the variable delay line circuit according to claim 1, wherein the offset delay amount is an initial delay generated in a circuit constituting the variable delay line circuit, Indicates the maximum amount of delay among delays.

[0055]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a schematic block diagram showing an entire configuration of a variable delay line circuit 100 according to a first embodiment of the present invention. The same components as those of variable delay line circuit 600 in FIG. , And the description thereof is omitted.

The variable delay line circuit 100 according to the first embodiment of the present invention shown in FIG. 1 differs from the variable delay line circuit 600 shown in FIG.

The control circuit 1 includes an arithmetic unit 2 and a switching circuit 12. FIG. 2 is a schematic block diagram showing a configuration of the arithmetic unit 2 according to Embodiment 1 of the present invention.

Arithmetic unit 2 in Embodiment 1 of the present invention
Includes an offset addition circuit 3, a multiplication circuit 4, and a subtraction circuit 5.

The offset adding circuit 3 receives the delay amount designating data CNT and the offset delay amount F0 from outside, and
These are added and output.

The multiplication circuit 4 receives the output of the offset addition circuit 3 and the reference data R (i) from the delay amount detection circuit 18, performs the following calculation, and outputs a value Y (i).

Y (i) = (CNT + F0) × R (i) / N (6) Here, R (i) indicates reference data obtained in the i-th measurement, and N is a delay circuit group 16 shows the total number of stages of delay circuits included in 16.

The subtraction circuit 5 outputs the output Y (i) of the multiplication circuit 4
And the offset delay amount F0, the control data D
(I) is calculated. Expression (7) shows the control data D (i). D (i) is the i-th reference data R (i)
Shows control data D based on the value Y (i) calculated using

D (i) = Y (i) −F0 (7) = (CNT + F0) × R (i) / N−F0 (8) Here, the offset delay amount F0 is an initial value based on the initial delay. This shows the maximum value of the delay amount F. Here, the initial delay amount F
Is usually Δd times the offset delay amount F0 (here, Δ
d indicates an average delay time of each delay circuit constituting the delay circuit group 16, and has a value of 0.25 to 1.0. ) Value. Hereinafter, the case where the initial delay amount F takes the value of F0 is called the maximum variation due to the initial delay (hereinafter referred to as MAX time), and the case where the initial delay amount F takes a value of 0.5 times F0 is determined by the initial delay. Average time of variation (hereinafter referred to as TYP)
The case where the initial delay amount F takes a value 0.25 times the value of F0 is referred to as the minimum time of variation due to the initial delay (hereinafter referred to as MIN).

As described above, the variable delay line circuit 100 includes the delay detection circuit 18 similar to the conventional variable delay line circuit 600.
, The delay characteristic of each delay circuit in the delay circuit group 16 is detected, and further, the control circuit 1 corrects the delay amount designation data CNT based on the initial delay occurring in the circuit constituting the variable delay line circuit 100.

FIG. 3 is a diagram for explaining the delay time obtained by arithmetic unit 2 according to the first embodiment of the present invention, and shows the correspondence with the delay time obtained by conventional arithmetic unit 51.

In FIG. 3, (a) shows the delay time of the input signal IN when the initial delay variation is MAX, and (b) shows the delay time of the input signal IN when the initial delay variation is MIN. .

As shown in (a) and (b), when control data is calculated using the conventional arithmetic unit 51, the delay signal corresponds to the delay amount designation data CNT shown in the equation (5). Delay by the initial delay amount F in addition to the delay amount K1. In addition, since the initial delay amount F varies depending on external conditions, the obtained delay signal varies under the influence of the influence.

On the other hand, as shown in FIG. 3C, when the control data is calculated using the arithmetic unit 2 according to Embodiment 1 of the present invention, the delay amount corresponding to the initial delay amount F is added to the delay amount K1. By adding K3, the input signal IN becomes a delay signal DT (i) delayed by the delay amount K1 and a fixed amount K2 (offset delay amount). That is, as a whole,
It is possible to obtain a delay signal DT (i) in which variation in the initial delay is suppressed.

Hereinafter, the control data D calculated by the arithmetic unit 2 will be described.
Will be described. Here, the delay time D of the input signal obtained by the value Y (i) output from the multiplication circuit 4
A (i) is shown in equation (9).

DA (i) = Δd × Y (i) (9) Using equation (6), equation (9) has the following form.

DA (i) = Δd × (CNT + F0) × R (i) / N (10) Here, using the relationship of Expressions (3) and (5), Expression (10) is converted into Expression (11). ), (12) and (13).

DA (i) = (CNT + F0) × T / N (11) = K1 + K2 (12) K2 = F0 × T / N (13) Here, the values of K1 and K2 take constant values. . Therefore, according to Equation (12), the delay time realized by the value Y (i) is a constant value that does not depend on the average delay time Δd of the delay circuit that depends on temperature, voltage, process, and the like.

FIG. 4 is a diagram showing the relationship among various parameters in the variable delay line circuit 100. For simplicity, the delay amount designation data CNT is set to 0.

By substituting the values of (a) and (b) shown in FIG. 4 into equation (6), the value Y (i) of (c) in FIG. 4 is obtained. Further, when the value of (c) in FIG. 4 is substituted into Expression (10), the delay time DA (i) takes the following value as shown in (d) of FIG.

DA (i) = F0 (14) That is, Expression (10) indicates that the value becomes a constant value (offset delay amount F0) regardless of the dispersion of the initial delay.

Here, actually, when the input signal IN is delayed based on the value Y (i) obtained by the multiplication circuit 4, in addition to the delay amount K1 and the delay amount K2 corresponding to the offset delay amount F0, Further, it is output after being delayed by the initial delay amount F (= F0 × △ d).

Therefore, in the subtraction circuit 5, the influence of the delay based on the initial delay is subtracted from the value Y (i) based on the equation (7).

Therefore, the control data D of the equation (7)
The delay time DT (i) realized by (i) takes the following values.

DT (i) = DA (i) −F0 × △ d (15) = K1 + K2-F0 × △ d (16) = K1 + (K2-F) (17) = K1 + K3 (18) K3 represents delay compensation for the above-described initial delay (see FIG. 3C).

As a result, in the variable delay line circuit 100, the input signal IN is delayed by the time obtained by adding the delay amount K1 corresponding to the delay amount designation data CNT and the fixed amount (K2) regardless of the variation of the initial delay. This is output as a signal.

The variable delay line circuit 700 shown in FIG.
Also in the variable delay line circuit 800 shown in FIG.
The same effect can be obtained by using the computing unit 2 according to the first embodiment of the present invention instead of the computing unit 51.

[0082]

According to the first embodiment of the present invention, in a variable delay line circuit which delays an input signal in accordance with delay amount designation data from the outside and outputs it as a delay signal, the variable delay line circuit passes through various constituent circuits. Even when the induced delay varies due to fluctuations in external conditions (voltage, temperature, etc.), a highly accurate delay signal can be output.

Further, by forming the circuit elements constituting the variable delay line circuit on the ASIC, the number of components can be greatly reduced, and a highly accurate and inexpensive variable delay line circuit can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram illustrating an overall configuration of a variable delay line circuit according to a first embodiment.

FIG. 2 is a schematic block diagram illustrating an overall configuration of a computing unit according to the first embodiment.

FIG. 3 is a diagram for explaining a delay time obtained by an arithmetic unit according to the first embodiment.

FIG. 4 is a diagram illustrating a relationship between various parameters in the variable delay line circuit according to the first embodiment;

FIG. 5 is a schematic block diagram showing the entire configuration of a conventional variable delay line circuit.

FIG. 6 is a schematic block diagram showing the entire configuration of a conventional variable delay line circuit.

FIG. 7 is a schematic block diagram showing an entire configuration of a conventional variable delay line circuit.

FIG. 8 is a schematic block diagram showing the entire configuration of a conventional variable delay line circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 variable delay line circuit 1 control circuit 2 arithmetic unit 3 offset addition circuit 4 multiplication circuit 5 subtraction circuit 10 signal generation circuit 11 signal delay circuit 18 delay amount detection circuit 12, 14 switching circuit 16 delay circuit group 17 selection circuit 19 reference signal generation Circuit 20 Crystal oscillation circuit

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-3-235513 (JP, A) JP-A-4-331507 (JP, A) JP-A-1-175408 (JP, A) JP-A-9- 289436 (JP, A) JP-A-9-321590 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H03K 5/13

Claims (3)

(57) [Claims] 1. A variable delay line circuit for delaying an input signal by a predetermined time in accordance with delay amount designating data received from the outside and outputting the same as a delay signal, wherein the variable delay line circuit receives the delay amount designating data and receives corresponding control data. A control means for outputting a reference signal, receiving the reference signal, delaying the reference signal in accordance with reference data, and outputting the input signal, and delaying the input signal in accordance with the control data to achieve the desired delay. Delay means for generating and outputting a signal; delay detection for receiving a signal obtained by delaying the reference signal output from the delay means and updating and outputting the reference data so that the reference signal is delayed by a predetermined time Means for receiving the reference data and the offset delay amount from the outside so that the input signal is delayed by the predetermined time in accordance with the delay amount designation data. Updates the control data, the variable delay line circuit. 2. A delay unit comprising: a first switching unit that switches between the input signal and the reference signal at a predetermined timing and outputs the received signal; and a cascade that receives and sequentially transmits the output of the first switching unit. A plurality of connected delay circuit groups, receiving in parallel the outputs of the delay circuit group, selecting and outputting one of the outputs based on the reference data for the reference signal, Selecting means for selecting and outputting any one of the outputs based on the control data with respect to the signal, wherein the delay detecting means receives a signal obtained by delaying the reference signal output from the delay means Means for detecting the number of stages of the delay circuit required to delay the reference signal for the predetermined time, and outputting the same as the reference data. An addition unit that adds the offset amount to the offset amount; a multiplication unit that multiplies the output of the addition unit by a proportional coefficient; and an operation unit that generates the control data by subtracting the offset delay amount from the output of the multiplication unit. The variable delay line circuit according to claim 1, wherein the proportional coefficient is a value obtained by dividing the reference data by the total number of stages of the delay circuit. 3. The variable delay according to claim 1, wherein the offset delay amount is an initial delay generated in a circuit constituting the variable delay line circuit, and indicates a maximum delay amount among the initial delays. Line circuit.