JP3281575B2 - Display control system and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention connects a display control device having an image memory for storing image information and a plurality of display devices, and controls the display of an image based on the image information on the plurality of display devices. The present invention relates to a display control system and a control method thereof.

[0002]

2. Description of the Related Art As a display device such as a computer device, a CRT display device is generally known. But,
Since this CRT display device requires a certain depth in the thickness direction of the display screen, the volume of the CRT display device becomes large as a whole, and it is difficult to reduce the size of the entire system. Further, in such display control of the CRT display device, it is necessary to constantly refresh the display data using a CRTC (CRT controller) or the like, and the display control has been complicated.

As a display device capable of compensating for the above-mentioned drawbacks of the conventional CRT display device, the size of the display device has been reduced.
In particular, there is a liquid crystal display device that can be made thinner. Some of such liquid crystal display devices include a ferroelectric liquid crystal (hereinafter, FLC: Ferr).
There is a display device (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of an oelectric liquid crystal. One of the features is that the liquid crystal cell has a preservability of a display state with respect to application of an electric field. That is, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC element therein is oriented in a first stable state or a second stable state depending on the direction of application of the electric field, and excluding the electric field. Also maintain their respective alignment states. Due to the bistability of such an FLC element, an FLCD utilizing it has a memorization of a display state. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-1987.
76357.

In such an FLCD display control device, there is no need to constantly refresh the screen unlike the CRT display control device. By preferentially updating the display content of the display area corresponding to the portion where the content of the display memory has been updated, there is an advantage that a large screen can be displayed without lowering the refresh rate.

[0005] As an application example of such a display device, a plurality of display devices are installed in an event held in a large venue such as an exhibition or a demonstration, and the same image information is placed on the plurality of display devices. By displaying, the same image information can be provided to a large number of people. On the other hand, the following three forms are known as display control systems that display different image information on a plurality of display devices.

(1) LAN connection system A plurality of host computers are connected using a LAN, and a display device is connected to each host computer via a display control device. (2) Multiple graphic subsystem method A plurality of display control devices are mounted on one host computer. Then, the display devices are connected to the respective display control devices.

(3) Display memory division method A display memory on a single host computer and a single display control device is logically divided into a plurality of memory regions, and a plurality of display devices connecting the respective memory regions are provided. Assign to

[0008]

However, in order to output the same image information or different image information to each display device by using a plurality of the conventional display devices, a display control device for controlling each display device. Needed the same number. In particular, in the case of image information different for a plurality of display devices, each of the above-described methods has the following disadvantages.

(1) LAN connection method One host computer and one display control device are required for one display device, so that the cost increases. Further, since it is necessary to control a plurality of host computers, the control program becomes large-scale and complicated. (2) Multiple Graphic Subsystem Method One display control device is required for one display device, so that the cost increases. In addition, since the number of display control devices that can be mounted on one host computer is limited, the number of connectable display devices is limited.

(3) Display memory division method It is necessary to sequentially read data from a memory area divided into a plurality of memory areas. For this reason, the number of display devices that can be connected is limited by the speed at which data can be read from the display memory. The present invention has been made in view of the above problems, and a display control of a plurality of display devices can be controlled by a single display control device, and a flexible display device is not limited to the number of connected display devices. It is an object to provide a display control system and a control method thereof.

[0011]

A display control system according to the present invention for achieving the above object has the following arrangement. That is, a display control system that connects a display control device having an image memory for storing image information and a plurality of display devices, and controls display of an image based on the image information on the plurality of display devices. Monitoring means for monitoring the presence or absence of an image information request signal output from each display device of the display device, and image information stored in an image memory of the display control device based on a monitoring result of the monitoring means. Distributing means for distributing the plurality of display devices to each display device.

[0012] Preferably, when an image request signal is output from all of the plurality of display devices as a result of monitoring by the monitoring device, the distributing device includes image information stored in an image memory of the display control device. Is distributed to each of the plurality of display devices. Preferably, when there is a display device that is not electrically connected to the next stage after the first display device and an image information request signal is output from the first display device, the monitoring means It is determined that an image information request signal has been output from a display device that is not electrically connected to the next stage after the first display device.

Preferably, a display device directly connected to the display control device is not electrically connected, and an image information request signal is sent from a display device connected to the next stage of the display device and subsequent stages. When output, the monitoring means:
It is determined that the image information request signal has been output from the display device immediately below the display control device. Also, preferably, the power supply for operating the monitoring means and the distribution means,
Supplied from the display control device.

Preferably, the display device is a liquid crystal display device using a ferroelectric liquid crystal. Preferably, the image processing apparatus further includes a relay device connected to the first display device, connected to the display control device or the second display device at a preceding stage, and connected to a third display device at a subsequent stage.

[0015] Preferably, the relay device includes first receiving means for receiving an image information request signal output from the third display device connected at a subsequent stage, and an image output from the first display device. A second receiving unit for receiving an information request signal, and a predetermined signal transmitted to the display control device or the second display device connected to a preceding stage based on the image information request signal received by the first receiving unit and the second receiving unit. And transmitting means for transmitting the data.

Preferably, when image information has been transmitted from a preceding stage, the transmitting means transmits the image information to the first display device and the third display device. A control method of a display control system according to the present invention for achieving the above object has the following configuration. That is, a control method of a display control system for connecting a display control device having an image memory for storing image information and a plurality of display devices and controlling display of an image based on the image information on the plurality of display devices. A monitoring step of monitoring the presence or absence of an image information request signal output from each display device of the plurality of display devices,
A distribution step of distributing image information stored in an image memory of the display control device to each of the plurality of display devices based on a monitoring result of the monitoring process.

A display control system according to the present invention for achieving the above object has the following configuration. That is, a display control system that connects a display control device having an image storage memory for storing image information and a plurality of display devices, and controls display of an image based on the image information on the plurality of display devices, and apparatus information storage means for storing device information for designating a display destination of the display device of the information, the transfer request based on the information
Zui, the said device information, and an output line address of the display device, and an output means for outputting the image information to be displayed on the display line specified by the output line address, the display that is designated by the device information The apparatus can display an image based on the image information on a display line specified by the output line address and receive the image information.
When the function becomes available, a request for information transfer is made .

Further, preferably, each of the plurality of display devices are assigned a unique identification ID, before
The device information storage means stores an identification ID of the display device.
You. Preferably, one of the plurality of display devices is provided.
Of the plurality of display devices is displayed on the operation screen display device.
Display control means for displaying another ID, wherein the device information
The storage means is instructed on the operation screen display device.
The identification ID is stored.

Preferably, the display control means includes:
ID for targeting all of the plurality of display devices
Is displayed on the operation screen display device. Preferably, the display control means further includes a plurality of image files.
Information on the operation screen display device,
The output means outputs one image from a plurality of image files.
Outputs image information of a file.

A control method of a display control system according to the present invention for achieving the above object has the following configuration. That is, the present invention relates to a control method of a display control system for connecting a display control device having an image storage memory for storing image information and a plurality of display devices, and controlling display of an image based on the image information to the plurality of display devices. A storage step of storing device information specifying a display device to which image information is to be displayed in the device information storage means; and based on the information transfer request, the device information, an output line address of the display device, An output step of outputting image information to be displayed on a display line specified by a line address, and a display device specified by the device information is displayed on a display line specified by the output line address. When the display of image based on the co
Information when it becomes possible to receive image information
Request for transfer .

A computer readable memory according to the present invention for achieving the above object has the following configuration. That is,
A display control device having an image memory for storing image information is connected to a plurality of display devices, and a control program code of a display control system for controlling display of an image based on the image information to the plurality of display devices is stored. A computer-readable memory, the program code of a monitoring step of monitoring the presence or absence of the output of an image information request signal output from each display device of the plurality of display devices, based on a monitoring result of the monitoring step, A program code for a distribution step of distributing image information stored in the image memory of the display control device to each of the plurality of display devices.

A computer readable memory according to the present invention for achieving the above object has the following configuration. That is,
A display control device having an image memory for storing image information is connected to a plurality of display devices, and a control program code of a display control system for controlling display of an image based on the image information to the plurality of display devices is stored. Computer-readable memory, comprising: a program code for a designation step of designating a display device on which image information is to be displayed; and a control for controlling display of an image based on the image information for the display device designated in the designation step. Process code.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. <First Embodiment> FIG. 1 is a diagram showing a schematic configuration of a display control system according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a host computer, which controls the entire display control system. Reference numeral 2 denotes an FLCD, which is used as a display device for image data such as various characters and image information output from the host computer 1. Reference numeral 3 denotes a repeater, which controls an FLCD display output from the host computer 1.
The LCD control signal is distributed to one FLCD 2 and further to the FLCD 2 connected at a later stage.

With the display control system having the above configuration, image data such as various characters and image information output from one host computer 1 is transmitted to each FLCD.
2 are simultaneously displayed on the display screen. Therefore, the user can simultaneously obtain the same image information at each location where each FLCD 2 is installed.

Next, a detailed configuration of the host computer 1 will be described with reference to FIG. FIG. 2 is a block diagram showing a detailed configuration of the host computer according to the first embodiment of the present invention. In FIG. 2, reference numeral 101 denotes a host CPU, which controls the entire display control system of the embodiment. 10
A bridge 6 interfaces between the host CPU 101 and the high-speed bus (PCI bus) 102.
Reference numeral 105 denotes a DRAM, which is used as a main memory and has a C
The control program executed by the PU 101 is stored, and is used as a work area when the CPU 101 performs control processing. A high-speed bus (PCI bus) 102 includes an address bus, a control bus, a data bus, and the like.

Reference numeral 103 denotes a medium speed bus, for example, ISA
Consists of a bus. A bridge 107 connects the high speed bus 102 and the medium speed bus 103. A system ROM 104 stores various programs such as a program for performing an initialization process of the entire display control system. 112
Is a display controller (display controller), which controls an interface with the FLCD 2.

Reference numeral 108 denotes an I / O controller having a parallel or serial interface, and also having a disk interface for the hard disk device 4 and the floppy disk device 5. Reference numeral 109 denotes a keyboard (KBD) controller, which is a keyboard 6 for inputting characters such as characters and numbers and other inputs.
The interface with the mouse 7 is controlled. Reference numeral 110 denotes a real-time clock, which also has a timer function for counting clocks and measuring time. An audio subsystem 111 inputs an audio signal from a microphone and outputs it to the medium speed bus 103, or outputs an audible signal to a speaker based on a signal from the medium speed bus 103.

Next, a detailed configuration of the display controller 112 will be described with reference to FIG. FIG. 3 is a block diagram illustrating a detailed configuration of the display controller according to the first embodiment of the present invention. 3, an SVGA 201 using an existing SVGA, which is a display control circuit for a CRT, is used as the display controller 112. Before describing the detailed configuration of the display controller 112 shown in FIG.
The detailed configuration of the VGA 201 will be described with reference to FIG.

FIG. 4 is a block diagram showing a detailed configuration of the SVGA according to the first embodiment of the present invention. In FIG. 4, for example, display data rewritten and displayed in a window area of a display memory of the display controller 112 is controlled by the PCI bus 102 under the control of the host CPU 101.
Is transferred to the display controller 112 via
It is temporarily stored in the FIFO 216. The bank address data for projecting the window area of the display memory to an arbitrary area of the VRAM 202 is also stored in the PCI bus 102.
Is transferred to the display controller 112 via the.

Then, the command from the host CPU 101, the above-mentioned bank address data, and data such as control information are transferred to the SVGA 201 as register set data. Further, data indicating the state of the SVGA 201 is transferred from the SVGA 201 to the host CPU 101 as register get data (see FIG. 3). FIFO21
6 are sequentially output from the FIFO 216, and are output from the bus interface unit 217 or V according to the type of data.
It is set in each register in the GA 222. VGA22
2 can know the bank address data, its display data, and data such as control commands based on the state of the data set in these registers.

The VGA 222 generates a corresponding VRAM address in the VRAM 202 based on the address of the window area of the display memory and the bank address data. At the same time, strobe signals RAS and CAS as memory control signals, a chip select signal CS, and a write enable signal WE are transferred to the VRAM 202 via the memory interface unit 220. As a result, display data can be written to the VRAM address. At this time, the rewritten display data is transferred to the VRAM 202 via the memory interface unit 220 in the same procedure.

On the other hand, the VGA 222 converts display data of the VRAM 202 specified by a request line address transferred from a line address
Similarly, the data is read from the VRAM 202 in accordance with the line data transfer enable signal transferred and stored in the FIFO 221. From the FIFO 221, the display data is transmitted to the FLCD 2 in the order in which the display data is stored.

The SVGA 201 is further provided with a data manipulator 218 and a graphics engine 219 that perform an accelerator function. For example, the host CPU 101
When data on the circle and its center and radius are set in the register 7 and drawing of the circle is instructed, the graphics engine 219 generates display data for drawing the circle,
The data manipulator 218 transmits this data to the VRAM 202 via the memory interface unit 220.
Write to.

The rewrite detection / flag generation circuit 223 outputs the VG
A222 monitors the VRAM address generated, and
The VRAM address when the display data of M202 is rewritten (written), that is, when the write enable signal and the chip select signal CS become "1", is fetched. Then, a line address is calculated based on the VRAM address, VRAM address offset, total line number, and total line bit number data obtained from the host CPU 101. The concept of this calculation is shown in FIG.

FIG. 5 is a diagram for explaining the concept of line address calculation according to the first embodiment of the present invention. As shown in FIG. 5, the pixel indicated by the address X on the VRAM 202 corresponds to the line N on the FLCD screen. Each line is composed of a plurality of pixels, and each pixel is composed of a plurality (n
) Bytes. The line address (line number N) at this time is calculated as follows.

N = 1 + ｛(VRAM address: X)-
(Display start address)｝ / (number of pixels in one line) × (1
The rewrite detection / flag generation circuit 223 sets a flag in the partial rewrite line flag register 224 according to the calculated line address. VRAM 20 at this time
FIG. 6 shows the relationship between the bit line 2 and the partial rewriting line flag
Shown in

FIG. 6 is a diagram showing the relationship between the VRAM and the partial rewrite line flag register according to the first embodiment of the present invention. FIG.
As shown in (1), for example, when the corresponding address on the VRAM 202 is rewritten to display the character "L", the rewritten line address is detected by the above calculation. Then, a flag is set in the partial rewrite line flag register 224 corresponding to this address ("1" is set).

Next, the description returns to FIG. CPU 203
Reads the contents of the partial rewrite line flag register 224 via the line address generation circuit 204 and sends the line address in which the flag is set to the SVGA 201. At this time, the line address generation circuit 204 sends out a line data transfer enable signal corresponding to the line address data, and
21), the display data of the above address is transferred to the binary halftone processing circuit 206.

The binarized halftone processing circuit 206 includes R, G,
B (5 bits each: 32K colors) or R (3 bits),
G (3 bits), B (2 bits) (total 256 colors),
The multi-value display data represented by R, G, B, and I (luminance) (1 bit: 16 colors) is converted into binary pixel data corresponding to each pixel on the display screen of the FLCD 2. still,
As shown in FIG. 7, one pixel of the display screen of the first embodiment has display cells having different areas for each color. The FLCD 2 has a display area of 1280 pixels in the horizontal direction and 1024 lines in the vertical direction. Of these, the effective display area is 1024 pixels × 768 lines excluding the hatched portion.

Next, the data format of the display data will be described with reference to FIG. FIG. 8 is a diagram showing a data format of display data according to the first embodiment of the present invention. FIG. 8A shows a data format of the display line A shown in FIG. 7, in which a line address is added at the head, and the pixel data portion of the display line is entirely composed of border pixel data. FIG. 8B shows the data format of the display line B shown in FIG. 7, in which a line address is added at the head, and the pixel data portion of the display line is the pixel data to be actually displayed and the two ends. It is composed of border pixel data. Each pixel of the displayed pixel data has two bits (R1, R2, G
1, G2, B1, B2). Therefore, the binarized halftone processing circuit 206 converts the 15-bit, 8-bit, or 4-bit RGB display data into 2-bit data for each color (that is, each color of RGB is represented by quaternary pixel data). Convert.

The binarization halftone processing method used in the binarization halftone processing circuit 206 may be a known one. Examples of such a method include an error diffusion method and an average density method. , Dither method and the like are known. Returning to the description of FIG. The border generation circuit 205 has the FLCD2
The pixel data of the border portion on the display screen is generated. That is, as shown in FIG. 7, the display screen of the FLCD 2 has 1024 lines composed of 1280 pixels, and among these display screens, a border portion (shaded portion) which is not used for display is used as a display screen. It is formed to border.
The pixel data of the border portion generated by the border generation circuit 205 is serially synthesized by the synthesis circuit 207 with the pixel data from the binary halftone processing circuit 206. Further, the combined pixel data is combined with the display line address from the line address generation circuit 204 in the combining circuit 208, and then sent to the FLCD 2 via the driver 209.

Next, the timing for transferring the display line address and the pixel data to the FLCD 2 will be described with reference to FIG. FIG. 9 is a timing chart showing the timing for transferring the display line address and the pixel data to the FLCD according to the first embodiment of the present invention. In FIG. 9, the display line address and the pixel data are 8 AD0 to AD7.
It is assumed that the data is transferred to the FLCD 2 as bit parallel data.

First, a synchronization signal HSYNC indicating a data transmission request is input from the FLCD 2 to the line address generation circuit 204 via the receiver 213. Next, the line address generation circuit 204 sets the requested line address to S
Send it to the VGA 201. Here, the synchronization signal HSYNC
Is a negative logic signal indicating a data transmission request when the LOW level is “0”.

As a result, the SVGA 201 outputs display data corresponding to the requested line address. At the same time, the line address generating circuit 204 sets the identification signal AHDL for identifying the display line address and the pixel data to HIGH.
FLCD2 is set to level “1” via driver 210
And the display line address is set to FLCD2.
Transfer to

When the transfer of the display line address to the FLCD 2 is completed, the identification signal AHDL is set to LOW level “0” and output to the FLCD 2 via the driver 210. At the same time, the pixel data from the SVGA 201 via the binarized halftone processing circuit 206 and the synthesizing circuits 207 and 208 is transferred to the FLCD 2 via the driver 209. Here, the identification signal AHD indicates that the display line address is output to the signal lines from AD0 to AD7 when it is at the HIGH level “1”. Also, LO
When W level is “0”, it indicates that pixel data is output to the signal lines from AD0 to AD7.

The CPU 203 performs each control of the configuration of the display controller 112 described above. That is, the CPU 203 sends the FLCD
2, information of the total number of lines, the total number of pixels, and the cursor information of the display screen are received. Further, the CPU 203 sends the VRAM address offset, the total number of lines, and the total number of pixels to the rewrite detection / flag generation circuit 223. Further, the partial rewrite line flag register 224 is initialized. Further, the display start line address, the number of continuous display lines, the total number of lines, the total number of pixels, and each data of the border area are sent to the line address generation circuit 204, and the partial rewrite line flag information is obtained from the line address generation circuit 204. . Further, the CPU 203 sends each data of the bandwidth, the total number of pixels, and the processing mode to the binary halftone processing circuit 206 and sends the border pattern data to the border generating circuit 205. Also, CPU2
03 outputs a reset signal for initializing the FLCD 2 to the FLCD 2 via the driver 212. Also,
A command for turning the FLCD 2 into a static state, which is a standby state, and a command for turning off the backlight of the FLCD 2 and putting it into a sleep state are transmitted to the driver 211.
To the FLCD 2 via the.

As described above, the host CPU 101
, Through the high-speed bus 102, a certain drawing command is sent to the display controller 112. And F
Synchronization signal HSYN indicating a data transmission request from LCD2
Every time C is output, the updated display line address and display data are output to the signal lines AD0 to AD7 and transferred to the FLCD 2 via the FLCD interface connector 214. The FLCD interface connector 214 combines signal lines for controlling the above-described FLCD 2 into one connector. The display controller 112 and the FLCD 2 are connected via the FLCD interface connector 214. The repeater 3 shown in FIG.
BOXPOW for supplying a voltage for operating the device (in this embodiment, it is assumed to operate at 5 volts)
Is also connected to the FLCD via the FLCD interface connector 214.
It is supplied to the LCD 2. 215 indicates a state where the signal BOXPOW is short-circuited to the ground voltage (ground).
This is a fuse for preventing an overcurrent from flowing.

Now, in the display control system in which a plurality of FLCDs 2 are connected as shown in FIG. 1, various control signals in the display controller 112 described above are distributed to each FLCD 2 via the repeater 3. Next, the configuration of the repeater 3 will be described with reference to FIG. <Description of Repeater 3> FIG. 10 is a block diagram showing the structure of the repeater according to the first embodiment of the present invention.

In FIG. 10, reference numerals 301 to 303 denote connectors. The connector 301 transmits and receives an FLCD control signal of the FLCD 2 to and from the host computer 1.
The connector 302 transmits and receives FLCD control signals to and from the FLCD 2. The connector 303 is a repeater 3 of the next stage.
The transmission / reception of the FLCD control signal is performed between the transmission / reception device and the device. 305-3
Reference numeral 07 denotes a driver, and signal lines AD0 to AD7, AHDL, and FLCD 2 output from the host computer 1.
A reset signal and a command signal for controlling the driver are connected to the drivers 306 and 307 via the connector 301 and then via the receiver 308. The output from the driver 306 is output to the FLCD 2 via the connector 302. The output from the driver 307 is output from the connector 30.
3 to the next-stage repeater 3.

Signal HSYNC output from FLCD 2
Is connected to one input signal line of the OR gate 304 via the receiver 309 after passing through the connector 302. The signal HSYNC output from the next-stage repeater 3 is
After passing through the connector 303, it is connected to the other input signal line of the OR gate 304 via the receiver 310. The output from the OR gate 304 is connected to the connector 301 via the driver 305, and is output to the host computer 1.

Reference numeral 311 denotes a resistor.
This is for forcibly setting the signal HSYNC from the FLCD 2 to the LOW level “0” when the LCD 2 is not connected. Therefore, one of the resistors 311 is connected to the signal HSYNC between the connector 302 and the receiver 309.
And the other is connected to the ground voltage (ground). Thereby, the FLCD 2 is not connected to the repeater 3 or the FL connected to the repeater 3
When the power of the CD 2 is not turned on and the FLCD 2 connected to the repeater 3 is not operating, one input line of the OR gate 304 connected to the output of the receiver 309 is forced to be LOW. The level is set to “0”. OR
The output from the gate 304 changes according to the state of the signal HSYNC output from the other input line, ie, the repeater 3 at the next stage. That is, the next-stage repeater 3
Signal HSYNC output from is high level "1"
In this case, the output of the OR gate 304 becomes HIGH level "1". Also, when the LOW level is “0”, O
The output of the R gate 304 becomes LOW level “0”.

Reference numeral 312 denotes a resistor, and when the repeater 3 is not connected to the next stage, a signal H from the next stage repeater 3 is output.
This is for forcing SYNC to a low level “0”. Therefore, one of the resistors 312 is connected to the signal line of the signal HSYNC between the connector 303 and the receiver 310, and the other is connected to the ground voltage (ground). Thereby, when the repeater 3 is not connected to the next stage, one input line of the OR gate 304 connected to the output of the receiver 310 is forcibly set to the LOW level “0”. O
The output from R gate 304 changes according to the state of signal HSYNC output from the other input line, that is, FLCD2. That is, when the signal HSYNC output from the FLCD 2 is at the HIHG level “1”, the output of the OR gate 304 is at the HIGH level “1”.
Becomes When the LOW level is “0”, the output of the OR gate 304 is at the LOW level “0”.

The signal BOXPOW output from the host computer 1 is supplied to the OR gate 304, the drivers 305 to 307, and the receivers 308 to 3 constituting the repeater 3.
10 is a signal for supplying power to the power supply 10. The connector 30
After being connected to the repeater 3 via the connector 1, it is output to the next repeater 3 via the connector 303 as it is. By connecting the repeater 3 described above to a plurality of FLCDs 2, a plurality of FLCDs 2 can be connected to one host computer 1.
Can be connected.

Next, the timing of transferring the display line address and the pixel data to the plurality of FLCDs 2 will be described with reference to FIG. FIG. 11 is a timing chart showing the timing for transferring the display line address and the pixel data to a plurality of FLCDs according to the first embodiment of the present invention.
Note that the description of FIG. 11 is based on three FLs as shown in FIG.
The case of a display control system to which the CD 2 is connected will be described as an example. As shown in FIG.
21, FLCD22 and FLCD23 output a synchronization signal HSYNC2 indicating a data transmission request asynchronously.
1, HSYNC22 and HSYNC23 are output. In the repeater 33, the repeater 3 is not connected to the next stage. Therefore, the repeater 33 is connected to the FLCD connected to itself.
When the synchronizing signal HSYNC 23 output from the H. 23 goes to the LOW level “0”, the HSYNC 33 is set to the LOW level “0” and output to the repeater 32 in the preceding stage.

In the repeater 32, the synchronization signal HSYNC 23 output from the repeater 33 connected to the next stage
The synchronization signal HSYNC22 output from the FLCD 22 connected to the repeater 32 becomes W level "0".
Becomes low level “0”, the HSYNC 32
Is output as a LOW level “0” to the repeater 31 at the preceding stage.

Similarly, in the repeater 31, the synchronization signal HSYNC22 output from the repeater 32 connected to the next stage is output.
Becomes LOW level “0”, and the synchronization signal HSYN output from the FLCD 21 connected to the repeater 31
When C21 becomes LOW level “0”, HSNY
C31 is output to the host computer 1 as LOW level “0”.

In the host computer 1, HSYNC3
When 1 is detected to be LOW level “0”, the identification signal AHD for identifying the display line address and the pixel data.
L is set to HIGH level “1” and the display line address is transferred to the repeater 31. When the transfer of the display line address is completed, the identification signal AHDL is set to LOW.
The level is set to “0” and the pixel data is transferred to the repeater 3. In this manner, the signal lines AD0 to AD7 output from the host computer 1 and the identification signal AHDL
Is FL through the repeater 31, the repeater 32, and the repeater 33.
Output to CD21, FLCD22, FLCD23.
Subsequently, when the pixel data is output from the host computer 1, the same image information is simultaneously displayed on the display screens of the FLCD 21, FLCD 22, and FLCD 23.

Each of the FLCD 21, FLCD 22,
HSYNC21, HSYNC output from FLCD23
C22 and HSYNC23 are respectively FLCD21,
By detecting that the pixel data is output from the host computer 1 by the FLCD 22 and the FLCD 23,
It is returned to HIGH level "1". Thereafter, after one line of pixel data is output from the host computer 1,
Again, the FLCD 21, FLCD 22, and FLCD 23 output the synchronization signals HSYNC 21, HSYNC 22, HSYNC 23.
To a low level “0”, the computer 1 repeatedly outputs pixel data. In this way, the same image information can be repeatedly displayed on the display screens of the FLCD 21, FLCD 22, and FLCD 23 at the same time.

Next, an outline of processing executed by the display control system of the first embodiment will be described with reference to FIG. FIG. 13 is a flowchart showing the processing executed in the first embodiment of the present invention. First, in step S101, it is determined whether HSYNC is output from a relay connected to the next stage in a certain relay. HS
If YNC is not output (N in step S101)
O), wait until output. On the other hand, when HSYNC is output (YES in step S101), the process proceeds to step S102.

Next, it is determined whether the synchronization signal HSYNC has been output from the display device to which the repeater itself is connected (step S102). Synchronization signal HSYN from display device
If C is not output (N in step S102)
O), wait until output. On the other hand, when the synchronization signal HSYNC is output from the display device (step S102).
YES), and proceeds to step S102.

Next, the apparatus connected to the preceding stage is
YNC is output (step S103). Next, it is determined whether the device connected to the preceding stage is a host computer (step S104). If it is not the host computer (NO in step S104), step S101
Return to On the other hand, if it is the host computer (YES in step S104), the process proceeds to step S105.

Then, display data is received from the host computer (step S105). The received display data is sequentially transmitted to the repeaters connected to the next and subsequent stages (step S106). As described above, according to the first embodiment, the presence or absence of the output of the image information request signal output from one display device and the display device connected thereafter is monitored, and based on the monitoring result, By providing a repeater capable of distributing image information output from a display control device to all display devices, a plurality of display devices can be connected to one display control device, and the same display image can be simultaneously generated by a plurality of display devices. It can be displayed on one display device. This allows
The same image information can be simultaneously displayed on a plurality of display devices arranged in a large venue such as a presentation venue or a demonstration venue.

<Second Embodiment> In a second embodiment, a display control system capable of displaying different image information on a plurality of display devices by using one display control device will be described. FIG. 14 is a diagram illustrating a schematic configuration of the display control system according to the second embodiment of the present invention. In FIG. 14, reference numeral 1101 denotes a host computer, which controls the entire display control system. Reference numeral 1102 denotes a keyboard; 1103, a mouse for inputting characters such as characters and numerals and other inputs.
Reference numerals 1104 to 1108 denote FLCDs, and FLCD-I /
It is connected to the host computer 1101 via the F1109, and is used as a display device for image information such as various characters and images output from the host computer 1101. Further, each of the FLCDs 1104 to 1108 is assigned a device ID (other than 0) unique to the device. 1
Reference numerals 110 to 1114 denote repeaters, which connect the host computer 1101 and the FLCDs 1104-1108 in a daisy chain.

Next, the detailed configuration of the FLCD-I / F 1109 will be described with reference to FIG. FIG. 15 is a block diagram showing details of the FLCD-I / F according to the second embodiment of the present invention. In FIG. 15, the host computer 11
First, a host CPU (not shown) incorporated in the microcontroller 01 notifies the microcontroller 204 of the device ID of the display destination FLCD via a serial I / F. The microcontroller 1204 sets the device ID notified from the host CPU in the device ID setting register 1240 of the frame memory control circuit 1207.

Subsequently, the host CPU connects to the system bus 1
230, display data is transferred to the display memory 1202 via the SVGA 1201. The display data is R
It has the form of 24-bit data expressing 256 gradations for each color of GB. The SVGA 1201 sequentially displays display data of the corresponding display memory addresses from left to right and from top to bottom of the display screen.
202 and transferred to the binary halftone processing circuit 1206. At this time, together with the display data, a data enable indicating the display data valid period and the reference clock Dot
Clock, Hsync indicating a horizontal synchronization signal, and Vsync indicating a vertical synchronization signal are also transferred.

The binarized halftone processing circuit 1206 has RGB
The multi-level display data of 256 gradations represented by 8 bits for each color is converted into 16-level pixel data corresponding to a display screen of an FLCD (not shown). In the second embodiment, one pixel on the display screen is composed of four dots of R, G, B, and I.
As a binarization intermediate processing method performed by the binarization halftone processing circuit 1206, an error diffusion method (ED method) for performing error diffusion in band units (units of a plurality of lines) is used.

The pixel data generated by the binary halftone processing circuit 206 is sent to the frame memory control circuit 1207 in synchronization with the data enable signal. The frame memory control circuit 1207 controls the horizontal synchronization signal Hsy
nc, a frame memory 12 calculated from a value indicated by a line counter (not shown) according to a vertical synchronization signal Vsync.
The pixel data is written to the frame memory address of No. 34. When writing the pixel data to the frame memory 1234, the pixel data is read from the frame memory 1234 at the same time.

Then, the comparator 1220 compares the written pixel data with the read pixel data. As a result of the comparison, if the pixel data is different, it is determined that the pixel data has been rewritten, and the rewrite flag register 1221 is determined.
Is set to 1 (ON) at the position corresponding to.
The rewrite flag register 1221 is composed of a bit string indicating whether or not a band corresponding to each bit has been rewritten.

The microcontroller 1204 reads the rewrite flag from the rewrite flag register 1235 in the frame memory control circuit 1207. This allows
The rewrite line in the next display on the FLCD is determined,
This is set in the frame memory control circuit 1207.
At this time, an area where the rewrite flag is ON is preferentially displayed.

The frame memory control circuit 1207 controls the FL
In response to a data request signal from a CD, the frame memory 1
The pixel data is read from the output line position designated by the microcontroller
Send to D. At this time, the microcontroller 1204
Multiplexes and transmits the device ID, output line address, and pixel data specified by the device.

The FLCD specified by the device ID is
The pixel data received from the FLCD-I / F 1109 is displayed at the line position specified by the line address on the display screen. When the reception of one line of pixel data is completed and the next one line of pixel data can be received, a data request signal is transmitted to the frame memory control circuit 1207. When device ID = 0 is specified, the pixel data is transmitted to all connected FLCDs.

Next, a specific configuration example of the display control system according to the second embodiment will be described with reference to FIG. FIG.
FIG. 6 is a diagram illustrating a specific configuration example of a display control system according to a second embodiment of the present invention. FLCD 1104 shown in FIG.
Is a display device for displaying an operation screen for controlling the display control system. The user operates this operation screen to determine an FLCD to be displayed and to make various settings. F
The LCDs 1105 to 1108 display an image based on the pixel data transmitted from the host computer according to the contents set by the FLCD 1104.

Next, details of the operation screen displayed on FLCD 1104 will be described with reference to FIG. FIG.
FIG. 7 is a diagram illustrating details of an operation screen for controlling the display control system according to the second embodiment of the present invention. In FIG.
The user can operate the mouse pointer 401 to perform a drag-and-drop operation. Window 4
An icon 10 displays an image of an image registered in the host computer 301 in advance. Here, icons 411 to 416 of registered image files are displayed as icons. In this window 410, the user can, of course, additionally register a new image file or delete a registered file. Window 420 is the FLCD shown in FIG.
Icon 4 of the display state of the display screen of 1105-1108
22 to 425 are displayed as icons.

When the user sets the image file to be displayed on the FLCD of the display destination, the user drags the image file to be displayed from the image file displayed as an icon in the window 410, and Is dropped on the FLCD where is displayed. When an image file dragged on the icon 430 “Display on all devices” in the window 420 is dropped,
All the FLCDs other than the FLCD displaying the operation screen are set to be the display destinations of the image file.

The operation screen shown in FIG. 17 displays the icon 411 of the image file on the icon 42 of the FLCD 1106.
3, the icon 412 of the image file is displayed on the FLCD 110.
5. Icon 422, icon 42 of FLCD 1107
4, the icon 413 of the image file is displayed on the FLCD 110.
8 shows a state in which drag and drop is performed on the icon 425 of FIG.

Next, an outline of the processing executed by the display control system according to the second embodiment will be described with reference to FIG. FIG. 18 is a flowchart showing processing executed in the second embodiment of the present invention. Here, a process executed when the user requests display of an image on a certain display device will be described as an example.

In step S501, an image display request from the user is awaited. Here, the image display request is
The user drags the icon of the image file on the operation screen and drops the icon on the FLCD icon.
In step S502, the image ID of the image file dragged by the user and the device ID of the FLCD are acquired.
In step S503, a dummy device ID that does not exist as a device ID is set to the device I of the FLCD-I / F 1109.
It is set in the D setting register 1240. This is to prevent the display of incomplete (halfway display data being written) during the writing of image data to the display memory 1202 in step 504.

In step S504, step S5
The image file of the image ID acquired in 02 is written in the display memory 1202. In step S505, the device ID obtained in step 502 is replaced with the FLCD-I
/ F1109 in the device ID setting register 1240. Thus, image display on the FLCD specified by the user is started. In step S506, a wait is performed for a certain time. This wait time is a time sufficient for the FLCD to scan one screen (one frame).

In step S507, the device ID of the FLCD for displaying the operation screen is set to FLCD-I / F 1109.
Is set in the device ID setting register 1240. In step S508, the contents of the operation screen are written into the display memory 1202, and the operation screen is restored. afterwards,
Returning to step 502, the system waits for an image display request from the user.

As described above, according to the second embodiment, it is possible to realize a display control system for controlling display on one host computer and a plurality of display devices. This makes it possible to provide a low-cost, flexible display control system in which the number of connected display devices is not limited. The present invention may be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, a printer, and the like).

Further, an object of the present invention is to supply a storage medium storing a program code of software for realizing the functions of the above-described embodiments to a system or an apparatus, and to provide a computer (or CPU) of the system or the apparatus.
And MPU) read and execute the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. As a storage medium for supplying the program code, for example, a floppy disk, a hard disk, an optical disk, a magneto-optical disk,
A CD-ROM, CD-R, magnetic tape, nonvolatile memory card, ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) May perform some or all of the actual processing, and the processing may realize the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written to a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the program code is read based on the instruction of the program code. It goes without saying that the CPU included in the function expansion board or the function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing.

When the present invention is applied to the storage medium, the storage medium stores program codes corresponding to the above-described flowcharts. Each module shown in the example will be stored in the storage medium. That is, in the first embodiment, at least the program code of each of the “monitoring module” and the “distribution module” may be stored in the storage medium.

The "monitoring module" monitors the output of the image information request signal output from each of the plurality of display devices. The “distribution module” distributes the image information stored in the image memory of the display control device to each of the plurality of display devices based on the monitoring result. Also,
In the second embodiment, at least the program code of each of the “designated module” and the “control module” may be stored in the storage medium.

The "designation module" designates a display device to which image information is to be displayed. The “control module” controls display of an image based on image information on a designated display device.

[0088]

As described above, according to the present invention,
It is possible to provide a flexible display control system and a control method thereof, in which display control of a plurality of display devices can be controlled by a single display control device and is not limited by the number of connected display devices.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a schematic configuration of a display control system according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a host computer according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a detailed configuration of a display controller according to the first embodiment of the present invention.

FIG. 4 is a block diagram illustrating a detailed configuration of an SVGA according to the first embodiment of the present invention.

FIG. 5 is a diagram for explaining the concept of line address calculation according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a relationship between a VRAM and a partial rewrite line flag register according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a display screen of the FLCD according to the first embodiment of the present invention.

FIG. 8 is a diagram illustrating a data format of display data according to the first embodiment of the present invention.

FIG. 9 is a timing chart showing a timing of transferring a display line address and pixel data to an FLCD according to the first embodiment of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a repeater according to the first embodiment of the present invention.

FIG. 11 is a timing chart showing a timing of transferring a display line address and pixel data to a plurality of FLCDs according to the first embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration example of a display control system according to the first embodiment of the present invention.

FIG. 13 is an overall view of an embodiment of the present invention.

FIG. 14 is a diagram illustrating a schematic configuration of a display control system according to a second embodiment of the present invention.

FIG. 15 is a block diagram illustrating details of an FLCD-I / F according to a second embodiment of the present invention.

FIG. 16 is a diagram illustrating a specific configuration example of a display control system according to a second embodiment of the present invention.

FIG. 17 is a diagram illustrating details of an operation screen for controlling the display control system according to the second embodiment of the present invention.

FIG. 18 is a flowchart illustrating processing executed in the second embodiment of the present invention.

FIG. 19 is a diagram showing a structure of a memory map of a storage medium storing a program code for realizing an embodiment of the present invention.

FIG. 20 is a diagram showing a structure of a memory map of a storage medium storing a program code for realizing an embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Host computer 2, 21, 22, 23 FLCD 3, 31, 32, 33 Repeater 4 Hard disk drive 5 Floppy disk drive 6 Keyboard 7 Mouse 101 Host CPU 102 High-speed bus 103 Medium-speed bus 104 System ROM 105 DRAM 106, 107 Bridge 108 I / O controller 109 Keyboard controller 110 Real-time clock 111 Audio subsystem 112 Display controller 201 SVGA 202 VRAM 203 CPU 204 Line address generator 205 Border generator 206 Binary halftone processing circuit 207, 208 Synthesis circuit 209, 210, 211, 212, 305, 306, 3
07 Driver 213, 308, 309, 310 Receiver 214 FLCD interface connector 215 Fuse 216, 221 FIFO 217 Bus interface unit 218 Data manipulator 219 Graphic engine 220 Memory interface unit 222 VGA 223 Rewrite detection / flag generation circuit 224 Partial rewrite line flag register 301 , 302, 303 Connector 304 OR gate 311, 312 Resistor

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Morimoto Hajime 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Yuichi Matsumoto 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inside (72) Inventor Kenji Inoue 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Nobuharu Ichihashi 3-30-2, Shimomaruko, Ota-ku, Tokyo Canon Inc. ( 56) References JP-A-9-163032 (JP, A) JP-A-8-328514 (JP, A) JP-A-5-100644 (JP, A) JP-A-64-38826 (JP, A) Hei 2-226333 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G09G 3/00-5/42 G02F 1/133 505-580 G06F 3/14-3/153 340

Claims (10)

(57) [Claims] 1. A display control system for connecting a display control device having an image storage memory for storing image information and a plurality of display devices, and controlling display of an image based on the image information on the plurality of display devices. A device information storage unit that stores device information that specifies a display device to which image information is to be displayed; and, based on the information transfer request, the device information, the output line address of the display device, and the output line address. Output means for outputting image information to be displayed on a specified display line, wherein a display device specified by the device information is displayed on a display line specified by the output line address, based on the image information. Display and receive image information
A display control system, wherein a request for information transfer is made when it becomes possible . 2. The apparatus according to claim 1, wherein a unique identification ID is assigned to each of the plurality of display devices, and the device information storage unit stores the identification ID of the display device. Display control system. 3. An operation screen display device among one of the plurality of display devices, further comprising: display control means for displaying identification IDs of the plurality of display devices; The display control system according to claim 2, wherein the identification ID specified on the screen display device is stored. 4. The display control according to claim 3, wherein the display control means displays an identification ID for targeting all of the plurality of display devices on the operation screen display device. system. 5. The display control means further displays information indicating a plurality of image files on the operation screen display device, and the output means includes an image of one image file among the plurality of image files. The display control system according to claim 3, wherein information is output. 6. A control of a display control system for connecting a display control device having an image storage memory for storing image information and a plurality of display devices, and controlling display of an image based on the image information on the plurality of display devices. A method of storing device information specifying a display device on which image information is to be displayed in a device information storage unit; and, based on a request for information transfer, the device information, an output line address of a display device, and An output step of outputting image information to be displayed on a display line specified by the output line address, and a display device specified by the device information, a display line specified by the output line address, Displaying an image based on the image information and receiving the image information;
A request for information transfer when the display becomes possible . 7. The display device according to claim 6, wherein a unique identification ID is assigned to each of the plurality of display devices, and the device information storage unit stores the identification ID of the display device. Control method of display control system. 8. A display control step of displaying identification IDs of the plurality of display devices on one operation screen display device among the plurality of display devices, wherein the device information storage unit performs the operation. The control method of the display control system according to claim 7, wherein the identification ID specified on the screen display device is stored. 9. The display control according to claim 8, wherein in the display control step, an identification ID for targeting all of the plurality of display devices is displayed on the operation screen display device. How to control the system. 10. The display control step further displays information indicating a plurality of image files on the operation screen display device, and the output step includes the step of displaying an image of one image file among the plurality of image files. 9. The control method for a display control system according to claim 8, wherein information is output.