JP3280490B2 - Thermal head - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermal head for printing on a recording medium such as a thermal paper or a thermal transfer film by causing a current corresponding to a printing signal to be selectively supplied to a plurality of heating elements to generate heat. About.

[0002]

2. Description of the Related Art FIG. 25 is a block diagram of a typical conventional thermal head 1. As shown in FIG. In the thermal head 1, a heating resistor 4 is connected to the common electrode 2, and a switching element 6 such as a power transistor is individually connected to the other end of each heating resistor 4 via an individual electrode 5. . An output terminal of each switching element 6 is commonly connected to a ground wiring 7, and a control signal input terminal of each switching element 6 is connected to an AND element 8.
The switching element 6 and the AND element 8 are formed in a drive circuit element 9 formed by an integrated circuit technology. In the drive circuit element 9, a shift register 10 having the same number of bits as the number of all the AND elements 8 is further provided. And a latch circuit 11 are formed.

In this conventional example, it is assumed that there are 24 heating resistors 4 and that the heating resistors 4 are divided into four blocks B1 to B4 in the order of arrangement. Therefore, 24 switching elements 6 and AND elements 8 are used each, and the AND elements 8 include the blocks B1 to B
The strobe signals XSB 1 to XS
B4 is input. Each strobe signal XSB1
To XSB4 are low-active signals. Therefore, each of the strobe signals XSB1 to XSB4 is
2 are respectively connected.

As shown in FIG. 26, heating resistors R1 to R
Numeral 24 designates scanning lines arranged linearly along the longitudinal direction of the substrate to form a scanning line. While closely transporting a thermosensitive recording medium substantially equal to the length of the scanning line, each heating resistor R1 to R
An image can be formed on a thermosensitive recording medium by selectively driving 24 in response to a print signal.

FIG. 27 is a timing chart for explaining the operation of the thermal head 1. The print data D is input to the shift register 10 as a serial signal together with the clock signal CK as shown in FIGS. 20 (1) and 20 (2). At a predetermined timing, the latch signal LT shown in FIG. 20C is input to the latch circuit 11, and the data of the shift register 10 is latched. Thereafter, the strobe signal XSB1 in FIG.
Commonly input to the D element 8.

As a result, the print data D latched by the latch circuit 11 is output to the switching element 6 of the first block B1. The switching element 6 is set to a conductive or cut-off state in accordance with print data. In the conductive state, a current from the common electrode 2 flows to the ground wiring 7 via the heating resistor 4, and the switching element 6 Is driven to generate heat. Thereafter, the corresponding strobe signals XSB2 to XSB4 are sequentially applied to the blocks B2 to B4, and the printing operation continues.

Here, while the strobe signal XSB4 is being output, the print data D of the next line is output from the control device 13 together with the clock signal CK, and is stored in the shift register 10. Further, the timing of storing the print data D of the next line in the shift register 10 may be performed during a period during which any of the strobe signals XSB1 to XSB4 is output as long as the latch signal LT is output.

[0008]

However, in the conventional thermal head 1, in the drive circuit element 9 used, the AND elements 8 are formed in the same number as the heating resistors 4, and the shift register 10 and the latch circuit 11 are used. Also, the number of bits is required to be the same as the number of the heating resistors 4, and there is a problem that the configuration of the drive circuit element 9 becomes complicated and the cost increases.

In addition, there is a problem that the drive circuit element 9 is large and it is difficult to reduce the size of the thermal head 1 because the configuration is complicated.

Further, since the printing operation period and the data transfer period are set separately, there is a problem that the entire printing time becomes longer.

An object of the present invention is to provide a thermal head capable of simplifying the circuit configuration and shortening the printing time in order to solve the above-mentioned problems.

[0012]

SUMMARY OF THE INVENTION The present invention provides a plurality of heating elements, a plurality of switching elements individually connected to each heating element, a gate element individually connected to each switching element, and a plurality of switching elements. A driving circuit element including a connected shift register, wherein the plurality of heating elements are divided into a plurality of blocks, and a gate element of each block has the same bit as the number of heating elements of each block. Are connected to the plurality of shift registers, and the same number of strobe signals as the number of sections of the block are respectively input to the gate elements corresponding to each block, and when the printing of each block is activated, the shift corresponding to the block is performed. A clock gate element for preventing clock input to the register is provided for each block, and each gate element Further, each of the small blocks is divided into a plurality of small blocks, and a gate control element for controlling a driving state of a gate element corresponding to each small block is provided for each small block. The gate control element activates the small block. A thermal head is connected in series so that gate control data for setting a state can be transferred.

[0013]

Further, the present invention is characterized in that the plurality of heating elements are shifted in a direction intersecting the arrangement direction of the heating resistors for each of the small blocks.

[0015]

[0016]

According to the present invention, a plurality of heating elements are divided into a plurality of blocks, and shift registers are also divided corresponding to the blocks, and each shift register is further divided into a plurality of small blocks. Since the same number of strobe signals as the number of divisions of the small block are input to the gate element corresponding to each small block, time division driving for each small block becomes possible. In addition, when a small block is activated for printing, a clock gate element for preventing a clock input to a shift register corresponding to the small block is provided for each small block, thereby eliminating a latch circuit which was conventionally indispensable. In addition, data can be transferred to another small block during the printing operation of the small block. Further, each gate element is further divided into a plurality of small blocks, and a gate control element for controlling the driving state of the gate element corresponding to each small block is provided for each small block, so that the time division driving is divided. The number of times or the print block can be set arbitrarily. Therefore, the influence of the voltage drop at the common electrode to which each heating element is commonly connected can be reduced, and the print density fluctuation can be suppressed. In addition, the gate control elements are connected in series so that gate control data for activating the small blocks can be transferred, so that the small blocks are sequentially driven according to the contents of the gate control data. can do. Therefore, it is possible to effectively prevent the number of input signals from increasing with the increase in the number of blocks and the wiring from becoming complicated.

[0017]

[0018]

Further, according to the present invention, the position of each heating resistor divided into small blocks is shifted in a direction crossing the arrangement direction of the heating resistors. Therefore,
The recording medium is conveyed in a direction intersecting the arrangement direction of the heating resistors, and the printing dots for each small block that are individually recorded at the time of each divided driving in which the heating resistors are time-divisionally driven for each small block are recorded. It is possible to form a high quality printed image which is aligned on a medium and has no distortion on the recording medium.

[0020]

FIG. 1A is a block diagram showing an electrical configuration of a thermal head having a clock gate element.
FIG. 1B is a schematic plan view showing the appearance of the thermal head. The thermal head includes a plurality of heating resistors R1 to R1.
R2048 and drive circuit elements IC0 to IC31 for driving the respective heating resistors R1 to R2048, and a total of four blocks including 512 heating resistors and eight drive circuit elements as one block B1 to B4.

One end of each of the heating resistors R1 to R2048 is commonly connected, and is supplied with a voltage VH. Block B
The drive circuit elements IC0 to IC7 of the first block and the drive circuit elements IC8 to IC15 of the block B2 form a series of print signals DI.
Are connected in series so that is continuously transferred,
Similarly, the drive circuit elements IC16 to IC23 of the block B3 and the drive circuit elements IC24 to IC31 of the block B4 are connected in series so that a series of print signals DI are continuously transferred. The driving circuit elements IC0 to IC0
A clock signal CLK for transferring the print signal DI is supplied to C31. Further, a strobe signal STB1 for determining the drive timing of the heating resistors R1 to R512 in the block B4 is supplied to the driving circuit elements IC24 to IC31, and similarly, the heating resistor R513 in the block B3.
Strobe signal STB2 for determining the drive timing of the drive circuit elements IC16 to R1024 is connected to the drive circuit elements IC16 to IC23, and the heating resistors R1024 to R153 of the block B2 are
No. 6 strobe signal STB3 for determining drive timing
Are connected to IC8 to IC15, and a strobe signal STB4 for determining the drive timing of the heating resistors R1537 to R2048 of the block B1 is connected to IC0 to IC7. A thermistor TH for temperature detection is attached to a part of the substrate of the thermal head, and signals THM1 and THM2 are provided.
Is output. The power supply and the voltage VD of the drive circuit elements IC0 to IC31 are supplied and connected to the ground line GND.

As shown in FIG. 1B, the heating resistor R1
R2048 to R2048 are arranged linearly along the longitudinal direction of the substrate to form scanning lines. While closely contacting and transporting a thermosensitive recording medium having a length substantially equal to the length of the scanning lines, print signals are applied to the respective heating resistors R1 to R2048. , An image can be formed on a heat-sensitive recording medium.

FIG. 2 shows the driving circuit element IC0 shown in FIG.
FIG. 3 is a block diagram showing an electrical configuration of IC 31. Each of the drive circuit elements IC0 to IC31 includes flip-flops FF1 to FF64 forming a 64-bit shift register.
AND elements G1 to G64 connected to the outputs of the flip-flops FF1 to FF64, and AND elements G1 to G64
Switching elements T1 to T6 connected to the output of G64
4, a NOT element Ga for inverting a strobe signal input from the STROBE terminal and inputting the inverted signal to each of the AND elements G1 to G64, and a strobe signal input from the STROBE terminal and a clock signal input from the CLOCK terminal. By taking a logical product, each flip-flop FF1
And an AND element Gb for inputting to the FF64.
The output side of each switching element T1 to T64 is connected to each heating resistor. As shown in FIG. 1A, when the respective drive circuit elements IC0 to IC31 are connected in series,
The DATAOUT terminal of the previous stage is connected to the DATAIN terminal of the next stage, and the clock signal CL in FIG.
K is input to all drive circuit elements IC0 to IC31,
Each strobe signal STB1 to STB4 is
The signals are input to all the drive circuit elements corresponding to 1 to B4.

FIG. 3 is an overall configuration diagram of the thermal head of FIG. 1, shown for easy comparison with the conventional thermal head of FIG. The thermal head 20 has a common electrode 3
0 is connected to one end of each heating resistor 24, and the other end of each heating resistor 24 is connected via an individual electrode 25 to each other.
Switching elements 26 are individually connected. An output terminal of each switching element 26 is commonly connected to a ground wiring 27, and a control signal input terminal of each switching element 26 is connected to an AND element 28. Further, the output of the shift register 21 for transferring the print signal DI is
Connected to one input of element 28. The strobe signals STB1 to STB4 are input via the NOT elements 22 to the AND elements 28 corresponding to the blocks B1 to B4, respectively. Then, the AND of the strobe signal STB4 and the clock signal CLK is calculated by the AND element 29, and is input to the shift register 21 of the block B1.
Similarly, strobe signal STB3 and clock signal CLK
Is calculated by the AND element 29 and input to the shift register 21 of the block B2. Further, the AND of the strobe signal STB2 and the clock signal CLK is
The operation is performed by the D element 29 and input to the shift register 21 of the block B3. The AND of the strobe signal STB1 and the clock signal CLK is calculated by the AND element 29 and input to the shift register 21 of the block B4. The thermal head 20 is controlled by a control device 23 such as a computer.

Next, the operation of the thermal head thus configured will be described. FIGS. 4 to 6 are timing charts showing the operation of the thermal head shown in FIGS.

First, in FIG. 4, data corresponding to blocks B4 and B3 of the data for one line is input as a print signal DI. At this time, since each of the strobe signals STB1 to STB4 is at a high level, the clock signal CLK is directly input to the shift register corresponding to each of the blocks B1 to B4, and the data of the block B4 is stored in the blocks B2 and B4. The data is transferred to the shift register, and the data of the block B3 is transferred to the shift registers of the blocks B1 and B3. While the print signal DI is being transferred to the shift register of each block, each of the strobe signals STB1 to STB
Since TB4 is at the high level, each heating resistor is not driven.

Next, when the strobe signal STB1 is inverted to a low level, a current selectively flows through the heating resistor in this portion based on the data stored in the shift register of the block B4, and the block B4 performs a printing operation. Do.

Next, when the strobe signal STB1 returns to the high level and the strobe signal STB2 inverts to the low level, the printing operation of the block B4 is completed, and based on the data stored in the shift register of the block B3. A current selectively flows through the heating resistors in the portion, and the block B3 performs a printing operation. While the strobe signal STB2 maintains the low level, the data of the blocks B2 and B1 are again input to the shift register of each block as the print signal DI, but the input of the clock signal CLK is blocked in the shift register of the block B3. Therefore, after all, the data of the block B2 is transferred to the shift register of the block 2, and the data of the block B1 is transferred to the shift register of the block B1.

Next, when the strobe signal STB2 returns to the high level and the strobe signal STB3 inverts to the low level, the printing operation of the block B3 ends, and based on the data stored in the shift register of the block B2.
A current selectively flows through the heating resistor in this portion, and the printing operation of the block B2 is performed.

Next, when the strobe signal STB3 returns to the high level and the strobe signal STB4 inverts to the low level, the printing operation of the block B2 ends, and based on the data stored in the shift register of the block B1,
A current selectively flows through the heating resistor in this portion, and the block B1 performs a printing operation. While the strobe signal STB4 keeps the low level, the data of the blocks B4 and B3 of the next line is again input to the shift register of each block as the print signal DI, but the clock signal CLK is input to the shift register of the block B1. Therefore, the data of block B4 is transferred to the shift register of block B4, and the data of block B3 is transferred to the shift register of block B3. In this manner, during the level inversion period of each of the strobe signals STB1 to STB4, the input of the clock signal CLK is prevented in the shift register of another block, so that the data transfer of another block can be performed during the printing operation of one block. it can.

FIG. 5 is a timing chart showing another operation example of the thermal head. In this operation example, in the data transfer period of the print signal DI and each of the strobe signals STB1 to STB1.
Since the level inversion period of STB4 does not overlap, the entire printing time is longer than in FIG. First, the data of the blocks B4 and B3 are transferred to the shift register of each block by the clock signal CLK, and then, when the strobe signal STB1 is inverted to a low level, the block B
4 performs a printing operation, and then when the strobe signal STB2 is inverted to a low level, the block B3 performs a printing operation.

Next, the data of the blocks B2 and B1 are transferred to the shift register of each block by the clock signal CLK, and when the strobe signal STB3 is inverted to a low level, the block B2 performs a printing operation, and then the strobe signal STB3. When STB4 is inverted to low level, block B1 performs a printing operation.

FIG. 6 is a timing chart showing another operation example of the thermal head. In this operation example, the level inversion period of the strobe STB2 and the data transfer period of the printing signal DI partially overlap, but when the strobe signal STB2 returns to the high level, the block B
Since the printing operation of No. 3 has been completed, even if the clock signal CLK is subsequently input to the shift register of the block B3 and erroneous data is stored, it is overwritten by the next cycle of data transfer, so that printing is performed. There is no. The operation in FIG. 6 is the same as that in FIG.

As described above, the blocks B1 and B2 are set as one group, and the blocks B3 and B4 are set as another group, and the data transfer is performed collectively. Thereafter, the strobe signal STB corresponding to each of the blocks B1 to B4 is set.
1 to STB4 to perform time-division driving, and at the time of printing operation of each block, a clock signal CL for data transfer.
By preventing K, printing operation and data transfer can be performed simultaneously in each group.

FIG. 7 is a block diagram showing an electrical configuration of a thermal head according to an embodiment of the present invention. In this thermal head, the plurality of heating resistors 24 are divided into eight blocks B11 to B14 and B21 to B24, one end of which is commonly connected to the common electrode 30 to be supplied with the voltage VH. Is connected to the switching element 26 individually via each individual electrode 25. The output terminal of each switching element 26 is commonly connected to a ground wiring 27, and each switching element 2
The output of the AND element 28 is connected to each of the control signal input terminals 6. Further, the output of the shift register 21 for transferring the print signal DI is connected to the input of each AND element 28. Two strobe signals STB1, STB2
Correspond to each of the blocks B11 to B1 via the NOT element 22.
4, and are input to the AND elements 28 corresponding to B21 to B24, respectively. The AND of the strobe signal STB1 and the clock signal CK1 is calculated by the AND element 29, and the shift register 21 of each of the blocks B11 to B14 is operated.
Is input to Similarly, the AND of the strobe signal STB2 and the clock signal CK1 is calculated by the AND element 29, and the shift register 21 of each of the blocks B21 to B24 is operated.
Is input to

The shift registers 21 of the blocks B11 to B14 are connected in series so that the print signal DI is continuously transferred, and similarly, the shift registers of the blocks B21 to B24 are also connected in series. . Further, an enable register E1 composed of a 1-bit shift register
1 to E14 and E21 to E24 correspond to the respective blocks B11 to B1.
4, provided for each of B21 to B24, and the output thereof is connected to the AND element 28 of each of the blocks B11 to B14 and B21 to B24. Each enable register E11
To E14 and E21 to E24 have the drive control signal ENB,
They are connected so as to be sequentially transferred by a clock signal CK2. The thermal head thus configured is controlled by a control device 23 such as a computer. The switching element 26, the AND element 28, the shift register 21, the enable registers E11 to E14, E2
1 to E24 are the driving circuit elements 3 in the integrated circuit technology.
4 are formed.

FIG. 8 is a block diagram showing an electrical configuration of a drive circuit element for driving the 64 heating resistors shown in FIG. 7 as one block. This drive circuit element includes flip-flops FF1 to FF64 forming a 64-bit shift register and each flip-flop FF
AND elements G1 to G6 connected to the outputs of 1 to FF64
4, the switching elements T1 to T64 connected to the outputs of the AND elements G1 to G64, and the strobe signal input from the STROBE terminal.
NOT element Ga for inputting signals to 1 to G64 and STR
AND for inputting the logical product of the strobe signal input from the OBE terminal and the clock signal input from the CK1 terminal to each of the flip-flops FF1 to FF64
A D element Gb and an enable register E composed of a 1-bit shift register for controlling the driving state of each of the AND elements G1 to G64 are provided.

The drive control signal ENB stored in the enable register E is transferred by the clock signal input from the CK2 terminal, and is transmitted to the next-stage drive circuit element by ENBOU.
Output via the T terminal. As shown in FIG. 7, when the drive circuit elements are connected in series, the data
The UT terminal is connected to the next-stage DATAIN terminal, and the previous-stage ENBOUT terminal is connected to the next-stage ENDIN terminal.

Next, the operation of the thermal head thus configured will be described. FIG. 9 is a timing chart for driving the thermal head of FIG. 7 in a time-division manner. First, while the drive control signal ENB is kept at the low level, the clock signal CK2 is input to initialize the enable registers E11 to E14 and E21 to E24.
Next, the blocks B11 to B11 of the data for one line
Data corresponding to 14 is input as a print signal DI. At this time, the two strobe signals STB1, STB2
Is a high level, the clock signal CK1 is directly input to the shift registers corresponding to the blocks B11 to B14 and B21 to B24,
The data of 11 to B14 are transferred to the shift registers of blocks B21 to B24. Note that while the print signal DI is being transferred to the shift register of each block, the two strobe signals STB1 and STB2 are at a high level, so that each heating resistor is not driven.

Next, at the same time when the level of the drive control signal ENB is inverted once, the clock signal CK2 generates a one-pulse clock, holds the enable register E11 of the block B11 at a high level, and prints only the block B11. It becomes possible state. Next, when the strobe signal STB1 is inverted to a low level, a current selectively flows through the heating resistor in this portion based on the data stored in the shift register of the block B1, and the block B11 performs a printing operation.

Next, the clock signal CK2 generates a one-pulse clock, transfers the contents stored in the enable register E11 of the block B11 to the enable register E12 of the block B12, and returns the enable register E11 to a low level to enable the enable register E12. Is inverted to a high level. Then, the printing of the block B11 ends,
The printing operation of block B12 starts anew.

Next, when the clock signal CK2 generates a one-pulse clock, the enable register E12 returns to a low level, the enable register E13 inverts to a high level, and printing of the block B12 is completed, and a new block is output. The printing operation of B13 starts.

Next, when the clock signal CK2 generates a one-pulse clock, the enable register E13 returns to the low level, the enable register E14 inverts to the high level, and the printing of the block B13 is completed. Printing operation starts.

In this way, the time division printing of the blocks B11 to B14 is performed, and the block B2
The data of blocks B11 to B24 are input.
Since the input of the clock signal CK1 is blocked to the shift register 21 of B14, the clock signal CK1 is sequentially transferred to the shift registers 21 of the blocks B21 to B24.

Next, the strobe signal STB1 returns to the high level, the strobe signal STB2 inverts to the low level, and the clock signal CK2 generates a one-pulse clock, thereby enabling the enable register E14 of the block B14.
Is stored in the enable register E2 of the block B21.
When the enable register E14 returns to low level and the enable register E21 inverts to high level, the printing operation of the block B21 starts.

Next, when the clock signal CK2 generates a one-pulse clock, the enable register E21 returns to a low level, the enable register E22 is inverted to a high level, and the printing operation of the block B21 is completed. The printing operation of block B22 starts.

Next, when the clock signal CK2 generates a one-pulse clock, the enable register E22 returns to a low level, the enable register E23 inverts to a high level, and the printing operation of the block B22 is completed, and a new block B23 is completed. Printing operation starts.

Next, when the clock signal CK2 generates a one-pulse clock, the enable register E23 returns to a low level, the enable register E24 inverts to a high level, and the printing operation of the block B23 is completed. The printing operation of block B24 starts.

In this way, time-division printing of blocks B21 to B24 is performed, and block B1
The data of the next line corresponding to 1 to B14 is input, but since the input of the clock signal CK1 is blocked to the shift registers 21 of the blocks B21 to B24, they are sequentially transferred to the shift registers 21 of the blocks B11 to B14. Is done.

As described above, data for one line can be printed in a time-division manner for eight periods, and by repeating this operation for each line, a series of images can be recorded.

FIG. 10 is a timing chart when the thermal head of FIG. 7 is driven in a time-division manner. The operation example shown in FIG. 10 controls the clock signal CK2 and the drive control signal ENB so that two of the enable registers E11 to E14 and E11 to E24 hold the high level as compared with the operation example of FIG. Is different.

First, the clock signal CK2 is input while the drive control signal ENB is kept at a low level to initialize the enable registers E11 to E14 and E21 to E24. Is input as a print signal DI, and each shift register 2
Transferred to 1.

Next, the levels of the drive control signal ENB and the clock signal CK2 are inverted twice, and the blocks B11, B
When the 12 enable registers E11 and E12 are held at a high level, the blocks B11 and B12 enter a printable state.

Next, when the strobe signal STB1 is inverted to a low level, the block B11, the block B11 based on the data stored in the shift register of the block B11, B12.
B12 performs a printing operation.

Next, the level of the clock signal CK2 is inverted twice, and the contents stored in the enable registers E11 and E12 of the blocks B11 and B12 are transferred to the enable registers E13 and E14 of the blocks B13 and B14. E14 is inverted to a high level.
Then, printing of blocks B11 and B12 ends, and printing operations of blocks B13 and B14 start anew.

In this way, time-division printing of blocks B11 to B14 is performed, and block B2
The data of blocks B11 to B24 are input.
Since the input of the clock signal CK1 is blocked to the shift register 21 of B14, the clock signal CK1 is sequentially transferred to the shift registers 21 of the blocks B21 to B24.

Next, the strobe signal STB1 returns to the high level, the strobe signal STB2 inverts to the low level, and the clock signal CK2 inverts the level twice, and the enable register E2 of the blocks B21 and B22.
When 1,22 is held at a high level, block B2
1, B22 perform a printing operation.

Next, when the level of the clock signal CK2 is inverted twice, the enable registers E21 and E22 return to a low level, the enable registers E23 and E24 invert to a high level, and the printing operation of the blocks B21 and B22 is completed. , The printing operation of blocks B23 and B24 starts.

In this manner, the time division printing of the blocks B21 to B24 is performed, and the block B1
The data of the next line corresponding to 1 to B14 is input, but since the input of the clock signal CK1 is blocked to the shift registers 21 of the blocks B21 to B24, the data is sequentially transferred to the shift registers 21 of the blocks B11 to B14. Is done.

In this manner, one line of data is
Printing can be performed in a time-division manner for one period, and by repeating this operation for each line, a series of images can be recorded.

FIG. 11 is a timing chart when the thermal head of FIG. 7 is driven in a time-division manner. The operation example illustrated in FIG. 11 is different from the operation example illustrated in FIG. 9 in that control is performed such that all the enable registers E11 to E14 and E21 to E24 are held at a high level.

First, the data corresponding to the blocks B11 to B14 is input as the print signal DI and transferred to each shift register, and at the same time, the drive control signal ENB and the clock signal CK2 are inverted eight times, so that each enable register E11 To E14 and E21 to E24 are all held at a high level. Next, when the strobe signal STB1 is inverted to the low level, the blocks B1 to B4 based on the data stored in the shift registers 21 of the blocks B1 to B4.
B4 performs a printing operation. During this period, blocks B21 to B21
The data of B24 is input, and blocks B11 to B1 are input.
Since the input of the clock signal CK1 is blocked to the shift register 21 of No. 4, the signals are sequentially transferred to the shift registers 21 of the blocks B21 to B24.

Next, when the strobe signal STB1 returns to the high level and the strobe signal STB2 inverts to the low level, the printing of the blocks B11 to B14 ends, and the printing operation of the blocks B21 to B24 starts. Block B
During the printing operation of 21 to B24, blocks B11 to B14
Is input, but the input of the clock signal CK1 is blocked to the shift registers 21 of the blocks B21 to B24, so that the block B11
To the shift register 21 of B14.

As described above, one line of data can be printed in a time-division manner in two periods, and by repeating this operation for each line, a series of images can be recorded.

FIG. 12 is a block diagram showing an electrical configuration of a thermal head according to another embodiment of the present invention. FIG.
The configuration of the thermal head No. 2 is the same as that of FIG. 7, except that enable registers E11 to E14 and enable registers E21 to E24 are connected in parallel, and the drive control signal ENB is supplied to the head enable registers E11 and E2.
1 are different from each other.

The operation of the thermal head will be described. FIG. 13 is a timing chart when the thermal head of FIG. 12 is driven by 8 time divisions. First, while the drive control signal ENB is kept at a low level, the clock signal C
K2 is input to each of the enable registers E11 to E1.
4. After initializing E21 to E24, next, data corresponding to blocks B11 to B14 among the data of one line is input as a print signal DI.

Next, when the level of the drive control signal ENB and the clock signal CK2 are inverted once, the block B11,
The enable registers E11 and E21 of B21 hold the high level, and the blocks B11 and B21 enter a printable state. Next, when the strobe signal STB1 is inverted to a low level, the block B11 performs a printing operation. In addition,
Regarding the block B21, since the strobe signal STB2 remains at the high level, printing is not performed.

Next, the clock signal CK2 generates a one-pulse clock, and the enable registers E11 and E21
Is stored in the next enable registers E12 and E22.
, The block B12 starts printing. Note that, for the block B22, the strobe signal STB
No printing is performed because 2 is at the high level.

Similarly, when the clock signal CK2 generates a one-pulse clock, the block B13 performs a printing operation, and then the clock signal CK2 generates a one-pulse clock, and the block B14 performs a printing operation.

In this way, the time division printing of the blocks B11 to B14 is performed, and the block B2
1 to B24 are input, and blocks B21 to B2
4 is transferred to the shift register 21.

The same time-sharing operation is performed for the blocks B21 to B24, so that data for one line can be printed in a time-sharing manner for eight periods.

FIG. 14 is a timing chart when the thermal head of FIG. 12 is driven in a time-division manner. FIG.
In the operation example shown in FIG. 13, the clock signal CK2 and the drive control signal ENB are controlled so that two of the enable registers E11 to E14 and E21 to E24 hold the high level as compared with the operation example of FIG. This is different from the operation example shown in FIG.

First, after inputting the clock signal CK2 and initializing each of the enable registers E11 to E14 and E21 to E24, next, data corresponding to the blocks B11 to B14 is input as the print signal DI and shifted. The data is transferred to the register 21.

Next, when the levels of the drive control signal ENB and the clock signal CK2 are inverted twice and the enable registers E11, E12, E21 and E22 hold the high level, the blocks B11, B12, B21 and B22 are ready for printing. Becomes Next, when the strobe signal STB1 is inverted to a low level, the blocks B11 and B12 perform a printing operation. Note that the printing operation is not performed on the blocks B21 and B22 because the strobe signal STB2 remains at the high level.

Next, the level of the clock signal CK2 is inverted twice, and the enable registers E11, E12, E21,
The contents of E22 are stored in the next enable registers E13, E
When transferred to E14, E23 and E24, blocks B13 and B14 perform a printing operation. Block B2
3 and B24 do not perform a printing operation because the strobe signal STB2 is at a high level.

In this way, the time-division printing of the blocks B11 to B14 is performed, and the block B2
1 to B24 are input.
By performing the same time-division driving for B24 to B24,
Data for one line can be printed in a time-division manner in four periods.

FIG. 15 is a block diagram showing another example of the electrical configuration of the thermal head. In this thermal head, one end of a heating resistor 24 is commonly connected to a common electrode 30, and a switching element 26 such as a power transistor is connected to the other end of each heating resistor 24 via an individual electrode 25. Connected individually. The output terminal of each switching element 26 is commonly connected to ground wiring 2
7, and a control signal input terminal of each switching element 26 is connected to an AND element 28 as a gate element.

Each heating resistor 24, switching element 26
And the AND element 28 are connected to the blocks B1-1 and B1.
-2 and a block B2-1, B2
-2, which are roughly divided into two blocks of a B2 block composed of -2, and a total of four blocks B1-1 and B2-
1, B1-2, B2-2, and the block B
1-1 AND element 28 of block B2-1 is connected to shift register 21a-1, and AND element 28 of block B2-1 is connected to shift register 21b-1.
The ND element 28 is connected to the shift register 21a-2,
The AND element 28 of the block B2-2 is the shift register 2
1b-2. Each shift register 21a-
1, 21b-1, 21, 21a-2, and 21b-2 are input to the shift register 21a-2 after the print signal DI is transferred by the shift register 21a-1, and further the same print signal D
They are connected so that I is input to the shift register 21b-2 after being transferred by the shift register 21b-1.

The strobe signal STB1 for determining the drive timing of the heating resistor 24 of the block B1-1 and the heating resistor 24 of the block B1-2 is supplied to the AND element 28 and the block B1- of the block B1-1 via the NOT element 22a. The second AND element 28 is wired so as to be input. The strobe signal STB2 for determining the drive timing of the heating resistor 24 of the block B2-1 and the heating resistor of the block B2-2 is supplied to the AND element 28 and the block B of the block B2-1 via the NOT element 22b.
It is wired so as to be inputted to the AND element 28 of 2-2.

The clock signal CK1 for determining the transfer timing of the print signal DI is supplied to the AND elements 29a and 29b.
, And the logical product of the strobe signal STB1 and the clock signal CK1 is calculated by the shift register 21a-1,
21a-2 and the strobe signal ST
The logical product of B2 and the clock signal CK1 is input to the shift registers 21b-1, 21b-2. The switching element 26, the AND element 28, the shift register 21a
-1, 21b-1, 21, 21a-2, 21b-2, etc. are formed in the drive circuit element 34 by integrated circuit technology.

The control device 23 for controlling the thermal head is provided with a memory 33.
Print data for each line is stored. For example, the first line print data LD1 is divided into four data D1.
1f, D11s, D12f, and D12s, and the second line print data LD2 is divided into four data D21
f, D21s, D22f, and D22s, and print data to which the same reference numerals are given below are stored in the memory 33.

FIG. 16 is a timing chart showing the operation of the thermal head of FIG. First, the print signal DI
Is low level, when the clock signal CK1 generates a pulse for one block, the shift register 21a-
Low-level data is all transferred to 1, 21b-1.

Next, one line of data D12s, D12f, D11s, D11f is continuously transmitted as the print signal DI, but the data D11f of the block B1-1 is transmitted.
When the clock signal CK1 generates a pulse for one block only during the period when the clock signal is transmitted, the shift register 21a-
The data D11f is transferred to the shift registers 21a and 21b-1, and the low-level data stored in the shift registers 21a-1 and 21b-1 is transferred to the shift registers 21a-2 and 21b-2.

Next, when the strobe signal STB1 is inverted from the high level to the low level, the blocks B1-1 and B-1
The high level is input to the AND element 1-2 of block 1-2, and the blocks B1-1 and B1-2 are in a printable state, and the heating resistance of the block B1-1 is determined based on the data D11f stored in the shift register 21a-1. A current selectively flows through the body 24 to perform printing. Also, the shift register 21a-2
, The low-level data are all stored, and the printing of the block B1-2 is not substantially performed. Thus, the block B1-1 can print the data D11f.

Since the AND element 29a always outputs the low level during the period when the strobe signal STB1 is at the low level, the clock signal CK1 is prevented from being input to the shift registers 21a-1, 21a-2. ing. Therefore, the data does not change even when the blocks B1-1 and B1-2 are in a printable state. During this period, first, the clock signal C is set while the print signal DI is at the low level.
When K1 generates a pulse for one block, the clock signal CK1 is input to the shift registers 21b-1 and 21b-2, and all low-level data is transferred. next,
As the print signal DI, one line of data D12s, D
12f, D11s, and D11f are continuously transmitted,
Only when the data D11s of the block B2-1 is being transmitted, when the clock signal CK1 generates a pulse for one clock, the data D11s is stored in the shift register 21b-1.
Is transferred, and the low-level data stored in the shift register 21b-1 is transferred to the shift register 21b-2.

Next, when the strobe signal STB1 returns to the high level and the strobe signal STB2 inverts to the low level, the AND elements 28 of the blocks B2-1 and B2-2 are turned on.
Is inputted to the block B2-1, the blocks B2-1 and B2-2 become printable, and the shift register 21b
Based on the data D11s input to −1, a current selectively flows through the heating resistor 24 of the block B2-1 to perform printing. Further, since all the low-level data is stored in the shift register 21b-2, the block B2-
No. 2 is not substantially printed. Thus, block B2
-1 data D11s can be printed.

Since the AND element 29b always outputs the low level during the period when the strobe signal STB2 is at the low level, the clock signal CK1 is prevented from being input to the shift registers 21b-1, 21b-2. ing. Therefore, the data does not change even if the blocks B2-1 and B2-2 are in the printable state. Also, during this period, the data D12 for one line is used as the print signal DI.
s, D12f, D11s, and D11f are continuously transmitted. When the clock signal CK1 generates a pulse for one block only during the period when the data D12f of the block B1-2 is being transmitted, the shift register 21a-1 outputs the pulse to the shift register 21a-1. Data D
12f is transferred.

Next, when the clock signal CK1 generates a pulse for one clock while the printing signal DI is at the low level, all the low-level data is transferred to the shift register 21a-1 and the shift register 21a-2
Is transferred to the data D12f stored in the shift register 21a-1.

Next, when the strobe signal STB2 returns to the high level and the strobe signal STB1 inverts to the low level, the AND elements 28 of the blocks B1-1 and B1-2 are turned on.
Are input to the blocks B1-1 and B1-2.
Are in a printable state, and based on the data D12f stored in the shift register 21a-2, the block B1-2
The current flows selectively to the heating resistor 24, and printing is performed.
Further, since all the low-level data is stored in the shift register 21a-1, printing of the block B1-1 is not substantially performed. Thus, the block B1-2 can print the data D12f.

During the period when the strobe signal STB1 is at the low level, the clock signal CK1 is prevented from being input to the shift registers 21a-1, 21a-2. During this period, one line of data D12s, D12f, D11s, and D11f are continuously transmitted as the print signal DI, but the data D1 of the block B2-2 is transmitted.
Only during the period in which 2s is sent, the clock signal CK1 becomes 1
When pulses for blocks are generated, the shift register 21
Data D12s is transferred to b-1.

Next, when the clock signal CK1 generates a pulse for one block while the printing signal DI is at the low level, all the low-level data is transferred to the shift register 21b-1 and the shift register 21b-2. Is transferred to the data D12s stored in the shift register 21b-1.

Next, when the strobe signal STB1 returns to the high level and the strobe signal STB2 inverts to the low level, the AND elements 28 of the clocks B2-1 and B2-2 are output.
Is input to the blocks B2-1 and B2-2.
Becomes a printable state, and based on the data D12s stored in the shift register 21b-2, the block B2-2
A current is selectively passed through the heating resistor 24 to perform printing.
Further, since all the low-level data is stored in the shift register 21b-1, printing of the block B2-1 is not substantially performed. Thus, the block B2-2 can print the data D12s.

As described above, the print data LD1 of the first line includes four blocks B1-1, B2-1, and B1-
Printing can be performed in a time-division manner in four periods for each of B2-2 and B2-2. The print data LD2 of the second line and subsequent lines can be printed by the same time-division driving as the first line.

FIG. 17 is a schematic diagram showing a print area on a recording medium when printing is performed at the operation timing shown in FIG. Since the recording medium is conveyed at a constant speed and printed in a time-division manner for four periods, each line is further divided into four small lines. In the first small line, a print area corresponding to the block B1-1 is printed, and the other areas are turned off. Similarly, the block B2-1 is printed in the next small line, the block B1-2 is printed in the next small line, and the block B2-2 is printed in the last small line. Hereinafter, a similar print area is formed in the second line and the subsequent lines.

FIG. 18 is a timing chart showing another operation example of the thermal head of FIG. First, one line of data D12s, D12f,
D11s and D11f are continuously transmitted, and the block B1
Only during the period when the data D12f of -2 and the data D11f of the block B1-1 are being transmitted,
When the clock signal CK1 generates one block of pulses, the data D12 is stored in the shift register 21a-2.
f is transferred, and the data D1 is stored in the shift register 21a-1.
1f is transferred. During this period, the strobe signal S
Since TB2 is at low level, the shift register 21b
No data transfer to -1, 22b-2 is performed.

Next, the strobe signal STB1 is inverted from the high level to the low level, and the strobe signal STB1 is inverted.
When TB2 returns to the high level, blocks B1-1 and B1
-2 becomes a printable state, and the shift register 21a-1
Based on the data D11f stored in the block B1-
1 performs printing, and a block B1-2 based on the data D12f stored in the shift register 21a-2.
Performs printing.

While the strobe signal STB1 is at the low level, the clock signal CK1 is prevented from being input to the shift registers 21a-1 and 21a-2, so that the blocks B1-1 and B1- Even if 2 is in a printable state, the data does not change. Also, during this period, the data D12 for one line is used as the print signal DI.
s, D12f, D11s, and D11f are continuously transmitted, and the clock signal CK1 is one block only during the period during which the data D12s of the block B2-2 is transmitted and the period during which the data D11s of the block B2-1 is transmitted. When a minute pulse is generated, the shift register 21b-
2, the data D12s is transferred to the shift register 21b.
The data D11s is transferred to -1. Since the strobe signal STB1 is at the low level during this period, data transfer to the shift registers 21a-1 and 21a-2 is not performed.

Next, when the strobe signal STB1 returns to the high level and the strobe signal STB2 inverts to the low level, the blocks B2-1 and B2-2 enter a printable state and are stored in the shift register 21b-1. The block B2-1 performs printing based on the data D11s, and the block B2-2 performs printing based on the data D12s stored in the shift register 21b-2. Note that during the period when the strobe signal STB2 is at the low level, the clock signal CK1 is
Since the input to −1 and 21b-2 is prevented, the data does not change even when the blocks B2-1 and B2-2 are in a printable state.

Thus, the data for one line is 4
Blocks B1-1, B2-1, B1-2, B2-2
Each time, printing can be performed in a time-division manner into two periods.

FIG. 19 is a circuit diagram showing an electrical configuration of a thermal head according to another embodiment of the present invention. This thermal head includes a number of heating resistors R1 to R2048,
In FIG. 19, 64 heating resistors are connected to one driving circuit 50, and further, 512 heating resistors and 8 driving circuits are connected to one block in FIG. Four blocks B1-
1, B2-1, B1-2, and B2-2.
The heating resistor is divided into these four blocks and driven in a time-division manner.

Further, as shown in FIG. 20, the heating resistor R1
To R2048 are the four blocks B1-1, B2-
The positions of the heating resistors are shifted by a distance t in a direction M intersecting with the arrangement direction of the heating resistors for each of B1-2 and B2-2. This distance t is a value obtained by dividing the transport distance of the recording medium in the printing cycle of each heating resistor by the above-mentioned number of blocks 4 for time-division driving.

FIG. 21 is a circuit diagram showing an example of drive circuit 50 shown in FIG. The drive circuit 50 converts the print data DI consisting of serial data into parallel data for each predetermined number of bits by transferring the print data DI in synchronization with an external clock signal CLK, and outputs the shift registers SR1 to SRn. A plurality of latch circuits L1 to Ln for storing the outputs of the shift registers SR1 to SRn in response to a latch signal LAT from the memory, and a plurality of latch circuits L1 to Ln for opening and closing the outputs of the latches L1 to Ln in response to an external strobe signal STB1 and print control signal BEO Gate element G1
To Gn, and a plurality of switching elements T1 to Tn for controlling the current flowing through the heating resistors R1 to Rn by the outputs of the gate elements G1 to Gn.

One end of a number of heating resistors R1 to Rn formed on the thermal head is connected to each of the switching elements T1 to Tn.
n, the other ends of the heating resistors R1 to Rn are commonly connected to the output side VH of the external power supply 51, and the source sides of the switching elements T1 to Tn are commonly connected. External power supply 5 to terminal GND2
1 is connected to the ground side.

FIG. 22 is a time chart when the thermal head shown in FIG. 19 is driven. The operation of the thermal head will be described below based on this time chart. In the time chart, instead of processing the print data D to be printed in advance as means for sequentially inputting print data corresponding to the heating resistors of the blocks B1-1, B2-1, B1-2, and B2-2 to be selected. , Serial data corresponding to the order of the heating resistors is input.

Next, the required print data to be printed corresponding to each block is selected from the continuous print data D and stored in the shift register in accordance with the clock signals CK1 to CK4. After the first print data D is output, print data corresponding to the heating resistor of the block B1-1 is stored in the shift registers SR1 to SRn by the clock signal CK1. Next, the latch signal LAT is inverted for a certain period of time, and data outputs of the shift registers SR1 to SRn are stored in the latch circuits L1 to Ln. Next, the print control signal BE
O, when the strobe signal STB is output at a low level, the block B1- stored in the latch circuits L1 to Ln is output.
The gate elements G1 to Gn are opened based on the printing data corresponding to one heating resistor, and the switching elements T1 to Gn are opened.
Tn becomes conductive. Thereby, the block B1-
An electric current selectively flows through the one heating resistor to generate heat, and printing is performed.

Similarly, blocks B2-1 and B1-
Printing by the heating resistors 2 and B2-2 is sequentially performed.

FIG. 23 is a time chart of clock signals CK1 to CK4 shown in FIG. Print data D
Among them, the print data DI is print data corresponding to the heating resistor of the block B1-1, the print data D2 is print data corresponding to the heating resistor of the block B2-1, and the print data D3 is the block B1. The print data D4 is print data corresponding to the block B2-2, and the print data D4 is print data corresponding to the block B2-2.

When the clock signal CK1 is input, the print data of the data DI is stored in the shift register corresponding to the block B1-1, and the low-level print data is stored in the shift registers of the other blocks. Similarly, by inputting the clock signal CK2, the print data of the data D2 is stored in the shift register corresponding to the block B2-1, and the low-level print data is stored in the shift registers of the other blocks. Is done. By inputting the clock signal CK3, the print data of the data D3 is stored in the shift register corresponding to the block B1-2, and the low-level print data is stored in the shift registers of the other blocks. By inputting the clock signal CK4, the print data of the data D4 is stored in the shift register corresponding to the block B2-2, and the low-level print data is stored in the other shift registers.

The case where the signals of the timing charts shown in FIGS. 22 and 23 are applied to the thermal heads arranged as shown in FIG. 20 using the drive circuits shown in FIGS. 19 and 21 will be described below. I do. In this case, first, the print data DI corresponding to the heating resistor of the block B1-1 is used.
And the heating resistor is driven. Next, the recording medium is conveyed by the distance t in the direction M, the print data D2 corresponding to the heating resistor of the block B2-1 is given, and the heating resistor is driven. Next, the recording medium is conveyed by the distance t in the direction M, the print data D3 corresponding to the heating resistor of the block B1-2 is given, and the heating resistor is driven.
Next, the recording medium is transported for a distance t in the direction M, and the block B2
The print data D4 corresponding to the -2 heating resistor is provided, and the heating resistor is driven.

Hereinafter, by repeating the above operation, the print image shown in FIG. 24 can be obtained on the recording medium. In this manner, the print dots of each line are aligned on a straight line, and a high-quality print image without distortion can be obtained.

Next, still another example of the thermal head will be described below. The electrical configuration of this thermal head is shown in FIG. 15, and the thermal head operates based on the timing chart shown in FIG. FIG. 20 shows the arrangement of the heating resistors of the thermal head.

As shown in FIG. 15, in the thermal head, one end of each heating resistor 24 is commonly connected to a common electrode 30, and the other end of each heating resistor 24 is connected via an individual electrode 25. For example, switching elements 26 such as power transistors are individually connected. The output terminal of each switching element 26 is commonly connected to ground wiring 2
7, and a control signal input terminal of each switching element 26 is connected to an AND element 28 as a gate element.

Each heating resistor 24, switching element 26
And the AND element 28 are connected to the blocks B1-1 and B1.
-2 and a block B2-1, B2
-2, which are roughly divided into two blocks of a B2 block composed of-
1, B1-2, B2-2, and the block B
1-1 AND element 28 of block B2-1 is connected to shift register 21a-1, and AND element 28 of block B2-1 is connected to shift register 21b-1.
The ND element 28 is connected to the shift register 21a-2,
The AND element 28 of the block B2-2 is the shift register 2
1b-2. Each shift register 21a-
1, 21b-1, 21, 21a-2, and 21b-2 are input to the shift register 21a-2 after the print signal DI is transferred by the shift register 21a-1, and further the same print signal D
They are connected so that I is input to the shift register 21b-2 after being transferred by the shift register 21b-1.

The strobe signal STB1 for determining the drive timing of the heating resistor 24 of the block B1-1 and the heating resistor 24 of the block B1-2 is supplied to the AND element 28 and the block B1- of the block B1-1 via the NOT element 22a. The second AND element 28 is wired so as to be input. The strobe signal STB2 for determining the drive timing of the heating resistor 24 of the block B2-1 and the heating resistor of the block B2-2 is supplied to the AND element 28 and the block B of the block B2-1 via the NOT element 22b.
It is wired so as to be inputted to the AND element 28 of 2-2.

The clock signal CK1 for determining the transfer timing of the print signal DI is supplied to the AND elements 29a and 29b.
, And the logical product of the strobe signal STB1 and the clock signal CK1 is calculated by the shift register 21a-1,
21a-2 and the strobe signal ST
The logical product of B2 and the clock signal CK1 is input to the shift registers 21b-1, 21b-2. The switching element 26, the AND element 28, the shift register 21a
-1, 21b-1, 21, 21a-2, 21b-2, etc. are formed in the drive circuit element 34 by integrated circuit technology.

The control device 23 for controlling the thermal head is provided with a memory 33.
Print data for each line is stored. For example, the first line print data LD1 is divided into four data D1.
1f, D11s, D12f, and D12s, and the second line print data LD2 is divided into four data D21
f, D21s, D22f, and D22s, and print data to which the same reference numerals are given below are stored in the memory 33.

FIG. 16 is a timing chart showing the operation of the thermal head of FIG. First, the print signal DI
Is low level, when the clock signal CK1 generates a pulse for one block, the shift register 21a-
Low-level data is all transferred to 1, 21b-1.

Next, one line of data D12s, D12f, D11s, D11f is continuously transmitted as the print signal DI, but the data D11f of the block B1-1 is continuously transmitted.
When the clock signal CK1 generates a pulse for one block only during the period when the clock signal is transmitted, the shift register 21a-
The data D11f is transferred to the shift registers 21a and 21b-1, and the low-level data stored in the shift registers 21a-1 and 21b-1 is transferred to the shift registers 21a-2 and 21b-2.

Next, when the strobe signal STB1 is inverted from the high level to the low level, the blocks B1-1 and B-1
The high level is input to the AND element 1-2 of block 1-2, and the blocks B1-1 and B1-2 are in a printable state, and the heating resistance of the block B1-1 is determined based on the data D11f stored in the shift register 21a-1. A current selectively flows through the body 24 to perform printing. Also, the shift register 21a-2
, The low-level data are all stored, and the printing of the block B1-2 is not substantially performed. Thus, the block B1-1 can print the data D11f.

Hereinafter, the data D11s, data 12f, and data 12s can be sequentially printed by inputting the print data DI, the clock signal CK1, and the strobe signals STB1 and STB2 based on the time chart as described above.

As described above, the print data LD1 of the first line includes four blocks B1-1, B2-1, and B1-
Printing can be performed in a time-division manner in four periods for each of B2-2 and B2-2. The print data LD2 of the second line and subsequent lines can be printed by the same time-division driving as the first line.

Therefore, when printing is performed at the operation timing shown in FIG. 16, the print image shown in FIG. 24 can be obtained on the recording medium. As described above, the print dots of each line are aligned on a straight line, and a high-quality print image without distortion can be obtained.

Next, still another example of the thermal head will be described below. The electrical configuration of this thermal head is shown in FIG. 15, and the thermal head operates based on the timing chart shown in FIG. The arrangement of the heating resistors of this thermal head is similar to the arrangement of the heating resistors shown in FIG. 21, and the heating resistors of blocks B1-1 and B1-2 and the blocks B2-1 and B2-2. Are shifted by a distance t in the M direction.

The timing chart of FIG. 18 will be described below. First, one line of data D12s, D12f, D11s, and D11f are continuously transmitted as the print signal DI, and a period during which the data D12f of the block B1-2 is transmitted and the data D11f of the block B1-1.
When the clock signal CK1 generates one block of pulses only during the period during which the clock signal is transmitted, the data D12f is transferred to the shift register 21a-2, and the data D11f is transferred to the shift register 21a-1. Since the strobe signal STB2 is at the low level during this period, data transfer to the shift registers 21b-1 and 22b-2 is not performed.

Next, the strobe signal STB1 is inverted from the high level to the low level, and the strobe signal S
When TB2 returns to the high level, blocks B1-1 and B1
-2 becomes a printable state, and the shift register 21a-1
Based on the data D11f stored in the block B1-
1 performs printing, and a block B1-2 based on the data D12f stored in the shift register 21a-2.
Performs printing.

Hereinafter, by inputting the print data DI, the clock signal CK1, and the strobe signals STB1 and STB2 based on the time chart as described above, the block B2-1 performs printing based on the data D11s. , Based on the data 11s, the block B2-
2 performs printing. Thus, one line of data is divided into four blocks B1-1, B2-1, B1-2, and B2.
Every two prints can be time-divided into two periods.

Therefore, when printing is performed at the operation timings shown in FIG. 18, the print image shown in FIG. 24 can be obtained on the recording medium. In this manner, a high-quality printed image without distortion in which the printed dots of each line are aligned on a straight line can be obtained.

[0128]

As described above in detail, according to the present invention, since the latch circuit can be omitted, the circuit configuration of the thermal head can be simplified, downsized, and the printing speed can be increased. Further, since the timing of the time-division driving can be set more finely, it is possible to more accurately compensate for print density fluctuation. Therefore, the printing time can be reduced and the printing quality can be improved.

Further, according to the present invention, it is possible to form an undistorted print image in which print dots are aligned on a recording medium. As a result, it is possible to improve the quality of the image printed by the thermal head.

[Brief description of the drawings]

FIG. 1A is a block diagram illustrating an electrical configuration of a thermal head including a clock gate element, and FIG. 1B is a schematic plan view illustrating an appearance of the thermal head.

FIG. 2 is a block diagram showing an electrical configuration of drive circuit elements IC0 to IC31 shown in FIG.

FIG. 3 is an overall configuration diagram of the thermal head of FIG. 1, shown for easy comparison with the conventional thermal head shown in FIG.

FIG. 4 is a timing chart showing the operation of the thermal head of FIGS. 1 and 3.

FIG. 5 is a timing chart showing another operation example of the thermal head of FIGS. 1 and 3;

FIG. 6 is a timing chart showing another operation example of the thermal head shown in FIGS. 1 and 3;

FIG. 7 is a block diagram showing an electrical configuration of a thermal head according to an embodiment of the present invention.

8 is a block diagram showing an electrical configuration of a drive circuit element for driving the 64 heating resistors shown in FIG. 7 as one block.

FIG. 9 is a timing chart when the thermal head of FIG. 7 is driven in an eight-time division manner.

FIG. 10 is a timing chart when the thermal head of FIG. 7 is driven in a four-time division manner.

11 is a timing chart when the thermal head of FIG. 7 is driven in a time-division manner.

FIG. 12 is a block diagram showing an electrical configuration of a thermal head according to another embodiment of the present invention.

FIG. 13 is a timing chart when the thermal head of FIG. 12 is driven in an eight-time division manner.

FIG. 14 is a timing chart when the thermal head of FIG. 12 is driven in a four-time-division manner.

FIG. 15 is a block diagram showing another example of the electrical configuration of the thermal head.

FIG. 16 is a timing chart showing the operation of the thermal head of FIG.

FIG. 17 is a schematic diagram showing a printing area on a recording medium when printing is performed at the operation timing shown in FIG. 16;

FIG. 18 is a timing chart showing another operation example of the thermal head of FIG.

FIG. 19 is a block diagram showing an electrical configuration of a thermal head according to still another embodiment of the present invention.

20 is a plan view showing an arrangement of heat generating resistors of the thermal head shown in FIG.

21 is a block diagram showing an electrical configuration of a drive circuit element 50 of the thermal head shown in FIG.

FIG. 22 is a timing chart showing the operation of the thermal head shown in FIG.

FIG. 23 shows clock signals CK1 to CK shown in FIG. 22;
4 is a timing chart of FIG.

FIG. 24 is a schematic view showing a print area on a recording medium when the thermal head shown in FIG. 19 is operated.

FIG. 25 is a block diagram of a typical conventional thermal head 1.

FIG. 26 is a plan view showing an arrangement of heat generating resistors of the thermal head shown in FIG. 25;

FIG. 27 is a timing chart illustrating the operation of the thermal head 1 of FIG.

[Explanation of symbols]

20 Thermal Head 21, 21a-1, 21b-1, 21, 21a-2, 21b-
2 shift register 22, 22a, 22b NOT element 23 controller 24 heating resistor 25 individual electrode 26 switching element 27 ground wiring 28 AND element 29, 29a, 29b AND element 30 common wiring 33 memory 34, 50 drive circuit element E11 to E14 , E21 to E24 enable register

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-64-72864 (JP, A) JP-A-62-133858 (JP, A) JP-A-2-215549 (JP, A) JP-A Sho 56- 106878 (JP, A) Actually open 1988-201734 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) B41J 2/355

Claims (2)

(57) [Claims] 1. A drive including a plurality of heating elements, a plurality of switching elements individually connected to each heating element, a gate element individually connected to each switching element, and a shift register connected to each gate element. A plurality of heating elements are divided into a plurality of blocks, and a gate element of each block is provided in a plurality of shift registers having the same number of bits as the number of heating elements of each block. The same number of strobe signals as the number of sections of the block are input to the gate elements corresponding to each block, and when the printing of each block is activated, the clock input to the shift register corresponding to the block is prevented. Clock gate elements are provided for each block, and each gate element further includes a plurality of small blocks. A gate control element for controlling the driving state of the gate element corresponding to each small block is provided for each small block, and the gate control element is provided for activating the small block. A thermal head, which is connected in series so that gate control data can be transferred. 2. The thermal head according to claim 1, wherein positions of the plurality of heating elements are shifted in a direction intersecting an arrangement direction of the heating resistors for each of the small blocks.