JP3278946B2 - Digital video signal transmission system and digital video signal transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal transmission system for transmitting digital video signals and a digital video signal transmission apparatus.

[0002]

2. Description of the Related Art When a digital video signal is transmitted, or a digital video signal is recorded on a magnetic tape, a disk, or the like, usually, a sample having a short distance on a television screen (hereinafter simply referred to as a screen) at the time of transmission or recording. Are transmitted or recorded by changing the order of the samples so that the distance becomes longer on the transmission path or the recording medium.
A method of changing the order of the samples of the digital video signal is called shuffling.

When a digital video signal is transmitted or recorded by shuffling, even if a sample is lost due to a transmission path error on the receiving side or a partial defect of the recording medium during reproduction, the screen of the sample is lost. The surrounding samples above are transmitted or recorded on a transmission path or a recording medium at a long distance, so that they are normally received or reproduced. Therefore, the missing sample can be interpolated by calculation using the surrounding samples on the screen having high correlation with the missing sample. Interpolating a missing sample with another sample is called retouching.

As an example of the conventional shuffling of a digital video signal, for example, as the first document, Electric
al System Design for the SMPTE D-1 DTTR (SMPTE Jour
nal, December, 1986).
type D-1 cassete-helical data and control records
(SMPTE 227M SMPTE Journal, March, 1986).

[0005] A digital VTR for recording a component digital video signal, a so-called D-1 shuffling system, described in the above-mentioned documents will be briefly described. FIG. 10 shows a part of the signal processing on the recording side of D-1. First, the component digital video signal specified by the CCIR 601 is decoded by the decoder 1 into Y, C
It is decoded into b and Cr signals. The number of samples in one horizontal line is as follows: Y = 720 samples, Cb / Cr = 360
Here is a sample. The decoded Y, Cb, Cr signals are divided into four sectors by the inter-sector shuffling means 2. That is, within one sector, the number of samples in one line is 180 samples for Y and 90 samples for Cb and Cr, respectively, for a total of 360 samples. Less than,
The processing in each sector will be described. Index within one horizontal line in each sector, and the luminance signal is Y
, Y179, and the color difference signals are Cb0, Cb
b2, ..., Cb178, Cr0, Cr2, ...,
Cr178. Next, the luminance signal data is divided into two groups, an even numbered group and an odd numbered index, and a total of four groups of two luminance signal groups and two color difference signal groups each having 90 elements. That is, (Y0, Y2,..., Y178), (Y1, Y
,..., Y179), (Cb0, Cb2,.
Cb178), (Cr0, Cr2, ..., Cr17)
Consider 4 groups of 8). Further, each group is divided into three in the order of the index size, that is, divided into three groups of the first half, the middle, and the second half in the line. For example, (Y
The group of (0, Y2,..., Y178) is (Y0,
Y2,..., Y58), (Y60, Y62,.
Y118), (Y120, Y122,..., Y17)
8) It is divided into three groups. As a result, one line is divided into a total of 12 groups each having 30 elements. Then, a 2-byte error correction check byte is added to each group in the outer encoder 3. That is, two bytes of error correction check bytes are added to the 30 data by the outer encoder to form a group having a total of 32 elements. Hereinafter, each group having the 32 elements is referred to as an outer code block. In D-1, one field is divided into, for example, 5 segments each including 50 lines in the NTSC system, and divided into 6 segments each including 50 lines in the PAL system, and recorded. As described above, in one segment, 50 lines and 12 outer code blocks exist in one line. Therefore, in each sector, 12 * 50 = 600 outer code blocks exist in one segment. Also, since the outer code block length is 32 bytes, 60 in one sector in one segment.
There are 0 * 32 data. The intra-sector shuffling means 4 has a buffer memory having a conceptually two-dimensional address space as shown in FIG. 11 and an address generating means, and performs intra-sector shuffling.

Next, the concept of intra-sector shuffling of D-1 will be briefly described. In the vertical direction of the 600 * 32 array of the buffer memory shown in FIG. 11, outer code blocks are stored in line order from the left. And
The outer code block is divided into four groups, and a total of 1
There are 50 outer code block groups. That is, FIG.
Consider a 150 * 32 array as shown in FIG. And
In a 150 * 32 array, the order of the columns is randomly changed. After that, the order of the rows is changed at random within each column, but the order is changed with an offset between the columns. As a result, in the sector, data is shuffled almost randomly in the row direction and the column direction. Thereafter, data is read from the buffer memory in the horizontal direction. Reading is performed in units of 60-byte blocks. Hereinafter, the block at the time of reading is referred to as an inner code block. The inner code block read from the buffer memory is added with 4 check bytes per 60 bytes of data in the inner encoder 5. Thereafter, SYNC, ID, etc. are added and recorded on the tape.

[0007]

However, in the above-mentioned method, there is a problem that data of a line adjacent to the same inner code block enters. For example, FIG.
In the 150 * 32 array shown in FIG. 2, the column index before shuffling is represented by Igrp (0 ≦ Igrp ≦ 14
9), the column index after shuffling is set to Jgrp (0 ≦
Jgrp ≦ 149), and FIG. 13 shows an example of the relationship between Igrp and Jgrp in one inner code block. In FIG. 13, Line indicates a line number at which data is actually sampled. According to FIG. 13, for example, mutually adjacent lines of Line 0 and Line 1 are included in the same inner code block. If adjacent lines enter the same inner code block, if an error occurs in the inner code block, the data of the adjacent lines will be erroneous at the same time on the screen, and the error positions on the screen will be concentrated without being dispersed. There was a problem that it would. In the case of a VTR, it is ideal that data that is close on a tape is shuffled so as to be arranged as far away from the screen as possible. Since data at a short distance is recorded at a short distance on the tape, if a long burst error occurs in the track direction of the tape, the error is not dispersed on the screen, and as a result, the wrong pixel is normally detected. It has been difficult to modify using the reproduced peripheral pixels. SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital video signal transmission system and a digital video signal transmission apparatus capable of dispersing data of adjacent lines into different inner code blocks.

[0008]

In order to achieve this object, a digital video signal transmission system according to the present invention uses the same line.
Outer code block consisting of digital video signals
In a digital video signal transmission system for converting and storing an address added to data of a network and reading and transmitting the stored digital video signal, the address is converted.
When that, for samples of all the digital video signals, adjacent m lines (m is an integer m ≧ 10) distributed in the inner code block different samples, the inner code block single
The data is read and transmitted at the order. The digital video signal transmission apparatus of the present invention, a buffer memory capable of storing samples of the digital video signal, on the same line
An outer code block composed of the digital video signal
Address conversion means for converting an address added to the buffer into an address of the buffer memory; and an inner code block for converting the digital video data stored in the buffer memory into an inner code block.
And means for reading transmitted in units, address translation Hand
The stage addresses so that adjacent m lines of samples (where m is an integer m ≧ 10 ) are distributed to different inner code blocks.
Is to be converted .

[0009]

According to the present invention, when shuffling an outer code block, data of adjacent lines is shrunk so that data of adjacent m lines ( m.gtoreq.10 ) fall in different inner code blocks. As a result, even when a long burst error in the track direction occurs on the tape, the error can be dispersed in the vertical direction on the screen.

[0010]

Embodiments of a digital video signal transmission system and a digital video signal transmission apparatus according to the present invention will be described below with reference to the drawings.

In an embodiment of the present invention, a helical scan digital VTR for recording a digital video signal is used.
An example will be described. In the present embodiment, one field is divided into one or a plurality of channels and recorded on a tape. Then, the LNUM of the vertical RNUM and the horizontal LNUM as shown in FIG.
* Consider a two-dimensional array of RNUMs. The sampled video signal is divided into one or more channels,
The data is written in an array as shown in FIG. 1 in the vertical direction and read in the horizontal direction. This embodiment will be described below with reference to FIG.

After the sampled data in one line is divided into one or a plurality of channels, the order of samples is randomly changed within one line for each channel. (Intra-line shuffling) Then, after the outer code check byte is added, L as shown in FIG.
Data is written in the NUM * RNUM array in the vertical direction. At this time, the address of the outer code block before being written to the array is L, and the address at the time of actually writing to the array is A.
Defined as DRS. That is, L corresponds to the line number of the sampled data, and ADRS corresponds to the horizontal address in the LNUM * RNUM array.

ADRS = (A * L) MOD LNUM (1) (A, L, and LNUM are integers A and LNUM are relatively prime)
Then, the address in the horizontal direction for writing the outer code block is determined according to the equation (1). Here, MOD means modulo calculation. The numbers in FIG. 1 indicate the line numbers at the time of sampling. That is, for example, the line 0 is converted to the address 0, the line 1 is converted to the address A, and the line 2 is converted to the address (2 * A) and written in the vertical direction on the array. Next, data written in the vertical direction in the array shown in FIG. 1 is read out in the horizontal direction, and an inner code check byte is added to a fixed number of data to form an inner code block.

In the present invention, by setting the constant A to an appropriate value in the equation (1), the adjacent m lines (m ≧ 1)
0 ) is not included in the same inner code block, and further, by appropriately selecting A, data of an adjacent line is dispersed as much as possible in the array. As a result, even if a long burst error occurs in the track direction on the tape, the data of the adjacent line is recorded at a position distant on the tape, so that when reproduced, the error is dispersed in the vertical direction on the screen. It became possible. In addition, since data of at least 10 adjacent lines is distributed to different inner code blocks, even if an error occurs in one inner code block, correction of an erroneous pixel is performed using data of lines above and below the erroneous pixel. Is possible.

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 2 is a block diagram showing the configuration of the digital video signal transmission device of the present invention. In FIG. 2, reference numeral 1 denotes sampled digital video data, 2 denotes in-line shuffling means, 3 denotes an outer encoder, 4 denotes a write address generating means, 5 denotes a buffer memory, 6 denotes a read address generating means, and 7 denotes an inner encoder. is there. In the present embodiment, a case will be described in which a digital video signal is in a wide PAL format.
The sampling frequency is 18 MHz for the luminance signal Y,
It is assumed that the frequency of the two color difference signals Cb and Cr is 9 MHz. It is assumed that the number of effective samples on the screen actually stored in the digital VTR is 960 samples in the horizontal direction and 304 lines in the vertical direction. Also, the color difference signal C
It is assumed that r and Cb are 480 samples which are half of Y in the horizontal direction and 304 lines in the vertical direction. The number of quantization bits for both the luminance signal and the chrominance signal is 8 bits. The sampling structure has an orthogonal structure between lines, fields, and frames, and it is assumed that the sample points of Cr and Cb are at the same positions as the odd-numbered sample points of Y in each line.

The above sample data is divided into four channels in each line. That is, in each channel, Y is 240 samples and Cr and Cb are 1 in one line.
There are 20 samples. Here, assuming that a luminance signal sampled at the same position as the color difference signal is Y0, and a luminance signal sampled at a position different from the color difference signal is Y1, both Y0, Y1, Cr and Cb are included in one line in each channel. Be a sample. FIG. 2 is a block diagram showing shuffling in each channel. The 120 sample data 1 of each of Y0, Y1, Cb, and Cr in one channel are shuffled by the intra-line shuffling means 2. That is, Y0, Y1, Cr,
Each data of Cb is in-line shuffling means 2
In, the order in the line is almost randomly changed. In FIG. 2, CH is a channel number, H is a sample number in a line, and L is a line number. The intra-line shuffling means 2 converts the intra-line sample address H into an outer code address Obyte. At this time, the shuffling pattern is changed for each channel and each line. Then, in the outer encoder 3, an outer code check byte is added to each of the shuffled data of Y0, Y1, Cb, and Cr. For example, in this embodiment, an 8-byte check byte is added. That is, the number of data of the outer code block is 12
It becomes 8. The write address generating means 4 generates an address for writing the outer code block to which the check byte has been added by the outer encoder 3 into the buffer memory 5. Since the logical configuration of the buffer memory is a two-dimensional array, the address is stored in two rows and columns as follows.
Think in dimensions. In other words, the address space of the buffer memory 5 is conceptually 1216 as shown in FIG.
Consider a * 128 two-dimensional array. The vertical direction corresponds to the outer code block length, and the horizontal direction corresponds to the number of outer code blocks per one field per channel. That is, there are four types of outer code blocks of Y0, Y1, Cb, and Cr per one line per channel, and there are 304 lines per field, so that 4 * 304 = 1216. That is, the array shown in FIG. 3 can store data of one field of each channel. Here, the line number input to the write address generation means 4 is L (0 ≦ L ≦ 30
3) The sample number in the outer code block is
(0 ≦ Obyte ≦ 127), the vertical address of the array shown in FIG. 3 is ROW (0 ≦ ROW ≦ 127), and the horizontal address is COLUMN (0 ≦ COLUMN ≦ 121).
Assuming that 5), the respective outer code blocks corresponding to Y0, Y1, Cb, and Cr are written to the buffer memory 5 according to the equations (2) and (3).

Y0: COLUMN = 4 * ((A * L) MOD 304) Cb: COLUMN = 4 * ((A * L) MOD 304) +1 Cr: COLUMN = 4 * ((A * L) MOD 304) +2 Y1: COLUMN = 4 * ((A * L) MOD 304) +3 (A is an integer and A and 304 are mutually prime) (2) ROW = Obyte (common to Y0, Y1, Cr and Cb) ( 3) As an example, FIG. 4 shows a state of writing to the buffer memory when A = 81. That is, Y0 of line 0
The outer code block composed of signals is sequentially written in the vertical direction at the location of address 0 in the horizontal direction of the buffer memory. Similarly, the Cb signal on line 0 is applied to address 1,
The Cr signal is written to address 2 and the Y1 signal is written to address 3. Further, the Y0 signal of the line 1 is the address 324.
The Cb signal is written to the address 325, the Cr signal is written to the address 326, and the Y1 signal is written to the address 327. Next, a read address for reading data from the buffer memory 5 is generated by the read address generating means 6, and data written in the buffer memory in the vertical direction is read in the horizontal direction. Reading from the buffer memory 5 is performed in block units, and the inner encoder 7 adds an inner code check byte for each block. In this embodiment, the inner code block length is 76 bytes, and 8 check bytes are added for every 76 bytes. Since the inner code block length is 76 bytes, one inner code block is sampled on the same line (Y
(0, Cb, Cr, Y1) 4 bytes constitute a set, and data of 19 lines is included.

Next, by choosing an appropriate value of A,
A description will be given of the fact that it is possible to prevent data of a line adjacent to the same inner code block from being included.
According to the equation (2), the (Y0, Cb, Cr, Y1) signals sampled on the same line are converted together, so that for simplicity, the signals in the horizontal direction of the address space of the buffer memory shown in FIG. The address is divided by 4, and the address space of the buffer memory is considered to be a 304 * 128 array shown in FIG. At this time, equation (2) is converted to equation (4). That is, the horizontal address of the buffer memory having the address space shown in FIG.
If LUMN ′ ≦ 303), COLUMN ′ = (A * L) MOD 304 (A is an integer, and A and 304 are mutually prime) (4) 76 bytes, that is, 19 lines of data are contained in one inner code block. Therefore, 16 inner code blocks are included in the horizontal direction of the 304 * 128 array shown in FIG. FIGS. 6 and 7 show the line numbers before conversion of the data contained in each of the above 16 inner code blocks. FIG. 6 shows the case where A = 81, and FIG. 7 shows the case where A = 223. Each row in FIGS. 6 and 7 shows an inner code block composed of 19 lines of data, and the numbers indicate the line numbers before conversion of the data included in the inner code. The line numbers are rearranged in ascending order. According to FIG. 6, the minimum distance in the line direction among the data included in one inner code block is 15 lines (immediately).
That is, m = 14) , and even if an error occurs in the inner code block, erroneous samples are dispersed in the vertical direction on the screen,
At least 15 lines apart are erroneous. As described above, according to the present invention, when compared with the conventional example, the minimum distance in the conventional example shown in FIG. 13 is one line, that is, when an error occurs in the inner code block, the lines adjacent to each other on the screen are This is a very excellent method against errors in the data, and in the conventional example, errors are concentrated on the upper part of the screen.

Next, as an embodiment of the present invention, a case where a digital video signal is in a wide NTSC system will be described. The number of effective samples on the screen actually stored in the digital VTR is 960 samples in the horizontal direction and 255 lines in the vertical direction. Also,
It is assumed that the color difference signals Cr and Cb have 480 samples, which is half of Y in the horizontal direction and 255 lines in the vertical direction. NTS
Even in the case of the C system, the configuration, processing, etc. are the same as in the case of the PAL system, and only the various parameters need to be changed. FIG. 8 shows the address space of the buffer memory in the case of the NTSC system. FIG. 8 corresponds to FIG. 5 in the PAL system. FIG. 8 shows an array of 255 * 128, in which the vertical direction corresponds to the outer code block length and the horizontal direction corresponds to the number of lines. In the array shown in FIG. 8, the write address is determined according to the equation (5). That is, the horizontal address of the buffer memory having the address space shown in FIG.
If COLUMN '≦ 254), COLUMN' = (A * L) MOD 255 (A is an integer A and 255 are mutually prime) (5) 85 bytes, that is, 22 lines of data are contained in one inner code block. In the horizontal direction of the 255 * 128 array shown in FIG. 8, 12 inner code blocks are included. However,
Since the inner code block length is not divisible by 4, (Y0,
It should be noted that the sequence of (Cb, Cr, Y1) may extend between inner code blocks. FIG. 9 shows the line numbers before the conversion of the data contained in each of the above-mentioned 12 inner code blocks.
FIG. 9 shows the case where A = 22. Each row in FIG. 9 shows one inner code block including 22 lines of data.
The numbers indicate the line numbers before the conversion of the data contained in the inner code, and the line numbers are rearranged in ascending order within the inner code. The numbers marked with * in FIG. 9 indicate the line numbers when the sequence of (Y0, Cb, Cr, Y1) straddles the inner code blocks. Note that the present invention is not affected even if the sequence of (Y0, Cb, Cr, Y1) straddles the inner code block. FIG.
According to the above, the minimum distance in the line direction among the data included in one inner code block is 11 lines (that is, m = 10) , and even if an error occurs in the inner code block, an erroneous sample is Scattered in the direction, and a place at least 11 lines away is erroneous.

In a digital VTR, one or a plurality of inner code blocks frequently cause an error at the time of reproduction due to an initial defect of the tape or adhesion of dust to the tape. In the present invention, samples of adjacent m lines (m is an integer m ≧ 10 ) are recorded in different inner code blocks and recorded.
Or, even if an error occurs in a plurality of inner code blocks, the error is dispersed in the upper and lower line directions on the screen, so that the erroneous pixel can be easily corrected by using the neighboring correctly reproduced pixels. is there.

In the embodiment of the present invention, the sampling frequency is set to 18 MHz for the luminance signal, and to the color difference signals Cr and C for the luminance signal.
b is 9 MHz, but the sampling frequency is not limited to these frequencies. For example, as in the conventional D-1, the luminance signal Y is 13.5 MHz and the color difference signal C is
r and Cb may be set to 6.75 MHz. Further, in this embodiment, the digital VTR for recording a component signal is used, but it is needless to say that the digital VTR for recording a composite signal may be used.
Further, in the present embodiment, the case where digital data is in the wide PAL system and the case in which the digital data is in the wide NTSC has been described by way of example.
0 samples, 304 lines in the vertical direction, Cb and Cr are 360 samples of half of Y in the horizontal direction, and 304 samples in the vertical direction.
Needless to say, the line or Y may be 720 samples in the horizontal direction, 255 lines in the vertical direction, Cb and Cr may be 360 samples, which is half of Y in the horizontal direction, and 255 lines in the vertical direction. Also, the number of quantization bits of Y, Cb, and Cr at each sample point is 8 bits, but may be 9 bits or 10 bits, for example. Further, the constant A used in the equations (1), (2), (4), and (5) can take a value other than the value shown in the present embodiment. In this embodiment, one line is divided into four channels. However, it is not always necessary to divide the line into four channels, and the buffer memory can store one field. It may store data. That is, the present invention can be implemented by changing the size of the buffer memory according to the number of samples stored in the buffer memory. In this embodiment, an example of a digital VTR has been described. However, it is needless to say that the present invention can be applied to a device for recording on a disk, such as a magnetic disk and an optical disk. Obviously, the present invention can be applied to a transmission device in exactly the same manner.

[0022]

As described above, according to the present invention, even when an error occurs during reproduction of a VTR or the like or transmission of digital data, the error can be dispersed on the screen.
As a result, it is possible to interpolate an erroneous pixel by using a peripherally reproduced pixel, and the practical effect of the present invention is great.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a virtual array for storing digital video data according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an embodiment of a digital video data transmission device of the present invention.

FIG. 3 is a schematic diagram showing an address space of a buffer memory for storing digital video data in one embodiment of the present invention.

FIG. 4 is a schematic diagram showing a method of writing data to a buffer memory.

FIG. 5 is a schematic diagram showing an address space of a buffer memory for storing digital video data in one embodiment of the present invention.

FIG. 6 is a diagram showing a line number (A =
Illustration showing (81)

FIG. 7 shows a line number (A =
Explanatory drawing showing 223)

FIG. 8 is a schematic diagram showing an address space of a buffer memory for storing digital video data in one embodiment of the present invention.

FIG. 9 shows a line number (A =
Explanatory diagram showing 22)

FIG. 10 is a block diagram showing a configuration of a digital video data transmission device in a conventional example.

FIG. 11 is a schematic diagram showing an address space of a buffer memory for storing digital video data in a conventional example.

FIG. 12 is a schematic diagram showing an address space of a buffer memory for storing digital video data in a conventional example.

FIG. 13 is an explanatory diagram showing line numbers included in one inner code block in a conventional example.

[Explanation of symbols]

 2 In-line shuffling means 3 Outer encoder 4 Write address generating means 5 Buffer memory 6 Read address generating means 7 Inner encoder 8 Read address generating means

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-57-164408 (JP, A) JP-A-1-233978 (JP, A) JP-A-7-99631 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H04N ^7/ 24-7/68 H04N 5/91-5/956

Claims (2)

(57) [Claims] 1. A digital video signal on the same line
In a digital video signal transmission method for converting and storing an address added to data of an outer code block to be configured and reading and transmitting the stored digital video signal, when converting the address, For every digital video signal sample, the adjacent m lines (m
Is a digital video signal transmission system in which samples of an integer m ≧ 10 ) are distributed to different inner code blocks, and read and transmitted in units of the inner code blocks . 2. A transmission apparatus for a digital video signal , comprising: a buffer memory capable of storing a sample of the digital video signal;
Is added to the data of the outer code block consisting of
And means for reading the transmission address conversion means for converting the dress to the address of the buffer memory, the digital video data stored in the buffer memory in inner code block units, said address translation means, adjacent m lines ( m is an integer m ≧ 10 ) different samples
Translate addresses to distribute to the inner code block
That digital video signal transmission apparatus.