JP3274270B2 - Method for adjusting cycle of oscillation circuit in synchronous semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous semiconductor memory device configured to take in input signals such as control signals and address signals in synchronization with a system clock signal .
The present invention relates to a method for adjusting the period of an oscillation circuit .

[0002]

2. Description of the Related Art Conventionally, for example, a synchronous DRAM (Dynamic Random Access Memory) has been used as a synchronous semiconductor memory device.
emory), so-called SDRAM (Synchronous DRA)
M) are known.

In such an SDRAM, control signals such as a row address strobe signal / RAS, a column address strobe signal / CAS, and a write enable signal / WE are integrated into a command for determining an operation mode. In this case, the data is taken in in synchronization with the system clock signal CLK.

[0004] Incidentally, in addition to the SDRAM, the operation mode of the DRAM is changed by the timing shift of the level change of the row address strobe signal / RAS and the column address strobe signal / CAS regardless of the system clock signal CLK. Asynchronous DRAMs for determining are also known.

Here, in the DRAM, a timer is required to control the refresh operation.
A built-in oscillation circuit and a counter composed of a frequency dividing circuit for counting the oscillation output of the oscillation circuit are built in, and these are used to constitute a timer.

In order for the operation of this timer to be accurate within an allowable range, that is, for the period of the output signal of the counter to be appropriate, the oscillation frequency of the oscillation circuit must be appropriate.

For this reason, the oscillation circuit is usually configured so that the oscillation frequency can be finely adjusted by cutting a fuse. However, in order to finely adjust the oscillation frequency of the oscillation circuit, the precondition is as follows. , It is necessary to measure the period of the output signal of the counter.

Here, in an asynchronous DRAM,
The measurement of the period of the output signal of the counter is performed by using a mode called a counter test cycle.

FIG. 19 is a waveform chart for explaining a method of measuring the period of the output signal of the counter by the counter test cycle. FIG. 19A shows a row address strobe signal / RAS, and FIG. 19B shows a column address signal. FIG. 19C and FIG. 19D show the output state of data.

That is, when measuring the period of the output signal of the counter by the counter test cycle, first, the column address strobe signal / CAS is changed from the H level to the L level, and then the row address strobe is changed. Signal / RAS is changed from H level to L level.

In this way, a CBR (CAS before RAS refresh) cycle is set, but the measurement time by the counter is set to t ₁ , for example, 100
At μs, the process shifts to a self-refresh cycle, data output is inhibited, and the output state of the data output circuit is set to a high impedance state.

Therefore, when the CBR cycle is set, the counter counts the oscillation output of the oscillation circuit and measures 100 μs after the row address strobe signal / RAS goes low.

On the other hand, after setting the CBR cycle, the column address strobe signal / CAS is set to H level,
When the column address strobe signal / CAS is set to L level again before the measurement time by the counter reaches 100 μs from the time when the row address strobe signal / RAS is set to L level, as shown in FIG. Becomes the data output state.

On the other hand, after the CBR cycle is set, the column measurement time of the counter becomes 100 μm from the time when the column address strobe signal / CAS is set to the H level and the row address strobe signal / RAS is set to the L level.
s, the column address strobe signal / CAS is again set to the L level.
Since we are transitioning to a self-refresh cycle,
The output state of the data output circuit is in a high impedance state.

Therefore, the point in time when the column address strobe signal / CAS is changed to L level again so that the output state of the data output circuit becomes the data output state, and from this state, the column address strobe signal / CAS is reset again. The level of the L level is gradually reduced, the output state of the data output circuit is observed, and the state where the output state of the data output circuit changes from the data output state to the high impedance state is set.

In this case, the counter determines that the time t _{2 from} when the row address strobe signal / RAS is set to L level to when the column address strobe signal / CAS is set again to L level is 100 μs. Time.

In this way, the actual time of the time when the counter determines that it is 100 μs, that is, the actual time of one cycle of the output signal of the counter can be measured.

Here, since the counter is constituted by a frequency dividing circuit, the oscillation frequency of the oscillation circuit can be calculated by calculating backward from the frequency division ratio, and by finely adjusting the oscillation frequency of the oscillation circuit, In addition, the period of the output signal of the counter can be optimized.

[0019]

However, the asynchronous type D
Unlike a RAM, in the case of an SDRAM, when a self-refresh command is taken in as an operation mode determination command, the cycle is set to, for example, 16 μs immediately.
Shift to the refresh operation.

For this reason, in the SDRAM, it is impossible to set a counter test cycle unlike an asynchronous DRAM, and it is not possible to measure the period of the output signal of the counter by a simple method. There was a problem.

In view of the above, the present invention provides a simple method.
An object of the present invention is to provide a method for adjusting the oscillation frequency of an oscillation circuit in a synchronous semiconductor memory device, which can adjust the oscillation frequency of an oscillation circuit and optimize the cycle of an output signal of a counter.

[0022]

According to the present invention , there is provided a method of adjusting a cycle of an oscillation circuit in a synchronous semiconductor memory device according to the present invention.
Input a self-refresh instruction in synchronization with the
And responding to the input of the self-refresh command.
Counter starts counting the oscillation signal from the oscillation circuit.
And then read in synchronization with the clock signal
Input a command and respond to it by setting the data output terminal to data.
The process of setting the output state, and the count number has reached a predetermined value.
At this point, the counter outputs a count end signal,
The data output terminal is connected to the data output terminal by a count end signal.
Data output state to high impedance state.
Receiving the self-refresh command
Measure the time from the time to the time when the state changes
And an oscillation frequency of the oscillation circuit based on the time.
It has a step of adjusting the number.

[0023]

According to the present invention, a self-refresh instruction is issued.
By inputting the counter, the counter
Signal count operation, then input read command
To set the data output terminal to the data output state.
And then responds to the end of counting by the counter.
Output terminal is in high impedance state from data output state
A series of steps to change the state is performed,
By performing these steps, self-reflection
Data output terminal is in the state from the point when the
Measure the time up to the point when the state changed, and based on this time
And execute the process of adjusting the oscillation frequency of the oscillation circuit
It is possible to do.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 1 to 18, an embodiment of the present invention will be described .
A case where the present invention is applied to a cycle adjusting method will be described as an example.

FIG. 1 shows an SD to which an embodiment of the present invention is applied.
FIG. 1 is a block diagram showing a main part of a RAM , where 1 is an SDRAM
The main body 2 is a memory cell array section in which memory cells are arranged, and 3 is an address buffer to which an address signal is input.

A row decoder 4 decodes a row address signal among address signals to select a word line.
Reference numeral 5 denotes a column decoder for decoding a column address signal among the address signals to select a column (column).

Reference numeral 6 denotes a data input / output circuit for inputting / outputting data, and reference numeral 7 denotes a clock buffer to which a system clock signal CLK is input.

Reference numeral 8 denotes a row address strobe signal / RAS and a column address strobe signal / CAS.
And an operation control circuit that receives a control signal such as a write enable signal / WE and controls the operation of each circuit.

Reference numeral 9 denotes an oscillating circuit, and reference numeral 10 denotes a self-refresh interval signal which counts the oscillation output of the oscillating circuit 9 and determines a self-refresh interval. The self-refresh interval signal is supplied to the row decoder 4. The counter supplies this self-refresh interval signal to the data input / output circuit 6 as the output disable signal DIS.

FIG . 2 shows the data input / output circuit 6 and the counter 1
FIG. 3 is a circuit diagram illustrating a configuration of a zero . In the data input / output circuit 6, 11 is an output unit, 12 is an input unit, 13 is an inverter, 14 is an OR circuit, 15 is a NOR circuit, and 16 is p
MOS transistor, 17 is an nMOS transistor, 1
8 is a data input / output terminal, DOUT is output data, DIN
Is input data.

An output section 11 of the data input / output circuit 6 is supplied with an output enable signal / EN from the operation control circuit 8, a cell data DATA from the memory cell array section 2, and an output disable signal DIS from the counter 10.

Here, as shown in FIG. 3, when the output enable signal / EN = “H”, the output of the OR circuit 14 =
“H”, pMOS transistor 16 = OFF, output of NOR circuit 15 = “L”, nMOS transistor 17 = O
FF, and the output state of the output unit 11 is a high impedance state (Hi-Z).

As shown in FIG. 4, when the output disable signal DIS = “H”, the output of the OR circuit 14
“H”, pMOS transistor 16 = OFF, output of NOR circuit 15 = “L”, nMOS transistor 17 = O
FF, and the output state of the output unit 11 is set to a high impedance state.

As shown in FIG. 5, the output enable signal / EN = "L" and the output disable signal DIS =
In the case of "L", a read state is set and the cell data DA
When TA = “H”, the output of the OR circuit 14 = “H”, p
MOS transistor 16 = OFF, output of inverter 13 = “L”, output of NOR circuit 15 = “H”, nMOS
The transistor 17 is turned on, and the output data DOUT =
"L".

On the other hand, as shown in FIG. 6, when the cell data DATA = “L”, the output of the OR circuit 14 = “L”, the pMOS transistor 16 = ON, and the output of the inverter 13 = “H”. Output of NOR circuit 15 =
"L", the nMOS transistor 17 is turned off, and the output data DOUT is set to "H".

In the counter 10, 19 ₁ , 1
9 ₂ and 19 _n are T (toggle) flip-flop circuits, CL
R-COUNT is a clear count signal supplied from the operation control circuit 8. The illustration of the T flip-flop circuits 19 ₃ , 19 _4, ... 19 _n-1 is omitted.

These T flip-flop circuits 19 ₁ , 1
9 ₂ · · · 19 _n is the same circuit configuration, if Shimese on behalf of the T flip-flop circuit 19 ₁ is configured as shown in FIG.

In FIG. 7, 20 to 23 are inverters, 24,
25 is a NAND circuit, 26 and 27 are transfer gates, 28 and 29 are nMOS transistors, 30, 3
1 is a pMOS transistor.

FIG. 8 shows the T flip-flop circuit 1
Is a waveform diagram showing the 9 _first operation, Fig. 8A is clear count signal CLR-COUNT, Figure 8B shows the oscillation output S _OSC, the positive-phase output Q of FIG. 8C T flip flop circuit 19 ₁ of the oscillator circuit 9 ing.

That is, first, as shown in FIG. 9, when the oscillation output S _OSC of the oscillation circuit 9 is “L”, the transfer gate 2
Consider the case where 6 = OFF and transfer gate 27 = ON.

In this case, the T flip-flop circuit 19 ₁
Indicates that the clear count signal CLR-COUNT is "L"
, The output is cleared and the output of the NAND circuit 24 =
“H”, output of inverter 21 = “L”, positive-phase output Q =
“L”, the output of the NAND circuit 25 = “H”, and the output of the inverter 23 = “H”.

From this state, as shown in FIG. 10, when the clear count signal CLR-COUNT returns to "H", the output of the NAND circuit 24 = "H" and the inverter 2
1 output = “L”, positive-phase output Q = “L”, output of NAND circuit 25 = “H”, output of inverter 23 = “H” are maintained.

Next, as shown in FIG. 11, when the oscillation output S _OSC of the oscillation circuit 9 becomes “H”, the transfer gate 26 is turned on and the transfer gate 27 is turned off.
The output of the NAND circuit 24 is set to “L”, the output of the inverter 21 is set to “H”, and the positive-phase output Q is set to “L”, NA
Output of ND circuit 25 = “H”, output of inverter 23 =
The state of "H" is maintained.

Next, as shown in FIG. 12, when the oscillation output S _OSC of the oscillation circuit 9 becomes “L”, the transfer gate 26 is turned off and the transfer gate 27 is turned on.
The state of the output of the NAND circuit 24 = “L”, the output of the inverter 21 = “H” is maintained, and the positive-phase output Q =
“H”, the output of the NAND circuit 25 = “L”, and the output of the inverter 23 = “L”.

Next, as shown in FIG. 13, when the oscillation output S _OSC of the oscillation circuit 9 becomes “H”, the transfer gate 26 is turned on and the transfer gate 27 is turned off.
The output of the NAND circuit 24 is set to “H”, the output of the inverter 21 is set to “L”, and the positive-phase output Q is set to “H”;
Output of ND circuit 25 = “L”, output of inverter 23 =
The state of "L" is maintained.

Next, as shown in FIG. 14, when the oscillation output S _OSC of the oscillation circuit 9 becomes “L”, the transfer gate 26 is turned off and the transfer gate 27 is turned on.
The state of the output of the NAND circuit 24 = “H”, the output of the inverter 21 = “L” is maintained, and the positive-phase output Q =
“L”, the output of the NAND circuit 25 = “H”, and the output of the inverter 23 = “H”.

Next, as shown in FIG. 15, when the oscillation output S _OSC of the oscillation circuit 9 becomes “H”, the transfer gate 26 is turned on and the transfer gate 27 is turned off.
The output of the NAND circuit 24 is set to “L”, the output of the inverter 21 is set to “H”, and the positive-phase output Q is set to “L”, NA
Output of ND circuit 25 = “H”, output of inverter 23 =
The state of "H" is maintained.

Next, as shown in FIG. 16, when the oscillation output S _OSC of the oscillation circuit 9 becomes “L”, the transfer gate 26 is turned off and the transfer gate 27 is turned on.
The state of the output of the NAND circuit 24 = “L”, the output of the inverter 21 = “H” is maintained, and the positive-phase output Q =
“H”, the output of the NAND circuit 25 = “L”, and the output of the inverter 23 = “L”.

[0049] Therefore, the T flip-flop circuit 19 _1, as shown in FIG. 8, the oscillation output S of the oscillation circuit 9
_The counter 10 operates as a frequency divider that divides the _OSC by half, and the counter 10 sets the oscillation output S _OSC of the oscillation circuit 9 to 1
/ 2n.

FIG. 17 is a waveform diagram showing the operation of the counter 10. FIG. 17A is a clear count signal CLR-COUNT output from the operation control circuit 8, and FIG.
Indicates the oscillation output S _OSC of the oscillation circuit 9.

[0051] Further, Figure 17C the T flip-flop circuits (TFF) 19 ₁ of the positive phase output Q, FIG. 17D T flip flop circuit 19 ₂ of the positive-phase output Q, FIG. 17E T flip flop circuit 19 _n positive phase An output Q, that is, an output disable signal DIS is shown.

FIG. 18 is a waveform diagram for explaining an embodiment of the present invention . FIG. 18A shows a system clock signal CLK, FIG. 18B shows a row address strobe signal / RAS, and FIG. 18C shows a column address signal. FIG. 18D shows the strobe signal / CAS, and FIG. 18D shows the write enable signal / WE.

FIG. 18E shows a clear count signal CLR-COUNT output from the operation control circuit 8, and FIG.
8F is the cell data DAT from the memory cell array unit 2.
18A shows an output enable signal / EN output from the operation control circuit 8, FIG. 18H shows output data DOUT output from the output unit 11 of the data input / output circuit 6, and FIG.
Is the oscillation output S _OSC of the oscillation circuit 9, and FIG.
The output disable signal DIS output from 0 is shown.

[0054] That is, in this embodiment, first, the row address strobe signal / RAS = "L", column address strobe signal / CAS = "H", and the write enable signal / WE = "L", giving self-refresh command, at time T _1, along with the self-refresh command is taken up and activates the oscillator circuit 9,
The counter 10 is cleared by setting the clear count signal CLR-COUNT = “L”.

Next, the row address strobe signal / R
AS = “H”, column address strobe signal / CA
S = “L”, write enable signal / WE = “H”, and a read command is given. At time T ₂ , the read command is fetched, and output enable signal / EN = “L”, and data The output state of the output unit 11 of the input / output circuit 6 is set to the data output state, and the output data DOUT is output.

Here, after the counter 10 is cleared, the counter 10 calculates one cycle of a self-refresh cycle, for example, 16 μm from the count number of the oscillation output S _OSC of the oscillation circuit 9.
When it is determined that s has elapsed, the output disable signal DIS is set to “H”.

As a result, the output of the OR circuit 14 = “H”,
The pMOS transistor 16 = OFF, the output of the NOR circuit 15 = “L”, the nMOS transistor 17 = OFF, and the output state of the output unit 11 of the data input / output circuit 6 becomes a high impedance state.

Therefore, the output unit 11 of the data input / output circuit 6 starts at time T ₁ when the self-refresh command is fetched.
Time T ₃ when the output state of the circuit becomes the high impedance state
By measuring the time ΔT until the counter 10
Is cleared, the actual time when it is determined that one cycle of the self-refresh cycle, for example, 16 μs has elapsed, that is, the cycle of the output signal of the counter 10 can be known.

Here, since the counter 10 is constituted by a frequency dividing circuit, the counter 10 is inversely calculated from the frequency dividing ratio to obtain the oscillation circuit 9.
The oscillation frequency of the counter 10 can be finely adjusted, and the period of the output signal of the counter 10 can be optimized.

As described above, according to the present embodiment, the period of the output signal of the counter 10 can be known by a simple method.
Thus, the oscillation frequency of the oscillation circuit 9 can be finely adjusted, and the period of the output signal of the counter 10 can be optimized.

In the above-described embodiment, after the operation of the counter 10 is enabled, the counter 10 counts the number of the oscillation output of the oscillation circuit 9 from the self-refresh cycle of one.
When it is determined that the cycle has elapsed, the data input / output circuit 6
The output state of the data input / output circuit 6 is controlled to the high impedance state. Alternatively, the output state of the data input / output circuit 6 may be controlled to the data output state. In this case, a self-refresh command is taken in. In such a case, the output state of the data input / output circuit 6 is controlled so as to be in a high impedance state.
The period of the output signal of the counter 10 can be measured by the same simple method as described above.

In the above embodiment, the self-
Although the case where the refresh instruction is used has been described, instead of this, the self-refresh operation is not performed, the operation of the counter 10 is enabled, and then the counter 10 determines the self-refresh from the count number of the oscillation output of the oscillation circuit 9. When the counter 10 determines that one cycle of the refresh cycle has elapsed, the counter 10 may use a special instruction for operating the output state of the data input / output circuit 6 to a high impedance state.

[0063]

As described above, according to the present invention, first,
By entering a self-refresh instruction,
Starts counting the oscillation signal from the oscillation circuit.
And then input a read instruction to
Set the output terminal to the data output state, and then
Data output terminal in data output state in response to
State from high state to high impedance state
By executing a series of steps, self-refresh
Data output terminal is in the state from the point when the
Measure the time to the point of change, and based on this time
And execute the process of adjusting the oscillation frequency of the oscillation circuit
It is possible to do. Therefore, in an easy way
Adjust the oscillation frequency of the oscillation circuit and adjust the output signal of the counter.
The cycle can be optimized .

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main part of an SDRAM to which an embodiment of the present invention is applied .

FIG. 2 is a circuit diagram showing a configuration of a data input / output circuit and a counter provided in the SDRAM shown in FIG.

FIG. 3 is a circuit diagram showing an operation of an output unit of a data input / output circuit provided in the SDRAM shown in FIG.

FIG. 4 is a circuit diagram showing an operation of an output unit of a data input / output circuit provided in the SDRAM shown in FIG.

FIG. 5 is a circuit diagram showing an operation of an output unit of a data input / output circuit provided in the SDRAM shown in FIG.

FIG. 6 is a circuit diagram showing an operation of an output unit of a data input / output circuit provided in the SDRAM shown in FIG.

FIG. 7 is a circuit diagram showing a T flip-flop circuit forming a counter provided in the SDRAM shown in FIG . 1 ;

8 is a waveform chart showing an operation of a T flip-flop circuit forming a counter provided in the SDRAM shown in FIG.

FIG. 9 is a circuit diagram showing an operation of a T flip-flop circuit forming a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 10 is a circuit diagram showing an operation of a T flip-flop circuit constituting a counter provided in the SDRAM shown in FIG . 1 ;

11 is a circuit diagram showing an operation of a T flip-flop circuit forming a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 12 is a circuit diagram showing an operation of a T flip-flop circuit constituting a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 13 is a circuit diagram showing an operation of a T flip-flop circuit constituting a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 14 is a circuit diagram showing an operation of a T flip-flop circuit forming a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 15 is a circuit diagram showing an operation of a T flip-flop circuit constituting a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 16 is a circuit diagram showing an operation of a T flip-flop circuit forming a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 17 is a circuit diagram showing an operation of a counter provided in the SDRAM shown in FIG . 1 ;

FIG. 18 is a waveform chart for explaining one embodiment of the present invention.

FIG. 19 is a waveform diagram for explaining a method of measuring a cycle of an output signal of a counter that counts an oscillation output of an oscillation circuit in an asynchronous DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 SDRAM main body 2 Memory cell array part 3 Address buffer 4 Row decoder 5 Column decoder 6 Data input / output circuit 7 Clock buffer 8 Operation control circuit 9 Oscillation circuit 10 Counter

Claims (1)

(57) [Claims] A self-refresh circuit in synchronization with a clock signal.
And a counter in response to the input of the self-refresh command.
Process where the data starts counting the oscillation signal from the oscillation circuit
And then input a read command in synchronization with the clock signal,
In response, the data output terminal is set to the data output state
The counter and the counter are counted when the count reaches a predetermined value.
Output a count end signal, and by the count end signal,
The data output terminal is pulled high from the data output state.
Changing the state to the impedance state, and when the self-refresh command is input,
Measuring the time until the state change, and adjusting the oscillation frequency of the oscillation circuit based on the time
Synchronous semiconductor memory device having a step of performing
Method of adjusting the period of the oscillation circuit in the device.