JP3273461B2 - Power converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter,
In particular, while suppressing the overvoltage and reducing the loss at the time of switching of the switching element by the power semiconductor element or the like, it is possible to set an appropriate capacitance of the snubber capacitor according to the withstand capacity of the element, and, The present invention relates to a power converter including a snubber circuit capable of reducing stress.

[0002]

2. Description of the Related Art Generally, when a power semiconductor element or the like is used as a switching element and a current supplied to a load is cut off by this switching element, energy accumulated in a wiring inductance together with a power supply voltage is applied to the element as a surge voltage. You. Circuit means for suppressing the voltage applied to the element within the allowable value of the element is a snubber circuit.The snubber circuit has, as basic elements, a capacitor as energy absorbing means and a discharging resistor thereof, and a discharge when charging the capacitor. It comprises a diode that bypasses the resistor.

[0003] As a prior art relating to a power conversion device having a snubber circuit of this kind, for example, Japanese Patent Application Laid-Open No. 6-3850 is disclosed.
A technique described in Japanese Patent Laid-Open Publication No. 6 (1996) -1994 is known. This prior art is an inverter in which two switching elements are formed in a bridge configuration, in which a snubber capacitor is provided for each switching element, and a snubber capacitor for clamping (hereinafter, referred to as a clamp capacitor) is provided in parallel with the bridge. It has. In the snubber circuit having such a configuration, when the switching element is turned off, first, an individual snubber capacitor having a small capacitance works to suppress an overvoltage applied to the switching element, and then, the energy stored in the main circuit wiring is reduced by the capacitance. An operation is performed in which a large clamp capacitor absorbs the light.

[0004]

Generally, in the snubber circuit, it is desirable to increase the capacity of the snubber capacitor constituting the snubber circuit in order to increase the overvoltage suppressing effect on the switching element. However, when the capacitance of the capacitor is increased, there is a problem that the loss of the snubber circuit increases. Assuming that the capacitance of the snubber capacitor is C and the voltage change during discharging is V, the loss of the snubber circuit is C
Is represented by V ^2/2, the capacitance of the snubber capacitor is higher loss is greatly increased.

[0005] In the prior art, the capacitance of each snubber capacitor is reduced, the capacitance of the clamp capacitor is set large, and the energy stored in the clamp capacitor is regenerated to the power supply to reduce the loss. However, in this snubber circuit, since the supply of electric charge to the clamp capacitor is mainly performed by the current passing through the individual snubber capacitor, when the capacitance of the individual snubber capacitor is smaller than the capacitance of the clamp capacitor, the capacitance is small. The larger the current flows through the clamp capacitor, the more the voltage of each snubber capacitor becomes more oscillating, causing stress on the individual snubber capacitors. Also,
This vibration causes an overshoot of the voltage, and the overshoot voltage is applied to the element as an overvoltage, thereby causing a problem that it is harmful to the original purpose of suppressing the overvoltage.

Further, when a bipolar transistor or IGBT is used as a switching element, as the voltage change (dV / dt) at the time of current interruption is larger, a tail current related to discharge of accumulated carriers increases, and switching loss of the element increases. I do. For this reason, the above-described oscillation of the voltage of the individual snubber capacitors causes a problem that the switching loss of the element has a bad influence.

Ideally, it is preferable to use a snubber circuit having a variable-capacitance snubber capacitor capable of increasing the capacity of the snubber capacitor according to an increase in current or voltage. In the snubber circuit of the related art described above, if the capacitance of each snubber capacitor is increased in accordance with an increase in the voltage, the oscillation of the voltage can be suppressed. However, making the capacitance of the capacitor variable requires newly providing a means for detecting a current or a voltage, a switch means for switching a plurality of capacitors, a means for controlling on / off of the switch means, and the like. This causes a problem of inviting an increase.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to make it possible to vary the capacitance of a snubber circuit capacitor by using low-cost and simple circuit means, and to provide a voltage for a switching element. It is an object of the present invention to provide a power conversion device that achieves both suppression and reduction of a snubber circuit loss, and also suppresses voltage oscillation to reduce stress on switching elements and other components and that can operate stably.

[0009]

According to the present invention, the object is to provide first and second switching elements connected in series between terminals of a main power supply, wherein the first and second switching elements are connected in response to a command from a control means. By controlling two switching elements,
In a power converter for supplying power to a load provided at a connection point between two switching elements, a first diode and a first capacitor connected between respective input / output terminals of the two switching elements are connected in series. Circuit means, and a second diode connected in series with a resistor and a second capacitor connected in parallel to each of the first diodes and passing a current in the same direction as the first diode. This is achieved by providing circuit means provided in parallel with the resistor, and a clamping snubber capacitor connecting the second capacitors.

The object of the present invention is to set the capacitance value of the second capacitor to be smaller than the capacitance value of the first capacitor. This is achieved by setting the capacitance value larger than the capacitance value of the second capacitor.

[0011]

In the power converter constructed as described above, the snubber capacitor for clamping is C5, and the first and second capacitors for the first switching element are C5.
1, 1st, 2nd for C2, 2nd switching element
Are C3 and C4. Also, when the first switching is on, the second switching element is off, and conversely, when the second switching element is on,
It is assumed that the first switching element is off. The first and second capacitors C1 and C2 for the first switching element constitute a first variable capacitance capacitor, and the first and second capacitors C3 and C4 for the second switching element are connected to the second variable capacitor. Is constructed.

Now, when the first switching element is on,
It is assumed that the second switching element is off. In this case, the first and second capacitors C1 and C2 provided in parallel with the first switching element have the same voltage and are charged with opposite polarities. The first and second capacitors C3 and C4 for the second switching element are:
The capacitor C3 is charged to a voltage equal to the power supply voltage, and the voltage of the capacitor C4 is zero. Further, the snubber capacitor C5 for clamping is charged to a voltage equal to the power supply voltage.

When the first switching element is turned off from the above-described state, a current continues to flow due to the energy stored in the wiring.
Flows from the diode to the load through C2 and C1 constituting the first variable capacitance capacitor, and charges these capacitors with a voltage. However, since the direction of the current of C2 is different from the polarity of the initially charged voltage, the initially charged voltage is discharged. On the other hand, the voltage of C1 is charged to the same polarity as the initial polarity. The remainder of the current is a diode and a snubber capacitor C for clamping.
5. Flow to the load through C4 and C3 constituting the second variable capacitance capacitor, and discharge the voltage of C4 and C3. At this time, while the voltage value of C3 decreases, the voltage of C4 is charged to a polarity opposite to that of C3 by the flowing current because the initial voltage is zero.

In the above-described operation, when the voltage of C2 decreases to a predetermined value (zero), the first diode which has been connected in series with C1 and has been in a reverse bias state by the voltage of C2 becomes conductive. , The capacitance of the first variable capacitance capacitor changes from a series combined capacitance of C1 and C2 to a single capacitance of C1. On the other hand, the voltage is charged in C4, the diode connected in series with C3, and the diode which has been in the conductive state until then becomes reverse-biased by the voltage of C4, and the second variable capacitance capacitor is connected to C3. The capacitance changes from a single capacitance to a series combined capacitance of C4 and C3.

As a result of the above-described operation, C1 is replaced by C5.
And the voltage of C2 becomes zero. Further, C3 and C4 are charged with voltages having the same voltage value and different polarities, and the combined voltage is canceled.

As described above, according to the power converter of the present invention, the overvoltage of the switching element is suppressed by the single capacitance of one of the two capacitors constituting the variable capacitance capacitor, and the discharging operation is performed by the current flowing through the series combined capacitance. Therefore, it is possible to sufficiently suppress the overvoltage of the switching element, and to reduce the snubber loss.

For example, assuming that the capacitance ratio between C1 and C2 is 4: 1 in the above description, the capacitance of the variable capacitance capacitor is 0.8 × C2 which is the series combined capacitance and the single capacitance (4
× C3) shows a five-fold change, and the overvoltage of the power semiconductor element can be sufficiently suppressed by the single capacitance of C1. Further, at the time of discharging, the discharging operation is performed by the current flowing in series with C1 and C2, so that only the snubber loss for the series combined capacitance is required.

In the above description, the diode controlled to be in the conductive state and the reverse bias state can be replaced by first and second switch means.
2, the same operation can be performed by controlling according to the voltage of C4.

[0019]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a power converter according to the present invention.

FIG. 1 is a diagram showing a configuration example of a power converter according to a first embodiment of the present invention, FIG. 2 is a diagram showing a current path for explaining the operation of the first embodiment of the present invention, and FIG. FIG. 4 is a waveform diagram for explaining the operation of the first embodiment of the present invention. FIG. 4 is a diagram for explaining the loss and the maximum voltage of the snubber circuit used in the first embodiment of the present invention in comparison with the prior art. FIG. 4 is a diagram for explaining a turn-off waveform of a switching element according to the first embodiment of the present invention in comparison with a conventional technique. In FIG. 1, 1 is a power supply, 2 is a load, Q1 and Q2 are IGBTs, D1 and D2 are diodes, Ds1 to Ds4 are snubber diodes, C1
C4 is a snubber capacitor, R1 and R2 are snubber resistors,
C5 is a clamp capacitor, and L1 and L2 are parasitic inductances.

A first embodiment of the present invention shown in FIG. 1 is an IGBT specially designed for a switching element using a power semiconductor element.
An upper arm composed of Q2 and a diode D2;
1 and a lower arm composed of a diode D1 are bridge-connected. This main circuit configuration corresponds to one phase of a three-phase inverter used to drive a load 2 such as a motor.

In FIG. 1, IGBTs Q1 and Q2, which are bridge-connected power semiconductor elements, have a collector terminal to which a current is input, an emitter terminal to output a current, and a gate terminal to which a control voltage is applied. The load 2 is controlled by applying or removing a control voltage to or from a terminal to pass or cut off a current flowing between the collector and the emitter. A path for supplying current from the power supply 1 to the load 2 using the IGBT Q1 is connected to the load 2 through an element (not shown) constituting an upper arm of another phase bridge via a wiring having a parasitic inductance L1 from the positive electrode of the power supply 1. , And then the load 2
From the other terminal to the connection point of IGBT Q1 and Q2, and further from the emitter terminal of IGBT Q1 to the negative electrode of power supply 1 through wiring L2 having parasitic inductance L2. In the above description, the parasitic inductances L1 and L2 are determined according to the shape of the wiring, and become smaller as the distance of the wiring becomes shorter. The load 2 is inductive like a motor, and the load current after the IGBT Q1 is turned off is returned to the diode D2.

A snubber circuit means in which a snubber diode Ds4, a clamp capacitor C5, and a snubber diode Ds2 are connected in series is connected to the bridge formed by the IGBTs Q1 and Q2 in parallel with the bridge. And
The snubber diodes Ds4 and Ds2 are respectively IG
They are connected in the direction in which current flows with the same polarity as BTQ2 and Q1. Further, snubber diodes Ds4 and Ds2 are connected in parallel with snubber resistors R2 and R1 for discharging, respectively.
Are provided.

A series circuit of snubber capacitors C1 and C2 is connected between the collector terminal of IGBT Q1 and the low potential side terminal (connection point of C5 and Ds2) of clamp capacitor C5, and capacitors C1 and C2 are connected. A snubber diode Ds1 functioning as a switch is provided between the connection point of the IGBT Q1 and the emitter terminal of the IGBT Q1. A series circuit of snubber capacitors C4 and C3 is connected between the emitter terminal of IGBT Q2 and the high-potential terminal of clamp capacitor C5 (the connection point between C5 and Ds4). A snubber diode Ds3 functioning as a switching means is provided between the connection point of the IGBT Q2 and the collector terminal of the IGBT Q2.

The series circuit of the snubber capacitors C1 and C2 and the series circuit of the snubber capacitors C4 and C3 function as variable capacitors by the snubber diodes Ds1 and Ds3 functioning as switch means. Note that the snubber diodes Ds1 and Ds3 are connected so as to allow current to flow in the same polarity as the IGBTs Q1 and Q2, respectively. Circuits connected between the collector and emitter terminals of the IGBTs Q1 and Q2 except for the clamp capacitor C5 described above are each provided with an IGBT.
It functions as an individual snubber circuit for Q1 and Q2.

Next, the operation of the first embodiment of the present invention having the above-described circuit configuration will be described.

In FIG. 2 showing the operation of the embodiment shown in FIG. 1 as a current path, FIG. 2A shows a current path when the IGBT Q1 is turned off, and FIG. 2B shows a current path when the IGBT Q1 is turned on. Is shown. FIG. 3 shows that when the IGBT Q1 is turned off or on in the embodiment shown in FIG.
Voltage V applied between collector and emitter of GBTQ1
ce, the current Ice flowing between the collector and the emitter of the IGBT Q1, the voltages Vc1 and Vc2 of the capacitors C1 and C2, and the voltage waveform of the voltage Vc5 of the capacitor C5 are shown. Although not shown, the voltages of the capacitors C3 and C4 will be described as Vc3 and Vc4, respectively.

In FIG. 3, T (Off) and T (On) indicate the times at which the IGBT Q1 turns off and on, respectively, E indicates the voltage of the power supply 1, and Vm indicates the maximum value of the voltage applied to the IGBT Q1. . In the following description, it is assumed that the capacitances of the capacitors C1 and C2 are set to C1> C2, and similarly, the capacitances of the capacitors C3 and C4 are set to C3> C4. Then, as described later, the capacitor C
1 and C2 are charged with voltages having the polarities shown in FIG. 1, respectively, during the ON period of the IGBT Q1, and these voltages are equal and this value is Vo. However, the voltage between the collector and the emitter terminal of the IGBT Q1 is zero because the voltages of the capacitors C1 and C2 are offset. At this time,
The capacitors C3 and C5 are charged with a voltage equal to the power supply voltage E, and the voltage of the capacitor C4 is set to zero for simplification.

Now, during the ON period of the IGBT Q1 before the time T (Off), the electromagnetic energy accumulated in the inductance of the main circuit wiring due to the current IL flowing through the load 2 can be expressed by the following equation (1). it can.

[0030]

(Equation 1)

In the off period of the IGBT Q1 after the time T (Off), the current due to the electromagnetic energy accumulated in the inductance of the wiring until the current is absorbed by the snubber circuit through the path indicated by the dotted line in FIG. It flows as a current of _{1 ~i 5.} That is, first, the current i ₁ tends to flow through the capacitors C1 and C2 as the first variable capacitance capacitors, but the voltage of the capacitor C2 charged during the ON period of the IGBT Q1 is forward with respect to the diode Ds2. Although it is a bias, it acts as a reverse bias for the diode Ds1, and at this time, the diode Ds1
Cannot pass current. Therefore, the current i ₁ is
It flows through the diode Ds2 via the capacitors C1 and C2, returns to the main circuit, and flows along the path leading to the negative electrode of the power supply. At this time, the capacitance of the capacitor as viewed from between the collector and emitter terminals of the IGBT Q1 is a combined capacitance in which the capacitors C1 and C2 are connected in series, and can be expressed as in Equation 2.

[0032]

(Equation 2)

In equation (2), for example, the capacitor C1
Assuming that the capacitance ratio between C2 and C2 is 4: 1, the combined capacitance of Expression 2 is 0.8C2, which is 1/5 of the capacitance when the capacitor C1 is used alone. The current i ₁ increases the charging voltage of the capacitor C1 from the voltage value Vo charged before the time T (Off), and conversely, the capacitor C2
, The charging voltage is reduced. If the capacitance of the capacitor is C1> C2, the value of the voltage increase of C1 and the value of the voltage decrease of C2 when the same current flows are different.
A voltage of (Vc1-Vc2) is applied between the collector and the emitter of TQ1.

At the same time when the above-mentioned current i ₁ starts to flow, the capacitors C3 and C3 constituting the second variable capacitance capacitor
4, the current i ₃ flows. The path of the current i ₃ is shown in FIG.
As shown in (a), since the diodes Ds3 and Ds4 both block this current, the current i ₃ flows in the order of the capacitors C3, C4 and C5, and the diode Ds
The current flows through the path returning to the negative electrode of the power supply 1 via the power supply 2.
The current i ₃ discharges the voltage charged in the capacitor C3 when the IGBT Q1 is turned on, while discharging the capacitor C3.
4 charges a voltage with a polarity different from that of the capacitor C3 shown in FIG. 2A, and also charges the capacitor C5.

During the period when the current i ₃ flows, the IGBT
The capacitance of the second variable capacitance capacitor as viewed from between the collector and emitter terminals of Q2 is the combined capacitance of capacitors C4 and C3 connected in series.
3 can be represented by an equation in which C2 is replaced by C4. The voltage values Vc3 and Vc4 of these capacitors
Is applied between the collector and the emitter of the IGBT Q2, and a voltage (Vc3-Vc4) is applied between the collector and the emitter of the IGBT Q2.
Recirculates through the diode D2. In addition, the voltages of the capacitors C4 and C3 are offset, so that
Diode Ds4 becomes forward biased, thereafter, it is possible to repeatedly charge the capacitor C5 and a current i ₄ to flow. The capacitance of the capacitor C5 is selected so that C5> C1. Most of the energy expressed by the equation 1 is absorbed by the capacitor C5.

Assuming that the time when the IGBT Q1 is turned off and the above-described current flows and the charging voltage Vc2 of the capacitor C2 becomes zero is T1, the reverse bias applied to the diode Ds1 by the voltage of the capacitor C2 becomes the time T1.
Thereafter disappears, the current through the capacitors C1, C2 composing the first variable capacitance capacitor that route is switched, the current changes from the current i ₁ to the current i _2, charging only the capacitor C1 through the diode Ds1 I will do it.

As described above, the snubber diode Ds1
Functions as a switch function that cuts off or allows current to flow according to the charging voltage of the capacitor C2. Therefore, after the time T1, the capacitor C1 works as a single capacitance. Now, for example, the capacitors C1 and C2
If the capacitance ratio of the first variable capacitance capacitor is 4: 1 after time T1, the capacitance of the first variable capacitance capacitor has increased five times the previous value, and the voltage rise of Vce can be rapidly suppressed. . Then, from the time when the current i ₂ starts flowing to the time when the energy shown in Expression 1 is absorbed, the capacitors C1 and C5 are provided in parallel with the IGBT Q1. As a result, the voltages of the capacitors C1 and C5 become equal, and the maximum voltage is V
m, and the maximum voltage of the IGBT Q1 is also equal to the value of Expression 3.

[0038]

(Equation 3)

Since the voltage applied to the second variable capacitance capacitor constituted by the capacitors C3 and C4 is a value obtained by subtracting the voltage of the capacitor C1 from the voltage of the capacitor C5, the voltage of the second variable capacitance capacitor is It is maintained at zero, and thus the current i ₃ does not flow.

In the above description, the capacitance of the capacitor C1 is larger than the capacitance of the capacitor C2. However, if the capacitance of the capacitor C1 is small and C2> C1,
Even if the capacity of the first variable capacitance capacitor is switched from the capacity expressed by Equation 2 to the capacity of only the capacitor C1, the change in the capacity is small and the effect of suppressing the voltage is small. Further, since the voltage cannot be sufficiently suppressed, the voltage of the capacitor C1 increases to be higher than the voltage of the capacitor C5, and so-called overshoot occurs. On the other hand, the voltage of the second variable capacitor undershoots to a negative value. Further, in order to eliminate the overshoot and the undershoot, the polarities of the currents flowing through the first and second variable capacitance capacitors change, causing a resonance phenomenon. Therefore, in order to suppress the overvoltage, which is an object of the present invention, the capacitances of the capacitors constituting the first and second variable capacitance capacitors together with the configuration of FIG. 1 are set to have a relationship of C1> C2 and C3> C4. is necessary.

The voltage of the capacitor C1 finally reaches the maximum value Vm represented by the equation (3) as shown as Vce in FIG. 3, but since Vm is larger than the power supply voltage E, the subsequent IGBT Q1 is turned off. During the steady state period, the capacitor C1 reaches the positive terminal of the power supply E via the diode D2, and is discharged from the negative terminal of the power source via the resistor R1 and the capacitor C2 to return to the capacitor C1.

At the start of the discharging operation, a reverse voltage is applied to the diode Ds1, which causes a reverse recovery of the diode Ds1. And usually, the diode D
An excessive reverse voltage obtained by adding the back electromotive voltage of the wiring to the difference voltage described above is applied to s1, but the capacitor C2 also has an effect of suppressing this reverse voltage. At the same time, the capacitor C
5 is over-charged from the capacitor C5 to the resistor R2.
To the positive electrode of the power supply 1 and from the negative electrode of the power supply 1 to the resistor R
It is discharged on a path returning to the capacitor C5 via the line 1. As a result of this discharge, the voltage Vc5 of the capacitor C5 decreases with time, as expressed by equation (4).

[0043]

(Equation 4)

The voltage of the capacitor C1 is equal to the voltage Vc5 of the capacitor C5 during the discharging process, and the amount of charge ΔQ reduced by the discharging is represented by C1 (Vm−Vc5). Assuming that the value obtained by dividing the charge amount ΔQ by the capacitance of the capacitor C2 is equal to the charging voltage of the capacitor C2, the voltage of the capacitor C2 can be expressed by Equation 5, and the voltage of the polarity Vc2 is applied to the polarity shown in FIG. Is charged.

[0045]

(Equation 5)

FIG. 2B shows a current path when the IGBT Q1 is turned on. In FIG. 2A described above, the current path is such that the capacitor C1 is connected to C3,
To C4, with respect to current and i ₁ to i _6, a i ₂ to i _7, i
Replacing each of ₃ to i _5, the principle is the same briefly described here.

When IGBT Q1 is turned on at time T (On), first, current i ₆ flows through capacitors C4 and C3,
The voltage of the capacitor C4 charged during the off period of FIG. 2A acts as a reverse bias on the diode Ds3.
Therefore, the current i ₆ flows from the diode Ds4 through the capacitors C4 and C3 to the IGBT Q1 and to the negative electrode of the power supply. At this time, the combined capacitance of the second variable capacitance capacitors composed of the capacitors C3 and C4 is expressed by the following equation (2), by replacing the capacitors C1 and C2 with each other.
4 can be described. Current i ₆
Increases the charging voltage for the capacitor C3 and conversely decreases the charging voltage for the capacitor C4.
And, between the collector and the emitter of the IGBT Q2, (V
c3-Vc4) is applied.

Simultaneously with the start of the current i ₆ , the current i ₅ flows through the first variable capacitance capacitor composed of the capacitors C 1 and C 2. This current i ₅ is supplied to the diode Ds4
Flows in the order of capacitors C5, C2 and C1 from the IGBT
It flows on the path returning to the negative electrode of the power supply 1 via Q1. Current i ₅
Discharges the voltage charged in the capacitor C1 when the IGBT Q1 is turned off.
As shown in (1), a voltage having a polarity different from that of the capacitor C1 is charged. In a period in which current i ₅ flows, combined capacitance of the first variable capacitance capacitor, the one represented by the number 2 expression. Then, since the polarities of the voltages Vc1 and Vc2 of the capacitors C1 and C2 constituting the first variable capacitance capacitor are different, a voltage of (Vc1−Vc2) is applied between the collector and the emitter of the IGBT Q1, and eventually Vc1 and Vc2. And are offset. Assuming that both voltages at this time are Vo, Vo can be expressed by equation (6).

[0049]

(Equation 6)

[0050] When the charging voltage Vc4 of the capacitor C4 becomes zero, since the reverse bias is applied to the diode Ds3 is eliminated, the current flowing through the second variable capacitor formed by capacitors C3, C4 is the current from the current i ₆ changes to i _7, current i ₇ is, slide into charging only the capacitor C3 through the diode Ds3. On the other hand, since the voltage applied to the first variable capacitance capacitor constituted by the capacitors C1 and C2 is a value obtained by subtracting the voltage of the capacitor C3 from the voltage of the capacitor C5, the voltage of the first variable capacitance capacitor is zero. to be maintained, and thus the current i ₅ does not flow.

It is an important aim of the present invention to reduce the loss associated with charging / discharging of the variable capacitor in the process of turning off and on the IGBT Q1 described above, and this point will be described below.

From the state in which the voltages of the capacitors C1 and C2 are expressed by the equations (4) and (5), respectively,
Assuming that the loss until the value changes to W, the loss W can be expressed by Expression 7.

[0053]

(Equation 7)

FIGS. 4A and 4B show the results of comparing the loss and the maximum voltage of the snubber circuit used in the first embodiment of the present invention with those of the prior art. ing.
The snubber circuit according to the prior art compared in FIG.
The general configuration is such that a diode and a capacitor are connected in series, and a resistor is provided in parallel with the diode. The capacitance of the capacitor of the snubber circuit of the prior art was set to a value equal to the combined capacitance Co when the capacitors C1 and C2 described in the first embodiment of the present invention were connected in series.

As can be seen from FIG. 4A, the maximum voltage Vm
As for the conventional snubber circuit, the snubber circuit according to the prior art has a form in which (C1 + C5) in the equation (3) in the embodiment of the present invention is replaced with Co. It is larger than in the embodiment of the invention, and the difference between them is proportional to the current IL.

As can be seen from FIG. 4 (b), looking at the loss, according to the present invention, the loss at the time of turn-on of the IGBT Q1 is represented by the following equation (7). Is replaced by Vm. And Vm of the snubber circuit according to the prior art is
It becomes larger than Vm of the present invention. Therefore, the conventional snubber circuit also has a larger loss W, and the difference therebetween is proportional to the square of the load current IL.

As described above, the snubber circuit used in the first embodiment of the present invention can reduce the loss and improve the overvoltage suppressing effect as compared with the snubber circuit according to the prior art.

The snubber circuit used in the first embodiment of the present invention can reduce the loss of the snubber circuit itself, but at the same time, a switching element using a power semiconductor element, that is, the IGBT in the embodiment. The effect of reducing the switching loss can also be achieved, which will be described below.

FIG. 5 shows a waveform at the time of turning off the IGBT Q1 in the first embodiment of the present invention in comparison with the prior art. IGBTs, bipolar transistors, GTOs as power semiconductor elements that are switching elements
It is assumed that a bipolar element (a semiconductor element in which a current flows by two kinds of carriers of electrons and holes) such as a (gate turn-off thyristor) is used. These elements are characterized in that a current called tail current, which is caused by discharging excessively accumulated carriers inside the element, flows after the current is cut off.

FIG. 5 shows a period during which this current flows as a tail period. Voltage fluctuation (dV /
It is known in the field related to power conversion technology that when dt) occurs, the tail current increases as the voltage fluctuation increases. This is, in a nutshell,
Since the voltage determines the speed at which carriers (charges) flow, it can be considered that as the voltage fluctuation increases, more carriers move in a shorter time and more current flows.

In the first embodiment of the present invention having such a structure as shown in FIG. 1, the combined capacitance of the variable capacitors is small during the period in which the current is cut off (before the tail period). Therefore, the voltage fluctuation is large, but in the subsequent tail period, the voltage increase is suppressed by the single capacitance of the capacitor C1 as described above, and the voltage fluctuation can be sufficiently reduced. Therefore, as shown in FIG. 5, in the case of the embodiment of the present invention, the tail current becomes small,
The loss caused by the voltage and the tail current can be reduced. In general, in a power converter having a snubber circuit, about 90% of the loss at the time of turn-off occurs in the tail period. Therefore, as in the embodiment of the present invention, the reduction in the tail current does not correspond to the reduction in the loss. It is valid. Therefore,
The above-described embodiment of the present invention has an effect that the loss of the snubber circuit and the loss of the element during the tail period can be reduced at the same time.

On the other hand, in the case of the prior art, the IGBT
When the capacitance of the capacitor of the individual snubber circuit provided in parallel with Q1 is small, the voltage becomes oscillating as shown in FIG. 5, and the tail current increases due to this effect, resulting in an increase in loss. Of course, it is possible to suppress the voltage oscillation by increasing the capacitance of the capacitor of the individual snubber circuit,
In this case, the loss of the snubber circuit increases in proportion to the capacitance of the capacitor.

In the first embodiment of the present invention, in order to change the capacitance of the snubber circuit, the diodes Ds1 and Ds3 allow the current to flow or cut off according to the charging voltage of the capacitors C2 and C4. That is, the diodes Ds1 and Ds3 are made to function as a kind of switch.

Therefore, in order to obtain the same characteristics as those of the first embodiment of the present invention shown in FIG.
3 is replaced with a switch element having an input / output terminal and a control terminal, and this switch element is connected to capacitors C2 and C2.
4 may be controlled according to the charging voltage.

FIG. 6 is a diagram showing the configuration of such a second embodiment of the present invention. 6, reference numerals 10 and 11 denote control means, S1 and S2 denote switch elements, and other reference numerals are the same as those in FIG. This second embodiment of the present invention
The switching elements S1 and S2 are used instead of the diodes Ds1 and Ds3 in FIG.
1 and S2 are converted to capacitors C by the control means 10 and 11.
2. Control is performed according to the charging voltage of C4.

That is, in the second embodiment of the present invention shown in FIG. 6, the input of the switch element S1 is located at the position of the diode Ds1 in the first embodiment of the present invention described with reference to FIG.
In addition to connecting the output terminal, the control unit 10 detects the charging voltage of the capacitor C2, and applies a signal for turning on the switch element S1 to the control terminal when the voltage is equal to or lower than a predetermined value. Similarly, the input and output terminals of the switch element S2 are connected to the position of the diode Ds3, and the control unit 11 detects the charging voltage of the capacitor C4, and turns on the switch element S2 when the voltage is equal to or lower than a predetermined value. Is applied to its control terminal.

Although the second embodiment of the present invention uses npn transistors as the switching elements S1 and S2, the switching elements S1 and S2 can satisfy the following conditions. Any other element may be used as long as it is a switch means. That is, (1)
The switch elements S1 and S2 allow current to flow in the same direction as the diodes Ds2 and Ds4 connected in parallel, respectively. (2) No current flows in the direction opposite to the current direction. (3) The switch elements S1 and S2 are:
Each of the input terminals (in the case of FIG. 6,
A high voltage is applied to the output terminal (emitters of S1 and S2 in FIG. 6) using the collectors of S1 and S2 as a reference potential, which is the opposite of a normal semiconductor device and can withstand this reverse voltage. thing.

In consideration of the above three conditions, the switching elements S1 and S2 cannot use a single element such as a MOSFET having a parasitic diode between input and output terminals. The switch elements S1 and S2 formed by the npn transistors shown in FIG. 6 satisfy the conditions (1) and (2). However, in order to satisfy the condition (3), the resistance between the base and the emitter is reduced. An element with increased voltage characteristics is required.

In the second embodiment of the present invention shown in FIG. 6, the control means 10 and 11
2, the charging voltage of C4 is detected, and if this voltage is 0 V or less in the polarity shown in FIG. 6, the switching elements S1 and S2 are turned on. Conversely, if the voltage is 0 V or more, S1 and S2 are detected.
Turn 2 off.

The characteristics of the second embodiment of the present invention shown in FIG. 6 are the same as those of the first embodiment of the present invention shown in FIG. 1, and the switching element S1 is switched in accordance with the voltages of the capacitors C2 and C4. , S2, by turning off and on, the IGBT
The capacitance of the snubber capacitor with respect to Q1 and Q2 can be changed equivalently. According to the second embodiment of the present invention, it is possible to obtain exactly the same effects as those of the first embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a power converter according to a third embodiment of the present invention, and is a system configuration example of motor control. 7, 3 is a snubber circuit, 4 is a drive circuit, 5 is a control circuit, 6 is a current detector, 7 is an AC power supply, 9 is a converter, Q3 to Q6 are IGBTs, and D3 to D3.
Reference numeral 6 denotes a diode, and other symbols are the same as those in FIG.

A power converter according to a third embodiment of the present invention shown in FIG. 7 is an inverter device for controlling a motor as a load 2, and receives power supplied from an AC power supply 7 to rectify AC to DC. DC power smoothed by a capacitor built in the converter 9 is applied. And
The inverter device is configured by providing the inverter shown in FIG. 1 for each of the U-phase to W-phase for one phase in parallel for three phases.

The configuration of the U phase is the same as that of FIG. The V phase has an upper arm composed of an IGBT Q4 and a diode D4 connected in parallel with the IGBT Q4.
And a diode D3 connected in parallel to the IGBTQ6. Similarly, the W phase has an upper arm formed by an IGBT Q6 and a diode D6 connected in parallel thereto, and a lower arm formed by a diode D6 connected in parallel to the IGBT Q5. D
And 5. The snubber circuit 3 surrounded by a dashed line in the U phase is the entire configuration of the snubber circuit for the upper arm and the lower arm shown in FIG. 1, and the snubber circuit 3 having the same configuration is divided into a V phase and a W phase. Are also provided. Then, electric power is supplied to the motor as the load 2 from an output terminal which is a connection point between the upper arm and the lower arm of each of the U, V, and W phase inverters.

As a configuration on the control side of the inverter device, a control circuit 5 and a drive circuit 4 are provided, and the control circuit 5 receives an input speed command 8 and a current detector 6 for detecting an output current of each phase. The driving circuit 4 generates a signal for turning on or off the IGBTs of the upper arm and the lower arm of each phase based on the signals of And the motor as the load 2 is controlled.

As described above, the power converter according to the third embodiment of the present invention can suppress the overvoltage and reduce the loss by the effect of the variable capacitor of the snubber circuit. The effect that the controllability can be improved when is small,
In addition, since the oscillation of the voltage is suppressed, noise that adversely affects the current detector 6 can be reduced.

In the following, a description will be given of the reduction of noise that adversely affects the current detector 6.

That is, in FIG. 7, a stray capacitor exists between the windings of the motor which is the load 2, and
When the output voltages of the U-phase to W-phase fluctuate, a high-frequency leakage current flows through the stray capacitor, and this leakage current may affect the current detector 6. In the case of the embodiment of the present invention, as described with reference to FIG. 2, since the voltage oscillation of the IGBT Q1 (equal to the fluctuation of the U-phase output voltage) can be suppressed, the above-described high-frequency leakage current can be reduced. It is.

The power converter according to the third embodiment of the present invention shown in FIG. 7 is also effective in stabilizing the control operation of the motor. That is, the cause of the noise is, in addition to the high-frequency leakage current flowing through the stray capacitor between the motor windings described above, a noise current related to a stray capacitance between the ground,
There are various factors, most of which are sudden voltage changes (dV
/ Dt), even when the voltage oscillates and dV / dt increases when using the snubber circuit according to the related art, the power converter according to the embodiment of the present invention can perform the voltage oscillation and Since dV / dt can be suppressed, noise can be reduced, and the control operation of the motor can be stabilized.

The above-described power converter according to the third embodiment of the present invention is configured by providing the inverter shown in FIG. 1 for each of the U-phase to W-phase three phases in parallel. However, the same configuration can be obtained by using the embodiment shown in FIG. 6, and the same effect can be obtained.

FIG. 8 is a diagram illustrating the configuration of a power converter according to a fourth embodiment of the present invention. This embodiment is shown in FIG.
This is an example in which the configuration of the variable capacitor in the third embodiment of the present invention described above is changed, and FIG. 7 only shows a portion related to the first variable capacitor of the snubber circuit 3 in FIG. However, the variable capacitance capacitors for all other IGBTs are similarly configured.

In the fourth embodiment of the present invention shown in FIG. 8, a switch element S is provided between a capacitor C1 and a diode Ds1.
The control circuit 5 controls the switch element S3 to be turned on or off based on the detection result of the load current by the current detector 6. That is, this embodiment is characterized in that the switch element S3 is controlled to be turned off when the load current to the motor is smaller than a preset value. With the switch element S3 turned off, the combined capacitance of the first variable capacitance capacitors constituted by the capacitors C1 and C2 is fixed to a value represented by Expression 2 regardless of the bias state of the diode Ds1. When the switch element S3 is in the ON state, the operation described in the description of FIG. 2 is performed.

When the motor is driven, the current supplied to the motor is a sinusoidal current whose phase is shifted by 120 degrees for each phase. Further, since the electromagnetic energy of the wiring is proportional to the square of the current as expressed by Equation 1, when the current is small, it is better to reduce the capacitance of the snubber circuit within the allowable range of the IGBT as the switching element. It is desirable from the viewpoint of reduction of the charging time and the charging time of the snubber circuit.

In the embodiment described with reference to FIG. 1, the condition under which the capacity of the variable capacitor is switched from the capacity expressed by the equation (2) to the capacity of the capacitor C1 alone is that the voltage of the capacitor C2 expressed by the equation (6) becomes zero. It is becoming. Since the equation (6) depends on the equation (3), the switching of the capacitance also indirectly depends on the load current in the embodiment shown in FIG. An attempt to make the indirect capacitance change with respect to the load current a direct relationship is shown in FIG.
This is an embodiment of the invention.

In the fourth embodiment of the present invention, the period during which the switching element S3 is turned off is a period during which the current in each cycle of the sine wave current to the load 2 is smaller than a preset value. When the peak value of the sine wave current for 2 is smaller than a preset value, the switch element S3 is always turned off.

According to the above-described fourth embodiment of the present invention,
When the current is small, the capacity is represented by the equation (2), and when the current is large, the capacity is variable.

[0086]

As described above, according to the present invention, it is possible to reduce the overvoltage on the power semiconductor element as the switching element, and reduce the loss of the snubber circuit and the switching loss of the power semiconductor element. In addition, it is possible to suppress voltage fluctuations, reduce noise affecting a device serving as a load, and stabilize the operation of the device.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration example of a power converter according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a current path for explaining the operation of the first embodiment of the present invention.

FIG. 3 is a waveform chart for explaining the operation of the first embodiment of the present invention.

FIG. 4 is a diagram for explaining the loss and the maximum voltage of the snubber circuit used in the first embodiment of the present invention in comparison with the prior art.

FIG. 5 is a diagram illustrating a turn-off waveform of a switching element according to the first embodiment of the present invention in comparison with a conventional technique.

FIG. 6 is a diagram showing the configuration of such a second embodiment of the present invention.

FIG. 7 is a diagram showing a configuration example of a power converter according to a third embodiment of the present invention.

FIG. 8 is a diagram illustrating a configuration of a power conversion device according to a fourth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 power supply 2 load 3 snubber circuit for one phase 4 drive circuit 5 control circuit 6 current detection means 7 AC power supply 9 converter 10, 11 control means Q1 to Q6 IGBT D1 to D6 diode Ds1 to Ds4 snubber diode C1 to C4 snubber capacitor C5 Clamp capacitors R1, R2 Resistance S1 to S3 Switch element

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H03K 17/16 H03K 17/16 M (72) Inventor Shigeru Sugiyama 5-2-1 Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi, Ltd. In the Omika factory (56) References JP-A-7-213076 (JP, A) JP-A-7-87726 (JP, A) JP-A-5-122946 (JP, A) JP-A-5-260758 (JP, A A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H02M 7/48 H02M 1/00 H02M 1/06 H02M 7/5387 H03K 17/16

Claims (7)

(57) [Claims] A first switching element connected in series between terminals of a main power supply, wherein the two switching elements are controlled in accordance with a command from a control means, so that the two switching elements are switched. In a power converter for supplying power to a load from a connection point of elements, a first power conversion apparatus connected between input and output terminals of each of the two switching elements.
A second snubber capacitor for connecting each of the second capacitors to each of the switching elements; and when the switching element is turned on, a second snubber capacitor is provided from the first capacitor corresponding to the element. And supplying the energy to the capacitors to cancel the charging voltages of both capacitors applied to the switching element. When the switching element is turned off, the voltage of the element is equal to or less than a predetermined value, and the first, Second
The voltage applied to the switching element is suppressed by the series combined capacitance of the two capacitors and by the single capacitance of the first capacitor corresponding to the element when the voltage of the element is equal to or higher than a predetermined value. Conversion device. 2. A semiconductor device comprising: a first switching element connected in series between terminals of a main power supply; and a second switching element, wherein the two switching elements are controlled in accordance with a command from a control means. In a power converter for supplying power to a load from a connection point of elements, a circuit means in which a first diode and a first capacitor connected between respective input / output terminals of the two switching elements are connected in series; A resistor and a second capacitor connected in parallel to each of the first diodes, and a second diode passing a current in the same direction as the first diode is connected in parallel to the resistor. A power converter, comprising: a circuit means provided in the power supply device; and a clamp snubber capacitor for connecting connection points between the resistor and the second capacitor. 3. A switching device comprising: a first and a second switching element connected in series between terminals of a main power supply; and controlling the two switching elements in accordance with a command from a control means. A power converter for supplying power to a load from a connection point of elements, a circuit means in which switch means connected between respective input / output terminals of the two switching elements and a first capacitor are connected in series; Circuit means in which a resistor and a second capacitor are connected in series to each of the switch means, and a diode for passing a current in the same direction as the switch means is provided in parallel with the resistor; And a clamping snubber capacitor for connecting a connection point between the second capacitor and a second capacitor, wherein the switch is provided in accordance with a voltage charged in the second capacitor. A power converter for turning off or on the switching means. 4. A switching device comprising: a first and a second switching element connected in series between terminals of a main power supply; and controlling the two switching elements in accordance with a command from a control means, thereby controlling the two switching elements. In a power converter for supplying power to a load from a connection point of elements, a first diode, a switch, and a first capacitor connected between input and output terminals of the two switching elements are connected in series. A circuit means, a resistor and a second capacitor connected in parallel to each of the series circuit sections of the first diode and the switch means are connected in series, and a current flows in the same direction as the first diode. Circuit means for providing a second diode to be connected in parallel with the resistor, and a snubber capacitor for clamping for connecting the second capacitors to each other. Is turned off when a load current to the load is smaller than a preset current value. 5. The power conversion device according to claim 1, wherein a capacitance value of said second capacitor is set smaller than a capacitance value of said first capacitor. 6. The power converter according to claim 1, wherein the capacitance value of the clamp snubber capacitor is set to be larger than the capacitance values of the first and second capacitors. apparatus. 7. A method comprising: providing a plurality of phases of first and second switching elements connected in series as one phase between terminals of a main power supply, and controlling the switching elements in accordance with a command from a control means. Thus, in a power converter for supplying power to a load from a connection point of two switching elements of each phase, the power converter according to any one of claims 1 to 6 is used for one phase. Power converter.