JP3272529B2 - Method of forming recess gate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a recess gate, and more particularly to a method of forming a recess gate of a field effect transistor (FET) having a recess structure.

[0002]

2. Description of the Related Art Heretofore, as a method of forming this kind of recess gate, a method of forming a HEMT type recess gate by the inventor of the present application is disclosed in Japanese Patent Application No. 3-184939.
Is disclosed.

[0003] The HEMT disclosed in this document will be described below.
A method for forming a mold recess gate will be briefly described.

According to this document, first, an MB is placed on a substrate.
An AlGaAs layer and an n ⁺ -GaAs layer are sequentially stacked by using the E method.

Next, a plasma CV is formed on the n ⁺ -GaAs layer.
A recess forming mask layer (also referred to as a SiN film) is formed by the method D. After that, a reverse-tapered resist pattern having an opening is formed on the SiN film. Subsequently, anisotropic etching is performed in the direction of the substrate surface from above the opening of the resist pattern to remove a part of the SiN film and form a recess mask layer. Thereafter, wet etching is performed using this recess mask layer as a mask to form n ⁺
Forming a recess in the GaAs layer; At this time, the depth of the recess is determined by n ⁺ -GaAs coupled to the recess mask layer.
The distance from the coupling surface of the s layer to the surface where the upper surface of the AlGaAs layer is exposed.

Next, a gate metal is deposited from an oblique direction on the drain electrode side toward the source electrode side at an incident angle of about 10 degrees with respect to the normal to the substrate surface, and the bottom of the recess is formed.
That is, the gate electrode is formed over the upper surface of the AlGaAs layer and a part of the recess side wall surface on the source electrode side. Thus, the gate electrode and the source electrode are formed close to each other, and the gate electrode and the drain are formed separately from each other. Therefore, minute gate electrode is closer to the source electrode side, the source resistance R _s is reduced, thus increasing the transconductance g _m.

[0007]

However, in the method of forming a recess gate disclosed in the above-mentioned conventional literature, when it is desired to increase the drain breakdown voltage between the gate electrode and the drain electrode, the conventional method of forming a recess gate is as follows. There was a problem as described above.

[0008] the recess width (and where the recess width, with respect to the longitudinal direction of the recess, orthogonal width, namely refers to the width in the channel direction.) In order to increase the parasitic resistance R _d of the drain side wide Then, the surface depletion layer of the AlGaAs layer becomes large, the ratio of the surface depletion layer occupying in the channel increases, and the channel region becomes narrow. As a result, the parasitic resistance, in particular, the source resistance R _S increases, so that the FE
Transconductance g _m of the T element is reduced.

When the thickness of the n ⁺ -GaAs layer is increased, when a recess is formed in the n ⁺ -GaAs layer by isotropic etching, a mask film (SiN film) is formed on the n ⁺ -GaAs layer. ), The etching proceeds uniformly in the depth direction of the recess and in the width direction of the recess. Therefore, the side etching proceeds in the direction of the recess width as much as the recess depth is increased, and it is difficult to control the recess width as designed.

Therefore, there has been a demand for an excellent recess gate forming method capable of increasing the drain withstand voltage without deteriorating the electrical characteristics of the FET element.

[0011]

According to the method for forming a recess gate of the present invention, first, an impurity-doped first semiconductor layer and a second semiconductor layer having a higher impurity concentration than the first semiconductor layer are formed on a substrate. And a mask layer (SiN film) are sequentially formed.

Further, a resist pattern having an opening with a large tendency and a side with an opening having a small tendency and having an opening with a reverse tapered cross section is formed on the mask layer.

Subsequently, anisotropic etching is performed on the substrate side from above the opening of the resist pattern by using a dry etching method, and the mask layer is partially removed to form a recess mask layer. Using the recess mask layer as a mask, the second semiconductor layer is etched to form a first recess in the second semiconductor layer. After that, at least the exposed portion of the recess mask layer on the side surface of the opening where the tendency is large is removed by etching to expose a portion of the second semiconductor layer.

Thereafter, using the remaining recess mask layer as a mask, at least an exposed portion of the second semiconductor layer is etched to the upper surface of the first semiconductor layer to form a second recess including a deep recess and a shallow recess. I do.

[0015]

According to the present invention described above, a first semiconductor layer is formed on a substrate,
After sequentially stacking the second semiconductor layer and the mask layer, a resist pattern having an inversely tapered opening having a different opening tendency is formed on the mask layer. Anisotropic etching is performed on the substrate side from above the opening to remove a part of the mask layer to form a recess mask layer. At this time, a recess mask layer in which a part of the recess forming mask layer is removed is formed by a dimension substantially equal to the dimension of the opening of the resist pattern. Therefore, a recess mask layer having an exposed surface that is not bonded to the resist pattern is formed on the bottom surface of the resist pattern, which has a large tendency to have a side surface of the opening. Thereafter, using the recess mask layer as a mask, the second semiconductor layer is etched to form a first recess in the second semiconductor layer.

Subsequently, the portion of the recess mask layer exposed below the opening is removed by using a suitable etching method. At this time, since the recess mask layer exposed below the opening is removed, an exposed surface portion of the second semiconductor layer appears (to be described in detail later).

Further, by using the recess mask layer remaining on the lower surface of the resist pattern as a mask, the exposed part of the second semiconductor layer is etched to the upper surface of the first semiconductor layer to form a deep recess and a shallow recess. Form a second recess. At this time, the deep recess is formed on the same side as the first recess and in the first semiconductor layer, while the shallow recess is formed on the side surface of the opening having a large tendency and formed in the second semiconductor layer. Formed. As described above, when the second recess is formed, the wet etching method is used as in the case of the first recess, so that the bottom region of the shallow recess is a region where a part of the second semiconductor layer before being etched is exposed. It can be formed in the shape of substantially the same region (details will be described later). For this reason, since the length from the upper edge of the source side of the deep recess of the second recess to the upper edge of the drain side of the shallow recess of the second recess is determined, a gate is formed on the bottom surface of the deep recess of the second recess in a later step. When electrodes are provided, the distance between the gate electrode and the drain electrode also becomes a predetermined length. For this reason,
Since the shallow recess is provided between the gate electrode and the drain electrode, the gate electrode and the drain electrode can be separated from each other, so that the electric field between the gate electrode and the drain electrode is reduced, and thus the breakdown voltage between the gate and the drain electrode is increased. can do.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming a recess gate according to the present invention will be described below with reference to the drawings.
emiconducer Field Effect
A description will be given by taking as an example the formation of a gate (Transistor). It should be noted that each figure merely schematically shows the shape, size, and arrangement of each component so that the present invention can be understood.

1A to 1D and FIGS. 2A to 2D.
(D) is a process drawing for explaining the formation process of the first embodiment of the present invention.

First, in the first embodiment of the present invention, a substrate 13 having a GaAs buffer layer 12 formed on a GaAs substrate 10 is used. Then, using a MBE method, an impurity-doped first semiconductor layer (hereinafter referred to as an n-GaAs layer) 14 and an n-GaAs layer are formed on the substrate 13.
A second semiconductor layer having a higher impurity concentration than the layer 14 (hereinafter, referred to as a second semiconductor layer)
It is called an n ⁺ -GaAs layer. ) 16 are sequentially formed. At this time, the thickness of each layer is set to, for example, 1500 ° for the n-GaAs layer 14 and 10 for the n ⁺ -GaAs layer 16, for example.
00 °.

Next, a source electrode and a drain electrode, which are ohmic electrodes, are formed on the n ⁺ -GaAs layer 16 by, for example, photolithography (not shown). Thereafter, a mask layer (hereinafter, referred to as an SiN film) 20 for forming a recess is formed on the upper surface of the structure including the source electrode and the drain electrode by using, for example, a plasma CVD method. At this time, the thickness of the SiN film 20 is set to about 1000 °. The reason for using this SiN film 20 is that R
This is because IE enables selective etching with GaAs and isotropic selective etching using buffered hydrofluoric acid (details will be described later).

Next, using a well-known phase shift technique (for example, JP-A-3-85543), an opening side wall surface 22a having a large tendency and an opening side wall surface 22b having a small tendency are used.
A resist pattern 22 having an opening 23 having a reverse tapered cross section is formed, and a structure shown in FIG. 1A is obtained. In addition, this cut is perpendicular to the substrate surface,
In addition, they are in a plane along the channel direction of a transistor that can be formed. The material of the resist pattern 22 used at this time is preferably a negative resist, for example, FSMR resist manufactured by Fuji Pharmaceutical Co., Ltd. The resist pattern 22 has a thickness of about 0.7 μm (7000 °).
And Also, the distance or length in the channel direction between opposing edges of the opening 23 of the resist pattern 22 is represented by H.

Next, using the resist pattern 22 as a mask, anisotropic etching is performed in a direction perpendicular to the substrate surface by a reactive etching method (RIE method) to remove a part of the SiN film 20. Thus, the structure shown in FIG. 1B is obtained. At this time, sulfur hexafluoride (SF ₆ ) and carbon tetrafluoride (CF ₄ ) are used as etching species for RIE.
Alternatively, another ion species may be used. The dimension of the portion of the SiN film 20 removed by this etching is substantially the same as the length H of the opening 23 of the resist pattern 22. Here, the SiN film 20 formed at this time is referred to as recess mask layers 20a and 20b.

Next, using the recess mask layers 20a and 20b as a mask, the n ⁺ -GaAs layer 16 is etched by any suitable wet etching (isotropic etching) so that the n ⁺ -GaAs layer 16 One recess 24 is formed to obtain the structure shown in FIG. At this time, between the end face edge of the first recess 24 formed, the distance or length of the channel direction and M _1. As is well known, in the isotropic etching, the depth direction and the lateral direction of the n ⁺ -GaAs layer 16 are etched at the same ratio. At this time, when the etching reaches the vicinity of the opening edge of the recess mask layers 20a and 20b, the etching is finished. At this time, the etching depth may be a depth of the n ⁺ -GaAs layer 16 or a depth reaching a part of the n-GaAs layer 14 thereunder. The etching conditions at this time are, for example, a phosphoric acid-hydrogen peroxide solution as an etchant solution, and the etching immersion time is, for example, about 2 minutes.

Next, using the resist pattern 22 as a mask, of the exposed portions of the recess mask layers 20a and 20b, at least the portion 20b of the recess mask layer on the side of the opening side 22a where the resist pattern tends to be large is removed by etching. Then, a part 2 of the n ⁺ -GaAs layer 16 is formed.
5 is exposed (FIG. 1D). The etching is completed when the etching reaches the bottom surface of the n ⁺ -GaAs layer 16b on the side of the opening side 22a, which has a large tendency, using buffered hydrofluoric acid as an etching solution. At this time, the remaining recess mask layers are 20c and 20d. By such etching, the opening side surface 2 having a small tendency is formed.
From the upper edge of the first recess 24 on the lower surface of the recess mask layer 20c on the 2b side, the recess mask layer 20 on the lower surface of the recess mask layer 20d on the side surface 22a of the opening 22a having a greater tendency.
The distance or length L _{1 in the} channel direction up to the open end of d.
Is determined. Here, the upper surface of the channel direction of a portion 25 of the n ⁺ -GaAs layer 16b the length and M _2.

Next, the remaining recess mask layer 20c
And 20d as a mask, at least n ⁺ -G
The exposed portions 25 of the aAs layers 16a and 16b are
Etching is performed to the upper surface of the GaAs layer 14 to form a second recess 26 including a deep recess 26a and a shallow recess 26b.
Is formed to obtain the structure shown in FIG. In the etching at this time, the same etchant liquid as used in the formation of the first recess is used, and the etching immersion time is set to, for example, about 1 hour.
5 seconds. The second recess 26 thus formed
Indicates the direction of the bottom surface of the first recess 24 and the n ⁺ -GaAs layer 16.
Since the exposed portion 25 of b is etched at the same ratio, the second recess 26 having a two-stage structure including the deep recess 26a and the shallow recess 26b is formed. At this time, n ⁺ -G
length M ₂ of the exposed portions 25 of the aAs layer 16b is, since substantially the same as the length of the shallow recess 26b, the upper edge of the deep recess 26a in the lower surface of the small opening side surface 22b side of the Risesumasuku layer 20c of-out tendency , it determines the length L ₂ to the upper edge of the shallow recess 26b on the underside of the Risesumasuku layer 20d of a large open side 22a side-out tendency. In the embodiment of the present invention, the thickness of the n ⁺ -GaAs layer 16 is set to about 1
Since the length is set to 000 °, the length L ₁ of the structure shown in FIG. 1D and the length L ₂ of the structure shown in FIG. 2A can be made substantially the same.

Next, a gate metal for forming a gate electrode is deposited on the substrate side from above the resist pattern 22 by using an evaporation method to form a gate metal layer 18a and a gate electrode 18b (FIG. 2). (B)). Here, titanium (Ti) and aluminum (Al) are used as gate metal materials.
And the structure of the gate electrode is preferably Ti
It is preferable to have a double structure in which Al is deposited thereon.

Next, the gate metal layer 18a on the resist pattern 22 is lifted off by using any suitable organic solvent (FIG. 2C), and thereafter, the remaining SiN film is formed by plasma etching. The gate electrode 18b is formed by removing 20c and 20d (FIG. 2D).
Through the steps described above, the MESFET of the present invention is completed.

The MESFET formed by the steps as in this embodiment has a deep recess 26a on the gate electrode side and a continuous shallow recess 26b on the drain electrode side. At this time, the surface depletion layer on the drain side
The gate electrode 18b is formed on both the surface of the deep recess 26a and the surface of the shallow recess 26b on the drain side of the gate electrode 18b. g
_m )). In an embodiment of the present invention, a deep recess is formed on the gate electrode side, and since the recess length M ₁ with respect to the gate length is also are shortened, thereby reducing the area of the surface depletion layer. Therefore, since the ratio to the channel generated by the operation of the MESFET can be reduced,
A decrease in mutual conductance g _m can be minimized.

On the other hand, a shallow recess 26b is formed on the drain side.
Is formed, the gate electrode 18b and n ⁺ -Ga
Since the As layer 16d can be separated, the gate electrode 18b
The electric field between the gate electrode and the drain electrode can be reduced. Therefore, the drain breakdown voltage increases.

Next, a second embodiment of the present invention will be described with reference to the sectional view of FIG.

The second embodiment of the present invention relates to a first recess 24
Since the steps up to the formation of are the same as in the first embodiment, a detailed description of the steps will be omitted.

Using the structure in which the first recess 24 is formed (see FIG. 1C), the opening side surface 22b having a small tendency is used.
Anisotropic etching is performed obliquely from above the resist pattern on the side with respect to the direction of the recess mask layer 20b on the side of the opening side 22a where the tendency is large, and the resist pattern 22 on the side of the opening side 22a where the tendency is large is formed. Only a part of the recess mask layer 20b on the bottom is removed by etching (FIG. 3). Subsequent steps are shown in FIG. 2A of the first embodiment.
Since these steps are the same as steps (D) to (D), detailed description of the steps is omitted.

In the second embodiment of the present invention, only the recess mask layer 20b on the bottom of the resist pattern on the opening side 22a (drain electrode side) where the tendency is high is removed by etching, and the opening side 22b having a low tendency is removed. The recess mask layer 20c on the bottom surface of the resist pattern 22 (on the source electrode side) is not etched. Therefore, the second recess is deeply recessed by isotropic etching in the post-treatment.
6a and the shallow recess 26b, the distance between the gate electrode and the source electrode can be reduced because the over-etching to the source electrode side is small. Therefore, the parasitic resistance, i.e. the smaller the source resistance R _s, is advantageous in that the mutual conductance g _m can be increased. Also,
In the second embodiment, as in the first embodiment, the shallow recess 26b
Since the gate electrode and the drain electrode are separated from each other, the breakdown voltage between the gate and the drain is improved.

In the first and second embodiments, the SiN layer is used as the recess mask layer 20. However, the present invention is not limited to this material.
i) A layer may be used.

In the first embodiment, the MESFET
Has been described, the BP-MESFET (Buried P-Layer) is used, for example.
rMESFET) or HEMT (High Ele)
ctron Mobility Transistor
).

[0037]

As is apparent from the above description, according to the method of forming a recess gate of the present invention, a deep recess is formed in a first semiconductor formed on a substrate, and a shallow recess is formed in a second semiconductor layer. Are formed continuously. For this reason,
When the gate electrode is formed in the deep recess, the surface depletion layer on the drain side becomes small because it depends on the bottom and side surfaces of the deep recess. For this reason, the surface depletion layer on the drain side can be controlled by the length direction of the bottom and side surfaces of the deep recess from the gate electrode, so that the mutual conductance g
_m can be set to a predetermined value without decreasing.

On the other hand, since a shallow recess is formed on the drain electrode side to separate the gate electrode from the second semiconductor layer, the electric field between the gate electrode and the drain electrode is reduced.
Therefore, the breakdown voltage between the gate electrode and the drain electrode also increases.

Further, as a method of etching a part of the recess mask layer, an anisotropic oblique direction from above the resist pattern on the side surface of the opening with a small tendency to the direction of the recess mask layer on the side surface of the opening with a large tendency. Etching is performed to remove only a part of the recess mask layer. At this time, since the recess mask layer on the source electrode side is not etched by the oblique anisotropic etching, over-etching on the source electrode side caused by isotropic etching when forming the second recess can be reduced. Therefore,
Parasitic resistance between the source electrode and the gate electrode, i.e., the source resistance R _s is reduced, the transconductance g _m is increased, thereby improving the electrical characteristics of the MESFET.

[Brief description of the drawings]

FIGS. 1A to 1D are process diagrams provided for explaining a first embodiment of the present invention.

2 (A) to 2 (D) are process diagrams provided for explaining a post-process of FIG. 1;

FIG. 3 is a process chart provided for explaining a second embodiment of the present invention.

[Explanation of symbols]

10: GaAs substrate 12: GaAs buffer layer 13: Substrate 14, 14a: n-GaAs layer 16, 16a, 16b, 16c, 16d: n ⁺ -GaAs
s layer 18a: Gate metal layer 18b: Gate electrode 20: Mask layer 20a, 20b, 20c, 20d: Recess mask layer 22: Resist pattern 22a: Open side with high tendency 22b: Open side with low tendency 23: Opening 24 : First recess 25: Exposed portion of n ⁺ -GaAs layer 26: Second recess 26a: Deep recess 26b: Shallow recess

Claims (3)

(57) [Claims] (A) a step of sequentially forming, on a substrate, a first semiconductor layer doped with impurities, a second semiconductor layer having a higher impurity concentration than the first semiconductor layer, and a mask layer; and (b) the mask Forming a resist pattern on the layer having an opening side with a large tendency and an opening side with a small tendency, and having a cross-sectional cut surface having an opening of a reverse taper type; and (c) using a dry etching method. Anisotropically etching the substrate side from above the opening of the resist pattern to partially remove the mask layer to form a recess mask layer; and (d) masking the recess mask layer. Forming a first recess in the second semiconductor layer by etching the second semiconductor layer; and (e) at least the portion of the exposed portion of the recess mask layer where the tendency is large. Opening A step of etching and removing a part on the side surface to expose a part of the second semiconductor layer;
(F) using the recess mask layer remaining in the step (e) as a mask, etching at least an exposed part of the second semiconductor layer to the upper surface of the first semiconductor layer;
A method of forming a recess gate, comprising: forming a second recess including a deep recess and a shallow recess. 2. The method according to claim 1, wherein the depth of the first recess formed in the second semiconductor layer according to the step (d) is reduced by exposing the second semiconductor layer. A method for forming a recess gate, comprising: extending from an upper surface of a portion to an exposed surface of the first semiconductor layer. 3. The method of forming a recess gate according to claim 1, wherein the etching of a part of the recess mask layer in the step (e) is performed from above the resist pattern on a side surface of the opening having a small tendency. A method of forming a recess gate, wherein anisotropic etching is performed in an oblique direction with respect to a direction of the recess mask layer on the side surface of the opening where the tendency is large.