JP3269162B2 - Electroluminescence display panel drive circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a drive circuit for an electroluminescence (EL) display panel, and more particularly to a low power consumption type drive circuit including a level shift circuit and suitable for integration in a semiconductor chip.

[0002]

2. Description of the Related Art A semiconductor integrated circuit (IC) chip constituting an EL display panel driving circuit receives a data input to be displayed with an image at a low voltage logic level and receives the data input sufficiently to drive an EL display element. And a voltage level shift circuit for converting the output signal into an output signal having a high logic level. EL
The threshold voltage required for starting light emission of the display panel is several hundred volts, and it is difficult to realize a driving circuit of the EL display panel with an IC using a normal IC manufacturing technique. Therefore, a high withstand voltage output circuit for generating such a high voltage EL element drive pulse and a normal low voltage logic level data input are handled.
An interface means between the control logic circuit and the V power supply system is required. This high withstand voltage output circuit generally includes a push-pull output circuit including a switch element necessary for charging a display element forming the load and a switch element for discharging. This type of high withstand voltage output circuit is described in Japanese Patent Application Laid-Open No. Hei 2-103092. The high withstand voltage driving circuit exemplified in this publication discloses a first circuit to which a high voltage is supplied.
A second power supply terminal to which a ground voltage or a negative high voltage is supplied, a low-voltage power supply terminal to which a low voltage of 5 volts is supplied, an input terminal for receiving an external input signal,
An output terminal connected to the L display element, a logic circuit for controlling ON / OFF of the buffer circuit in response to an input signal supplied to the input terminal, and an output unit in response to a control signal supplied from the logic circuit. It has a buffer circuit for controlling ON / OFF and an output section for supplying a current to the EL display element and absorbing a discharge current from the EL display element. This output section includes a thyristor having an anode connected to a first power supply terminal and a cathode connected to an output terminal, a diode having a cathode connected to the cathode / gate of the thyristor and an anode connected to the cathode of the thyristor, and a collector for the thyristor. Comprises an npn transistor whose thyristor has its cathode and gate connected to its second power supply terminal via its low-voltage switching element. Also, np
The base of the n transistor is a PMOS in the buffer circuit.
The PMOS transistor has a configuration in which it is connected to the drain of the transistor and the source of the PMOS transistor is connected to the low-voltage power supply terminal.

According to the configuration described in the above publication, the number of circuit elements and current consumption can be reduced, but the power consumption in the non-driving state is large and the manufacturing process is complicated. An example of this type of EL panel driving circuit having a CMOS structure whose manufacturing process is simplified is NEC Corp., the assignee of the present application.
The data is described in page 409 of the data book “Display Controller / Driver IC” issued on May 10, 1989. The drive circuit disclosed in this publication includes first and second power supply terminals, first and second ground terminals, an internal logic circuit, and an output circuit.
And a high voltage from the second power supply terminal to the output circuit, and the output of the internal logic circuit is supplied to the output circuit. Although not shown in the above publication, this output circuit has a level shift circuit for converting a low-voltage logic level output from the internal logic circuit to a high-voltage logic level output. Each ground wiring is commonly connected to a ground terminal. In this drive circuit, when the output circuit is driven, the current flowing from the high voltage power supply side to the ground line via the output circuit is the ground potential (0 level).
Is varied. Further, even if the ground lines of the logic circuit and the output circuit are provided independently of each other, if the ground potential of the output circuit drops below the ground potential of the internal logic circuit, the transistors constituting the level shift circuit are completely turned off. Does not enter the state. As a result, a through current flows from the high-voltage power supply to the ground terminal. As a result, the operation speed of the level shift circuit is reduced, which further causes malfunction.

Referring to FIGS. 4 and 5, the EL display panel driving circuit 1 according to the prior art shown in FIGS.
The circuit includes an internal logic circuit 2, output stages 101 to 140, an input terminal 3, a first power supply terminal 4, a second power supply terminal 5, a ground terminal 6, and high voltage output terminals 401 to 440.
The output stage 101 includes an inverter INV, a first level shift circuit 10, and an output transistor P having a push-pull configuration.
103 and N103. Level shift circuit 1
0 includes a series connection circuit of transistors P101 and N101 and a series connection circuit of transistors P102 and N102 connected in parallel between the second power supply terminal 50 and the ground terminal 60. The gate electrode of transistor P101 is connected to a connection point c between transistors P102 and N102, and the gate electrode of transistor P101 is connected to a connection point d between transistors P101 and N101.

The input terminal 30 is the input terminal of the inverter INV and the gate electrode of the transistor N102, the output terminal of the inverter INV is the gate electrode of the transistor N101 and the gate electrode of the output transistor N103, and the connection point c between the transistors P102 and N102 is the output. Each is connected to a gate electrode of the transistor P103. Further, a first power supply terminal 40 is connected to the inverter INV.
From the second power supply terminal 50 to the level shift circuit 10 and the output transistor P103.
From the power supply voltage VDD2. The source electrodes of the transistors N101, N102 and N103 and the ground terminal of the inverter INV are commonly connected to a ground terminal 60, respectively.

The input terminal 3 of the drive circuit 1, the first and second power supply terminals 4 and 5, the ground terminal 6, and the output stage 70
Means the corresponding terminals 30, 40, 50,
60 and 70 respectively. Since the output stages 102 to 140 have the same configuration as the output stage 101, the description of the output stage 101 described below also applies to these output stages 102 to 140.

Next, referring to FIGS. 4 and 5, FIG. 6 showing an equivalent circuit of the output stage in FIG. 5, and FIG. 7 showing a waveform diagram for explaining the operation of this output stage, FIG. In operation, first, the voltage VDD2 supplied from the power supply terminal 5 to the terminal 50 is supplied from the terminal 70 to the output terminal 401 by the ON state of the output transistor P103. In this case, the output of the level shift circuit 10, that is, the voltage at the connection point c is set to the low (L) level to turn on the transistor P103. For this purpose, the microcomputer (not shown) controls the internal logic circuit 2 to supply a high (H) level input data signal from the terminal 30 to the inverter INV and the gate electrode of the transistor N102. Assuming that the power supply voltage of the inverter INV at this time is VDD1, the logic level of this input data signal is a voltage between the power supply voltage VDD1 and the ground potential GND (0 V). That is, H level = VDD1 and L level = 0. The ON / OFF state of each of the transistors of the level shift circuit 10 is determined by the transistor P1
02 and N101 are ON and P101 and N102 are OFF. In this operation mode, the conduction / non-conduction state changes in the order of transistors N102 → N101 → P101 → P102. The input signal inverted by the inverter INV becomes H level, and the level shift circuit 10
Transistor N101 and output transistor N10
3 is supplied to each gate electrode. In response to this signal, the transistors P101 and N102 are turned on, the transistors P102 and N101 are turned off, the potential at the connection point c goes low, the transistor P103 is turned on, the transistor N103 is turned off, and the output H from the output terminal 70 goes high. The level becomes the high voltage VDD2. However, the threshold voltages Vth of the transistors N101 and N102 are smaller than VDD1 and larger than 0.

Now, when the transistor N101 changes from ON to O
The transient state in which the transistor N102 changes from OFF to ON to the FF will be described with reference to FIG. 6. In the equivalent circuit 61 of the level shift circuit 10 in the steady state, as described above, the transistors P102 and N10
1 is ON, transistors P101 and N102 are OF
It is assumed that the state is F. Next, when the transistor N101 changes from ON to OFF and the transistor N102 changes from OFF to ON, during a transition period of the change, both the transistors P102 and N102 are turned on, and both the transistors P101 and N101 are turned off. That is, a through current flows through the path of the power supply VDD2 → P102 → N102 → GND (equivalent circuit 62). On the other hand, since both the transistors P102 and N102 are in the ON state, if the ON resistance between the drain and the source of the transistor N102 is smaller than the ON resistance of the transistor P102, a voltage drop due to the ON resistance of the transistor P102 causes a drop in the connection point c. The potential decreases to the L level. In response to this L-level voltage, transistor P101
Is turned on, which causes the transistor P101
And the potential at the connection point d of N101 rises to the H level. Transistor P10 receiving this voltage at its gate electrode
Since the ON resistance of No. 2 increases, the potential of the connection point c drops to a level lower than the L level. Accordingly, the ON resistance of the transistor P101 further decreases, and finally, the transistor P102 is turned on and the transistor P101 is turned on.
The connection point c becomes the GND level in the FF state. In response to this GND level, the output transistor P103
It becomes N state. On the other hand, since the transistor N103 is in the OFF state in response to the input signal IN, the high power supply voltage VDD2 is supplied to the output terminal 70 (the equivalent circuit 6 in the drawing).
3). Note that, in order to sufficiently turn on the transistor P101, the ON resistance of the transistor N102 is set to be 1/4 or less of the ON resistance of the transistor P102. Transistor N101 is ON, N102
Changes to OFF N101 → N102 → P102 → P
Since the above description also applies to the transition period of the operation mode change of 101, the resistance value of the ON resistance of the transistor N101 is set to １ ／ or less of the resistance value of P101.

Referring to FIG. 7, an input terminal 30 is externally provided.
5 shows a waveform 72 of an input signal IN from the inside supplied to the input terminal 30 of the output stage 101 from the internal logic circuit 2 with respect to the input signal waveform 71 to the input stage. That is, at time t1
, The input signal IN from the outside becomes H level, and changes to L level at time t2 and H level again at time t3. The L level of this signal IN is 0 V, H
The level changes with the voltage VDD1 of the low-voltage power supply. The output stage 101 converts the level and outputs the output terminal 70 to the output terminal 4.
01 is supplied to the internal signal IN (waveform 73).
The L level is 0 V, and the H level is the high voltage power supply voltage VDD2.

[0010]

In the above-described output stage circuit, a plurality of output transistors P103 / N103 are provided.
In the transitional period of the ON / OFF change of the voltage, the GND potential at which the current flowing through the high-voltage power supply circuit should be 0 V is varied (waveform 7).
4). Therefore, noise due to the fluctuation of the GND potential is superimposed on the external input signal IN, and the operation stability of the level shift circuit 10 is impaired. That is, at the input terminal 3 of the external input signal IN, the H level of the input signal IN decreases at the time t1, and the time t2 and t3 and the input signal I
A shift occurs between the trailing edge and the leading edge of N (waveform 75 of the input terminal 3), causing a malfunction in the internal logic circuit 2.

Referring also to FIG. 8, a partially modified circuit for explaining the operation of the conventional drive circuit shown in FIG. 8 connects the inverter INV supplied with the low voltage external power supply voltage VDD1 and the internal logic circuit 2 to each other. Receiving ground wiring GND1
And level shift circuit 10 receiving supply of high-voltage external power supply voltage VDD2 and output transistor P103 / N1
03 is grounded at the nodes a and b, and the GND wiring of the IC chip (not shown).
The pads are connected independently. According to this connection, the above-described fluctuation of the GND potential at the contact point b (waveform 7
4) is not directly transmitted to the contact a as it is, so that the above-mentioned malfunction of the internal logic circuit 2 can be suppressed to some extent.

On the other hand, when the EL display panel drive voltage is about 400
Although a voltage change of V is required, the breakdown voltage between the source and the drain of the output transistor P103 / N103 is 200
V, the high voltage VDD2 and the ground wiring GND
A method of inverting the polarity of a potential difference of 200 V between the two at a predetermined switching timing is generally used. The level of noise generated during the transition period during the polarity inversion is about 1 to 3 V for both the positive polarity and the negative polarity, and the potential of the ground wiring GND2 may be lower than the potential of the ground wiring GND1 due to the negative noise. In addition, there is a reduction in the potential of the ground line GND2 caused by the switching noise of one of the output stages of the plurality of output stages being superimposed on the potential of the ground line GND2 via the line capacitance between the lines of the EL display panel. . The former is generally not synchronized with the output change of the output stage,
The latter synchronizes. The drop in the potential of the ground wiring GND2 due to noise that is not synchronized with the output change of the output stage causes the following obstacle. That is, the transistors P101 / N101 of the level shift circuit 10 are turned ON / OFF,
Transistors P102 / N102 are OFF / O respectively
When the transistor N101 is in a steady state at N, the potential of the ground wiring GND2 is lower than the potential of the ground wiring GND1 even though the transistor N101 is in the OFF state because the L level of the ground wiring GND1 is applied to its gate electrode. As a result, the transistor N101 becomes semi-conductive, and a current flows through the transistors P101 / N101. On the other hand, the obstacles when the noise is synchronized with the output change of the output stage are as follows. That is, the transistor P101 / N10
1 are OFF and ON, respectively, and the transistor P10 /
When N102 is in the ON / OFF steady state, transistor N102 receives the L level of ground line GND1 at its gate electrode and is in the OFF state, so that the potential of ground line GND2 changes to ground line GND.
1 lower than the potential of transistor N10.
2 becomes semi-conductive, and the transistor P102 / N10
2, a current flows. Further, a current also flows through the output transistors P103 / N103 due to this semi-conductive state. If the time during which these currents flow becomes longer, the temperature of the IC chip containing this output stage rises, and the free electrons in the internal diode element that determines the breakdown voltage of the IC increase, making it easier for avalanches to occur. The breakdown voltage of the layer connection is reduced, which causes latch-up and element destruction.

SUMMARY OF THE INVENTION An object of the present invention is to provide an EL display panel driving circuit suitable for high-density integration on an IC chip, saving power consumption.

[0014]

According to the present invention, there is provided an inverter for receiving an input signal from an input signal terminal, a series connection circuit of a pair of P-channel FET and N-channel FET, and a P-channel FET of one of the series-connected circuits. Channel FET and N
An auxiliary level shift circuit in which the connection points of the channel FETs are connected to the gates of the N-channel FETs of the other series connection circuit, and a pair of a P-channel FET and an N-channel FET
And the P of one of the series-connected circuits
A connection point between the channel FET and the N-channel FET is a level shift circuit connected to the gate of the P-channel FET of the other series connection circuit, and a series connection circuit of the P-channel FET and the N-channel FET. A first power supply terminal for receiving a low-voltage external voltage comprises a source of a pair of P-channel FETs of the auxiliary level shift circuit and a source connected to the P-channel FET and an N-channel FET. Connected to the inverter, a first ground line is connected to the inverter, and the input signal terminal and the output terminal of the inverter are respectively connected to the P-channel F of the auxiliary level shift circuit.
A second power supply terminal connected to the gates of the ET (P202) and the P-channel FET (P201) and receiving a high-voltage external voltage includes a source of a pair of P-channel FETs of the level shift circuit and a P-channel FET of the output circuit. FE of the auxiliary level shift circuit.
The drain of T (N201) is the N of the level shift circuit.
An N-channel FET (N202) connected to the gate of the channel FET (N102),
Is the N-channel FE of the level shift circuit.
The gate of T (N101) and the N channel F of the output circuit
The drain of the P-channel FET (P102) of the level shift circuit is connected to the gate of the ET (N103).
Connected to the gate of a P-channel FET (P103) of the output circuit;
The source of ET is commonly connected to a second ground wiring, and the first ground wiring and the second ground wiring are independent of each other. .

Even if the potential of the auxiliary ground terminal changes, the change does not substantially change the potential of the ground terminal. Therefore, generation of an unnecessary large current in the output circuit can be avoided.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to FIG. 1, which shows a circuit diagram of a first embodiment of the present invention, in which components common to FIG. Shift circuit 2
0 has a configuration added to the configuration of FIG. That is,
The output stage 101 of this embodiment includes an input terminal 30, a first power supply terminal 40 receiving a low voltage external voltage VDD1, and a second power supply terminal 50 receiving a high voltage external voltage VDD2.
And a first ground terminal 60 (connected to the ground wiring GND1) and a second ground wiring 60a (connected to the ground wiring GND2)
And a high voltage output terminal 70. The output stage 101 is connected to the inverter INV connected to the input terminal 30.
An auxiliary level shift circuit 20 connected to the inverter INV and the input terminal; a level shift circuit 10 receiving the output of the circuit 20;
0a, and an output transistor P103 / N103 of a push-pull configuration connected to the output transistor P103. Further, the inverter I
The NV and auxiliary level shift circuit 20 are connected to a first power supply terminal 40 (voltage VDD1), and the level shift circuit 10 and the output transistor P103 are connected to a second power supply terminal 50 (voltage VDD2). The inverter INV is connected to the first ground wiring GND1, the level shift circuits 10, 20 and the output transistor N103 are connected to the ground wiring GND2, and the connection point of the output transistors P103 / N103 is connected to the high voltage output terminal 70.

The auxiliary level shift circuit 20 includes a series connection circuit of transistors P201 / N201 and a series connection circuit of P202 / N202 inserted in parallel between the first power supply terminal 40 and the second ground terminal 60a, respectively. The gate electrode of the transistor N201 is connected to the connection point e of the transistors P202 / N202.
Are connected to the connection point f of the transistors P201 / N201, respectively. An input signal IN from the input terminal 30 is supplied directly to the gate electrode of the transistor P202 and to the transistor P2 via the inverter INV.
01 are respectively supplied to the gate electrodes. Further, the connection point f is connected to the gate electrode of the transistor N102 of the level shift circuit 10, and the connection point e is connected to the level shift circuit 1
0 and the gate electrode of the output transistor N103. The connection point c of the transistors P102 / N102 of the level shift circuit 10 is connected to the gate electrode of the output transistor P103.

Next, the operation of the output stage 101 in this embodiment will be described with reference to FIG. 2 showing an equivalent circuit of the output stage in this embodiment and FIG. 3 showing a waveform diagram for explaining the operation thereof. In the initial state, the output transistor P103 /
It is assumed that N103 is in an ON / OFF state. (A) In the case where a voltage of 0 V is generated from the output terminal 70 Since the output transistor is in the initial state, the transistors P101 / N1 of the level shift circuits 10 and 20 are used.
02, P201 / N202 are ON, P10
2 / N101 and P202 / N201 are in the OFF state (equivalent circuit 26). In response to the L level of the input signal IN, the transistor P201 is turned on and the transistor P202 is turned on.
Change to FF. In the transition period of the change, both the transistors P202 / N202 are in the ON state, and the transistor P2
01 / N201 are both turned off. That is, a through current flows through the path of the power supply VDD1 → P202 → N202 → GND (equivalent circuit 21). At this time, the transistors P201 / N201 are both OFF, and the connection point f remains at the H level, so that the transistor N202 also keeps the ON state. Transistor P202 / N
202 are both ON, the transistor P20
If the ON resistance of the transistor 2 is smaller than the ON resistance of the transistor N202, the voltage drop due to the ON resistance of the transistor P202 is small, so the potential at the connection point e rises and approaches the H level. When this voltage reaches the H level, the transistor N201 turns on (equivalent circuit 22). As a result, the potential at the connection point f falls to the L level, and the ON resistance of the transistor N202 receiving this voltage at the gate electrode increases. As a result, the potential at the connection point e further rises to the H level. Thus, the ON resistance of the transistor N201 further decreases. Eventually, transistor P202 becomes O
N, the transistor N202 is turned off, and the connection point e becomes the VDD1 level (equivalent circuit 23).

When the transistor N101 is turned on in response to the H level of the connection point e, the ON state changes from N102 to N10 every time the logic level of this connection point is inverted.
It shifts in the order of 1 → P102 → P101. In the transitional period of these ON state shifts, the transistor P1
01 / N101 are both ON, transistor P102
/ N102 are both OFF. That is, the power supply V
A current flows through the path of DD2 → P101 → N101 → GND2 (equivalent circuit 22). In this transition period, both the transistors P102 / N102 are in the OFF state and the connection point c holds the L level in the above-described steady state, so that the transistor P101 also maintains the ON state (the equivalent circuit 22). Also, transistors P101 / N101
Are both in the ON state. On the other hand, since the ON resistance of the transistor N101 is set smaller than the ON resistance of the transistor P101, the potential of the connection point d drops to L level due to the voltage drop due to the ON resistance of the transistor P101. When approaching, the transistor P102 is turned ON and the connection point c
Is set to the H level, the ON resistance of the transistor P101 is further increased, and the potential of the connection point d of the transistor P101 / N101 is further decreased to approach the L level.
Feedback is applied so as to further reduce the ON resistance of the transistor P102. As a result, the transistor P102 becomes O
N, the transistor N102 is turned off, and the connection point c becomes H level. When the connection point c becomes H level, the output transistor P103 is turned off. At the same time, the output transistor N103 receives the H level of the connection point e and is in the ON state, so that the output terminal 70 becomes 0V (equivalent circuit 23). Note that the above-described level shift circuit 10
Similarly, in the level shift circuit 20, in order to speed up the transition of the transistors N201 / N202 to the ON state and thereby reduce the unnecessary current during the transition period, the value of the ON resistance of each of the transistors P201 / P202 is reduced. Is set to about 1/4 or less of the corresponding value of N201 / N202. (B) When the same voltage as the high voltage VDD2 is generated from the output terminal 70 (OUT) The level shift circuits 10 and 2 before the high voltage generation operation
0 transistor ON / OFF state is P101 / N1
02 is OFF, P102 / N101 is ON, P201 /
N202 is OFF and P202 / N201 is ON in each steady state (equivalent circuit 23). In response to the H level of the input signal IN, the transistor P201 changes to ON and P202 changes to OFF. In the transition period of the change, both the transistors P201 / N201 are in the ON state,
Both 202 / N202 are turned off. That is, a current flows through the path of the power supply VDD1, P201, N201, and GND2 (equivalent circuit 24 in the figure). At this time, the transistors P202 / N202 are both OFF, and the connection point f holds the L level in the steady state, so that the transistor N202 also keeps the OFF state. Transistor P20
1 / N201 are both ON, while the ON resistance of the transistor P201 is set smaller than the ON resistance of the transistor N201.
The voltage drop due to the ON resistance of 1 is smaller, and the potential at the connection point e rises and approaches the H level. Upon receiving this H-level voltage, the transistor N202 turns on (equivalent circuit 2).
5). As a result, the potential at the connection point e decreases and approaches the L level. A transistor N receiving this voltage at the gate electrode
As the ON resistance of 201 increases, the potential at node f further rises and approaches the H level. Along with this, feedback is performed so that the ON resistance of the transistor N202 further decreases. Eventually, the transistor P202 becomes OF
F and N202 are turned on, the connection point e is at the GND2 level, the transistor P201 is turned on, N201 is off, and the connection point f is at the VDD1 level (equivalent circuit 2).
6).

When the transistor N102 is turned on in response to the H level at the connection point f, the transistor N102
During the transitional period of the switching to the ON state, the transistor P
102 / N102 are both ON, transistor P10
1 / N101 are both OFF. Therefore, the power supply terminal 50 of the voltage VDD2 → P102 → N102 → GN
A current flows through the path of D2 (equivalent circuit 2 shown).
5). At this time, the transistors P101 / N101 are both in the OFF state, and the connection point d is the L in the previous state (equivalent circuit 24).
Since the level is maintained, the transistor P102
Keep N state. Both the transistors P102 / N102 are in the ON state, while the ON resistance of the transistor N102 is set smaller than that of the transistor P102. Therefore, the potential at the connection point c decreases due to the voltage drop due to the ON resistance of the transistor P102. Approaching the L level,
The transistor P101 is turned on, the potential at the connection point d is raised to approach the H level, and the transistor P102 is turned on.
The resistance is further increased, the potential at the connection point c is further lowered to approach the L level, and feedback is performed so as to further reduce the ON resistance of the transistor P101. As a result, the transistor P102 is turned off and the transistor N102 is turned on, and the connection point c becomes the GND2 level (equivalent circuit 26). When the connection point c becomes L level, the output transistor P103 is turned on, the N103 is turned off, and the output terminal 7 is turned off.
0 is supplied with the high voltage VDD2 (equivalent circuit 26).

Referring also to FIG. 3, the internal logic circuit 2
, The internal signal IN from the input terminal 30 to the input terminal 30 becomes the H level at the time t1, the L level at the time t2, and the t3
Is a pulse that repeatedly changes to the H level again, and the L level takes the value of 0 V and the low voltage power supply VDD1. The potential at the connection point e of the level shift circuit 20 changes as shown by the waveform 33 due to the noise (waveform 32) superimposed on the ground wiring GND2 generated by the operation of the output stages (102 to 140) other than the output stage 101. By the above operation, the output of the waveform 34 is obtained at the output terminal 70.

As described above, the auxiliary level shift circuit 20 in the output stage 10 of the above embodiment complements the transistors P201 and P202 in response to the input signal IN.
Since the N / OFF control is performed, it is hardly affected by the fluctuation of the potential of the ground wiring GND2. That is, even when the potential of the ground wiring GND2 becomes lower than the potential of the ground wiring GND1, the difference from the potential of GND1 is VDD1- (the absolute value of Vth) (where Vth is the transistor P201 / P202
(The threshold value of the input signal IN) is not confused with the L level of the input signal IN. Therefore, the transistors N201 / N202 in the configuration of the prior art described above are used.
And the generation of unnecessary currents associated therewith is avoided. The influence of noise that may occur due to the level change of the voltage VDD2 in the process of changing the potential of the connection point e from the H level to the L level can be avoided by the common connection by the ground wiring GND2. That is, the L level potential of the connection point e also shifts following this noise, and the threshold value of the transistor N101 / 102 receiving this signal also follows the fluctuation of the noise of the potential level of the ground line GND2 and is the same. The transistor N101
/ N102 is not accidentally turned on.

In the above embodiment, the relationship between the level of the voltage VDD1 and the potential of the ground line GND1, and the level of the voltage VDD
2 and the voltage of the ground wiring GND2 can be reversed in height. In that case, transistors P10 forming level shift circuits 10 and 20, respectively,
1 / N101, P102 / N102, P201 / N20
1, and the arrangement of the series connection circuits of P202 / N202 are interchanged with each other.

According to this circuit configuration, the transistor N2
Since the ON resistance of 01 / N202 (connection corresponds to N201 / N202 in FIG. 1) is smaller than the ON resistance of transistors P201 / P202 (connection corresponds to N201 / N202 in FIG. 1), the ratio of these ON resistances is desired. When these level shift circuits 20 are configured to set the value to the above value, the occupied area on the IC chip surface can be made smaller than that in the above-described embodiment.

[0025]

As described above, according to the present invention, an auxiliary level shifter having a circuit configuration substantially complementary to a level shift circuit and supplying a pair of control signals to the level shift circuit in response to an input signal. Circuit, and the level shift circuit, the auxiliary level shift circuit, and the output circuit are connected to an auxiliary ground terminal separate from the ground terminal, so that even if the potential of the auxiliary ground terminal fluctuates, The fluctuation does not substantially change the potential of the ground terminal. Accordingly, erroneous driving of the level shift circuit on the high voltage side can be avoided and unnecessary current in the output transistor can be avoided.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an output stage of an EL display panel drive circuit according to the present invention.

FIG. 2 is an equivalent circuit diagram of the output stage of FIG.

FIG. 3 is a waveform chart for explaining the operation of the output stage of FIG. 1;

FIG. 4 is a block diagram of a conventional EL display panel drive circuit.

FIG. 5 is a circuit diagram of an output stage of the drive circuit of FIG.

FIG. 6 is an equivalent circuit diagram of the output stage of FIG.

FIG. 7 is a waveform chart for explaining the operation of the output stage in FIG. 5;

FIG. 8 is a partially modified circuit diagram for explaining the operation of the drive circuit of FIG. 4;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Level shift circuit 20 Auxiliary level shift circuit 30 Input terminal 40 1st power supply terminal 50 2nd power supply terminal 60 1st ground terminal 60a 2nd ground terminal 70 High voltage output terminal (OUT) 101 Output stage GND1 1st Ground wiring GND2 Second ground wiring IN Input signal INV Inverter VDD1 Low voltage external voltage VDD2 High voltage external voltage P101, 102, 103, 201, 202 P-channel FET N101, 102, 103, 201, 202 N-channel FET

Claims (2)

(57) [Claims] An input terminal for receiving an input signal from an input signal terminal.
A series connection of a converter and a pair of P-channel FET and N-channel FET
And a P-channel F of one of the series-connected circuits
The connection point between ET and N-channel FET is
Auxiliary relay connected to the gate of the N-channel FET
Bell shift circuit and a series connection of a pair of P-channel FET and N-channel FET
And a P-channel F of one of the series-connected circuits
The connection point between ET and N-channel FET is
Level connected to the gate of the P-channel FET in the continuation circuit
Shift circuit, P-channel FET and N-channel FET
Column connection circuit, and the P channel of this series connection circuit.
The connection point between the FET and the N-channel FET is
A first power supply terminal configured to receive a low-voltage external voltage is connected to the auxiliary level.
Source of a pair of P-channel FETs of the
Connected to an inverter, and further provided with a first ground wiring.
And the input signal terminal and the output terminal of the inverter are connected to the inverter.
The P-channel FET (P
202) and the gate of the P-channel FET (P201).
And a second power supply terminal for receiving a high-voltage external voltage is connected to the level switch.
Source of a pair of P-channel FETs of the
Connected to the source of the P-channel FET of the power circuit.
Of the N-channel FET (N201) of the auxiliary level shift circuit
The drain is an N-channel FET of the level shift circuit.
(N102) connected to the gate of the auxiliary level shift circuit.
The drain of 2) is an N-channel of the level shift circuit.
The gate of the FET (N101) and the N channel of the output circuit
P-channel FET (P102) connected to the gate of the
Is the P-channel FET (P1) of the output circuit.
03), and the level shift circuit, the auxiliary level shift circuit,
And the source of each N-channel FET of the output circuit
Are commonly connected to a second ground wiring, and the first connection
The ground wiring and the second ground wiring are independent.
And an electroluminescence display driving circuit. 2. The voltage of said first and second power supply terminals is
The connection relationship between the P-channel FET and the N-channel FET that have a negative polarity with respect to the reference voltage from the ground wiring and constitute each of the series-connected circuits is reversed with respect to the reference voltage; The electroluminescence display drive circuit according to claim 1, wherein: