JP3263882B2 - Vertical synchronization signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical synchronizing signal processing circuit for performing clamping on a vertical synchronizing signal and determining whether the clamped vertical synchronizing signal has a negative polarity or a positive polarity. About.

[0002]

2. Description of the Related Art A computer display device that receives data from various computers and displays images such as characters, diagrams, patterns, and the like according to the data, uses information represented by data from the computer as information content. ,
A horizontal period portion and a vertical period portion are formed with a video signal which is to be repeated at a predetermined cycle, and the video signal is supplied to, for example, a display cathode-ray tube in which horizontal scanning and vertical scanning are performed, and a video signal for display is provided. An image is displayed on a cathode ray tube. Therefore, in a computer display device, a horizontal synchronizing signal and a vertical synchronizing signal are used for forming a video signal containing information represented by data from a computer as an information content, and forming a horizontal scanning signal and a vertical scanning signal for a display cathode ray tube. A signal, and therefore the computer receives the horizontal synchronization signal and the vertical synchronization signal together with the data.

[0003] Each of the horizontal synchronization signal and the vertical synchronization signal received by the computer display device from the computer is generally not uniform regardless of the connected computer, but differs depending on the connected computer. It has a frequency, an amplitude, a DC level, and the like, and further forms a pulse train of a negative polarity or a pulse train of a positive polarity. therefore,
In a computer display device, a configuration is adopted that can appropriately respond to each of a horizontal synchronization signal and a vertical synchronization signal arriving in various states from a computer, and as a part thereof, for example, a horizontal synchronization signal from a computer and In the part that accepts the vertical sync signal,
A discriminating circuit unit is provided which has a function of discriminating whether a vertical synchronizing signal from a computer forms a pulse train of negative polarity (negative polarity) or a pulse train of positive polarity (positive polarity). Can be

A discriminating circuit for performing a function of discriminating whether a vertical synchronizing signal from a computer has a negative polarity or a positive polarity has a function of detecting a vertical synchronizing signal received from a computer in accordance with the computer. Assuming that the frequency, amplitude, DC level, and the like are assumed to be different, first, the received vertical synchronization signal is subjected to a clamping process to standardize the DC level, and then the clamped vertical synchronization signal is processed. , To determine whether it is of negative polarity or positive polarity. FIG. 3 shows a conventionally proposed vertical synchronization signal processing circuit as a component of such a determination circuit section.

In the vertical synchronizing signal processing circuit shown in FIG. 3, a vertical synchronizing signal SV is supplied to an input terminal 11 from a computer. In response to the vertical synchronizing signal SV from the input terminal 11, one end is connected to the input terminal 11 and the other end is connected to the ground potential point via the resistor 13; The ground value is clamped by the diode 14 connected to the other end of the power supply unit 12 and connected to the power supply unit + B via the resistance element 15 on the anode side. In connection with the diode 14, there is provided a diode 16 whose anode side is connected to the anode side of the diode 14 and whose cathode side is connected to the ground potential point. A current flows from the power supply unit + B through the resistance element 15 to the diode 16, and the resistance of the resistance element 15 is
Is selected to be a forward current sufficient to cause the diode 16 to maintain a stable ON state.

The diode 16 generates a substantially constant forward voltage between its anode and cathode when a sufficient forward current flows from the power supply section + B through the resistance element 15, and this forward voltage is, for example, 0V. .7v. Therefore, the potential of the connection point P on the anode side of the diode 14 is maintained at 0.7 V. Then, under such a condition, in the base level period of the vertical synchronization signal SV appearing on the connection point Q side at the other end of the capacitor element 12 from the input terminal 11 through the capacitor element 12,
A forward current flows from the power supply section + B to the diode 14 through the resistance element 15, so that the base level is connected between the both ends of the resistance element 13, and thus to the connection point Q.
For example, the vertical synchronization signal SVc to which the ground value is clamped, which is clamped to a potential based on the potential of 0.7 V
Is obtained.

[0007] The vertical synchronization signal SVc obtained at the connection point Q and subjected to the base value clamp is supplied to the signal processing unit 18 through the terminal 17. In the signal processing section 18, in addition to other various signal processing, the vertical synchronization signal SVc
Is subjected to a polarity discriminating process for discriminating whether the signal is negative or positive, and a discrimination output signal SD is obtained together with other various output signals.

The vertical synchronizing signal S supplied to the input terminal 11
The base value clamping operation for V is directly performed by the capacitor element 12 and the diode 14, and the clamp level is set by the diode 14 from the power supply unit + B to the resistance element 15 during the base level period of the vertical synchronization signal SV. Through the forward current through the
It is set according to the forward voltage generated between the anode and the cathode of the diode 14. That is, the clamp level of the vertical synchronization signal SVc having the ground value clamp obtained at the connection point Q is, for example, from the potential of the connection point P maintained at 0.7 V to the diode during the base level period of the vertical synchronization signal SV. The potential of the diode 14 is reduced by the forward voltage in the diode 14 caused by the flow of the forward current.

[0009]

In the vertical synchronizing signal processing circuit as described above, the capacitor element 12 and the diode 14 which perform the base value clamping operation during the base level period of the vertical synchronizing signal SV supplied to the input terminal 11.
Of the forward current flowing through the diode 14 becomes smaller as the duty ratio (the ratio of the base level period to the period) of the base level period in the vertical synchronization signal SV increases. When the duty ratio of the vertical synchronization signal SV in the base level period is small, the forward current flowing through the diode 14 during the base level period of the vertical synchronization signal SV causes the diode 14 to maintain a stable ON state. It is assumed to be a relatively large value which is sufficient to cause the diode 14 to produce a substantially constant forward voltage between its anode and cathode, and this forward voltage can be, for example, 0.7V. Is done. Therefore, in such a case, the clamp level of the vertical synchronization signal SVc having the base value clamp obtained at the connection point Q is, for example, 0.
From the potential of the connection point P maintained at 7v, for example, 0.7
For example, 0 v is obtained by reducing the forward voltage in the diode 14 which is set to v.

On the other hand, when the duty ratio of the vertical synchronizing signal SV in the base level period is large, the forward current flowing through the diode 14 during the base level period of the vertical synchronizing signal SV takes a small value. Thereby, the forward voltage generated by the diode 14 between its anode and cathode depends on the small value of the forward current, for example,
It is assumed to take a value smaller than 0.7v. Therefore, in such a case, the clamp level of the vertical synchronization signal SVc having the base value clamp obtained at the connection point Q is, for example,
From the potential of the connection point P maintained at 0.7 V, for example,
The forward voltage in the diode 14, which is set to be smaller than 0.7V, is obtained by reducing the forward voltage. For example, the diode 14 has a value larger than 0V and smaller than 0.7V.

Therefore, when the vertical synchronizing signal SV supplied to the input terminal 11 is of a negative polarity with an amplitude value of 1.0 V, as shown in FIG. Since the duty ratio of Tb is small,
In the base level period Tb of the vertical synchronizing signal SV, the forward current flowing through the diode 14 takes a large value, whereby the forward voltage in the diode 14 becomes a substantially constant value of, for example, 0.7 V. It shall be taken. Therefore, in such a case, as shown in FIG. 4B, the vertical synchronizing signal SVc having the base value clamp obtained at the connection point Q has a clamp level at which the base level portion is set to a normal level. It takes a value, for example, 0v.

On the other hand, when the vertical synchronizing signal SV supplied to the input terminal 11 is of a positive polarity with an amplitude value of 1.0 V, as shown in FIG. Since the duty ratio of the level period Tb is large, the forward current flowing through the diode 14 takes a small value in the base level period Tb of the vertical synchronizing signal SV. The value is smaller than 0.7v, for example, about 0.3v. Therefore, in such a case, the vertical synchronization signal SVc obtained at the connection point Q and having the base value clamp applied thereto is the same as that shown in FIG.
As shown in E, the clamp level at which the base level portion is placed is not a normal value, for example, 0 V, but is higher than that, for example, about 0.4 V. Will be.

As described above, when the vertical synchronizing signal SV supplied to the input terminal 11 has a negative polarity as shown in FIG. 4A, the ground value clamp obtained at the connection point Q is applied. As shown in FIG. 4B, the clamp level of the vertical synchronizing signal SVc assumes a normal value, for example, 0 V, while the input terminal 1
When the vertical synchronization signal SV supplied to 1 is of a positive polarity as shown in FIG. 4D, the vertical synchronization signal SVc obtained at the connection point Q and having a base value clamped is
As shown in FIG. 4E, under the condition that the clamp level is not a regular value, for example, 0.4 V, the base value clamp obtained at the connection point Q may be used. Is applied to the terminal 17.
In the signal processing unit 18 supplied through the network, various inconveniences occur in signal processing there.

For example, in the signal processing section 18, a threshold level is set for the vertical synchronization signal SVc on which the base value is clamped, and the vertical synchronization signal SVc is set.
A process of removing a noise component mixed in c is performed. When the vertical synchronization signal SV supplied to the input terminal 11 has a negative polarity, as shown in FIG.
With respect to the vertical synchronization signal SVc having the base value clamped, the noise component N mixed into the vertical synchronization signal SVc is reduced to the threshold level Ln, with the threshold level Ln set based on 0 V. Thus, the noise component N mixed in the vertical synchronization signal SVc is properly removed. On the other hand, when the vertical synchronizing signal SV supplied to the input terminal 11 has a positive polarity, as shown in FIG. 4F, a threshold value is applied to the vertical synchronizing signal SVc having the base value clamped. When the noise level Np is set on the basis of 0 V, the noise component N mixed in the vertical synchronization signal SVc may exceed the threshold level Lp. The noise component N mixed in the signal SVc is not properly removed. Note that the vertical synchronization signal SVc
The horizontal synchronizing signal or the like undesirably mixed into the vertical synchronizing signal SV supplied to the input terminal 11 can be considered as the noise component N mixed into the input terminal 11.

In view of the above, according to the present invention, a clamping process is performed on a vertical synchronizing signal such as a vertical synchronizing signal supplied from various computers by using a capacitor element and a diode. When determining whether the vertical synchronization signal is negative or positive, the vertical synchronization signal to be clamped has a negative polarity and a positive polarity with a relatively simple configuration. It is an object of the present invention to provide a vertical synchronizing signal processing circuit that can make the clamp level of the clamped vertical synchronizing signal appropriate in any case.

[0016]

To achieve the above object, a vertical synchronization signal processing circuit according to the present invention has one end connected to an input terminal to which a vertical synchronization signal is supplied, and the other end connected to a first terminal. via the resistance element, for example, is a grounding potential
A capacitor element connected to the first reference potential point , a cathode side connected to the other end of the capacitor element, and an anode side connected to the second resistance element , for example, as a power supply unit .
A first diode connected to the second reference potential point, the anode is connected to the anode side of the first diode, a second diode having a cathode side connected to the first reference potential point, the other capacitor element In addition to a polarity discriminator connected to the other end of the capacitor element and discriminating whether the vertical synchronization signal obtained at the other end of the capacitor element is negative or positive,
Is connected between the anode side of the diode and the first reference potential point.
The vertical synchronization signal obtained at the other end of the element has a positive polarity.
Signal indicates that the discrimination output signal is
The vertical synchronization signal obtained at the other end of the
And an impedance element configured to reduce the potential on the anode side of the first diode.

[0017]

In the vertical synchronizing signal processing circuit according to the present invention configured as described above, the vertical synchronizing signal supplied to the input terminal is subjected to the ground value clamp by the capacitor element and the first diode. Thereby, a vertical synchronization signal having a ground value clamp obtained at the other end of the capacitor element to which the cathode side of the first resistor element and the cathode of the first diode is connected is supplied to the polarity discrimination unit, and the polarity discrimination is performed. From the unit, a discrimination output signal indicating that the vertical synchronization signal to which the base value clamp has been applied is negative or the vertical synchronization signal to which the base value clamp has been applied is positive is obtained. . When the vertical synchronization signal to which the base value clamp is applied is negative, the vertical synchronization signal SV supplied to the input terminal is negative, and the vertical synchronization signal to which the base value clamp is applied is applied. When the signal is positive, the vertical synchronization signal supplied to the input terminal is positive, so that the discrimination output signal is, after all, the vertical synchronization signal supplied to the input terminal is negative. Alternatively, this indicates that the vertical synchronization signal supplied to the input terminal has a positive polarity.

When the impedance element is controlled by the discrimination output signal, the vertical synchronizing signal supplied to the input terminal is of a positive polarity, and when a discrimination output signal indicating this is obtained from the polarity discrimination unit, the impedance is determined. The element assumes a state in which the potential on the anode side of the first diode connected to the second resistor element and the anode side of the second diode is reduced. The potential on the anode side of the first diode is reduced by the impedance element when the vertical synchronizing signal supplied to the input terminal is of a negative polarity and a discrimination output signal indicating this is obtained from the polarity discrimination unit. Instead, it takes a value set by the forward voltage generated by the second diode, the vertical synchronization signal supplied to the input terminal is of positive polarity, and a discrimination output signal indicating this is obtained from the polarity discrimination unit. At this time, the impedance is lowered by the impedance element, and the value becomes smaller than the forward voltage generated by the second diode when the vertical synchronization signal supplied to the input terminal is negative.

The clamp level of the vertical synchronizing signal obtained at the other end of the capacitor element and having the base value clamped is changed from the potential on the anode side of the first diode to the base level period of the vertical synchronizing signal supplied to the input terminal. In this case, the potential is reduced by the forward voltage generated by the first diode when the forward current flows through the first diode. The value of the forward current flowing through the first diode during the base level period of the vertical synchronization signal supplied to the input terminal is such that the vertical synchronization signal supplied to the input terminal has a negative polarity and the duty ratio of the base level period is small. Is large when the vertical synchronizing signal supplied to the input terminal is positive and the duty ratio in the base level period is large. Thereby, the forward voltage generated by the first diode during the base level period of the vertical synchronization signal supplied to the input terminal becomes equal to the second voltage when the vertical synchronization signal supplied to the input terminal is negative. And the vertical synchronizing signal supplied to the input terminal is negative when the vertical synchronizing signal supplied to the input terminal is positive. It is smaller than usual.

Therefore, when the vertical synchronizing signal supplied to the input terminal has a negative polarity, the potential of the anode of the first diode and the first level of the vertical synchronizing signal supplied to the input terminal during the base level period. Both the forward voltage produced by the diode will be equivalent to the forward voltage produced by the second diode at the same time, and the grounded clamped vertical synchronization obtained at the other end of the capacitor element. The clamp level of the signal takes a regular value of 0 V, for example. When the vertical synchronization signal supplied to the input terminal has a positive polarity, the first
The potential on the anode side of the diode becomes smaller than the forward voltage generated by the second diode when the vertical synchronizing signal supplied to the input terminal is of a negative polarity due to the decrease caused by the impedance element. On the other hand, the forward voltage generated by the first diode during the base level period of the vertical synchronization signal supplied to the input terminal is reduced, and the forward current flowing through the first diode is reduced. As a result, the potential on the anode side of the first diode is equal to the forward voltage generated by the first diode during the base level period of the vertical synchronization signal supplied to the input terminal. That is, the clamp level of the vertical synchronization signal having the base value clamp obtained at the other end of the capacitor element takes a normal value of, for example, 0V. It is.

As described above, based on the relatively simple configuration including the impedance element, when the vertical synchronizing signal supplied to the input terminal has a negative polarity, In either case, the vertical synchronization signal obtained at the other end of the capacitor element and supplied to the polarity discrimination unit is subjected to the base value clamped vertical synchronization signal, and the clamped vertical synchronization signal is supplied to the other end of the capacitor element. The level will be a regular value.

[0022]

FIG. 1 shows an example of a vertical synchronizing signal processing circuit according to the present invention.

In the example shown in FIG.
1 is supplied with, for example, a vertical synchronizing signal SV from a computer. One end of the input terminal 21 corresponds to the vertical synchronization signal SV supplied to the input terminal 21.
, And the other end is connected to the ground potential point via a resistor 23, and the cathode is connected to the other end of the capacitor 22 and the anode is connected to the power supply + B via a resistor 25. , A ground value clamp is performed by the diode 24 connected to the ground.

In connection with the diode 24, a diode 26 having an anode connected to the anode of the diode 24 and a cathode connected to the ground potential point.
Further, a transistor 29 whose emitter is connected to the anode side of the diode 24 and whose collector is connected to the ground potential point, and whose emitter-collector path is connected in parallel to the diode 26, is a variable impedance element. It is provided as. The transistor 29 is supplied at its base with a discrimination output signal SD sent from a polarity discriminating unit included in a signal processing unit 28 described later, whereby the impedance of the emitter-collector passage is changed according to the discrimination output signal SD. The off-state, in which the value takes an extremely large impedance value that can be regarded as substantially nonexistent, and the impedance forming state, in which the impedance value of the emitter-collector path is relatively small, are selectively selected. You.

When the transistor 29 is in an impedance forming state, a current flows from the power supply unit + B through the resistance element 25 to both the diode 26 and the emitter-collector path of the transistor 29. When the transistor 29 is turned off, the diode 26 is connected to the resistance element 2 from the power supply + B.
5, but the emitter-collector path of transistor 29 is substantially free of current. The resistance value of the resistance element 25 is determined based on the assumption that the transistor 29 is turned off.
The current flowing through diode 26 is selected to be a forward current sufficient to keep diode 26 stable on.

The diode 26 generates a substantially constant forward voltage between its anode and cathode under a sufficient forward current flowing from the power supply section + B through the resistance element 25. The forward voltage is, for example, 0V. .7v. Therefore, under the condition that the transistor 29 is turned off, the potential of the connection point P on the anode side of the diode 24 where the resistance element 25 and the anode side of the diode 26 are connected is maintained at 0.7 V. Become. On the other hand, under the condition that the transistor 29 assumes an impedance forming state, a relatively small value of impedance formed by the emitter-collector path of the transistor 29 is connected in parallel to the diode 26. , The potential at the connection point P is reduced to a value smaller than the forward voltage of 0.7 V generated by the diode 26. In such a case, the potential of the connection point P is set in accordance with the adjustment of the impedance value of the emitter-collector path in the transistor 29 in the impedance forming state, and the impedance value of the emitter-collector path in the transistor 29 in the impedance forming state is adjusted. The potential of the connection point P is adjusted to, for example, about 0.3 V.

Under the circumstances, the resistance element 23 and the diode 24 are connected from the input terminal 21 through the capacitor element 22.
During the base level period of the vertical synchronizing signal SV appearing on the connection point Q side at the other end of the capacitor element 22 to which the cathode side is connected, a forward current flows from the power supply unit + B through the resistance element 25 to the diode 24, , Between the two ends of the resistance element 23, that is, at the connection point Q, the base level portion of the connection point P is, for example, 0.7 V or 0.1.
Clamped to a potential based on a potential of about 3v,
The vertical synchronization signal SVc to which the base value clamp has been performed is obtained.

The vertical synchronization signal SVc obtained at the connection point Q and subjected to the base value clamp is supplied to a signal processing unit 28 through a terminal 27. In the signal processing unit 28, in addition to various other signal processing, a polarity determination unit included in the signal processing unit 28 determines whether the vertical synchronization signal SVc has a negative polarity or a positive polarity. Is done,
A discrimination output signal SD from the polarity discrimination unit based on the signal is obtained together with other various output signals. The discrimination output signal SD obtained from the polarity discrimination unit included in the signal processing unit 28 takes a high level indicating that the vertical synchronization signal SVc to which the base value clamp has been applied is negative,
When the vertical synchronizing signal SVc to which the base value clamp has been applied has a positive polarity, the level is set to a low level indicating this.

The vertical synchronization signal S to which the base value clamp has been applied
When Vc has a negative polarity, the vertical synchronization signal SV supplied to the input terminal 21 has a negative polarity, and when the vertical synchronization signal SVc subjected to the base value clamp has a positive polarity, Since the vertical synchronizing signal SV supplied to the input terminal 21 is of a positive polarity, the discrimination output signal SD is, when the vertical synchronizing signal SV supplied to the input terminal 21 is of a negative polarity, When the vertical synchronizing signal SVc supplied to the input terminal 21 has a positive polarity, it takes a low level indicating this. Then, the discrimination output signal SD obtained from the polarity discrimination unit included in the signal processing unit 28 is supplied to the base of the transistor 29 as described above.

The transistor 29 is turned off when the discrimination output signal SD supplied to the base is at a high level, and the transistor 29 is supplied with the discrimination output signal S supplied to the base.
When D takes a low level, an impedance forming state is assumed. Therefore, the transistor 29 is turned off when the vertical synchronization signal SV supplied to the input terminal 21 is negative, and the transistor 29 is turned off when the vertical synchronization signal SV supplied to the input terminal 21 is positive. At some point, an impedance forming state is established.

The vertical synchronizing signal S supplied to the input terminal 21
The base value clamping operation for V is directly performed by the capacitor element 22 and the diode 24, and the clamp level is changed from the power supply unit + B to the resistance element 25 by the diode 24 during the base level period of the vertical synchronization signal SV. Through the forward current through the
It is set according to the forward voltage generated between the anode and the cathode of the diode 24. That is, the clamp level of the vertical synchronizing signal SVc obtained at the connection point Q and having the base value clamped is determined by the forward current flowing through the diode 24 during the base level period of the vertical synchronization signal SV from the potential of the connection point P The forward voltage generated by the diode 24 is set to a reduced potential. The potential of the connection point P is based on the forward voltage generated by the diode 26 when the vertical synchronization signal SV supplied to the input terminal 21 is negative and the transistor 29 is turned off. For example, when the vertical synchronizing signal SV supplied to the input terminal 21 is of a positive polarity and the transistor 29 assumes an impedance forming state, the voltage drop by the transistor 29 may be reduced. For example, it is set to about 0.3 V.

Even in this example, during the base level period of the vertical synchronizing signal SV supplied to the input terminal 21, the diode 24 of the capacitor element 22 and the diode 24 that perform the base value clamping operation is connected. The value of the flowing forward current decreases as the duty ratio of the vertical synchronization signal SV in the base level period increases. When the duty ratio of the vertical synchronization signal SV in the base level period is small, the vertical synchronization signal S
The forward current flowing through the diode 24 during the base level period of V has a relatively large value that is sufficient to maintain the diode 24 in a stable ON state;
As a result, the diode 24 generates a substantially constant forward voltage between its anode and cathode, and this forward voltage is set to, for example, 0.7 V. On the other hand, if the duty ratio of the vertical synchronization signal SV in the base level period is large, the diode 2
4 has a small value, so that the forward voltage generated by the diode 26 between its anode and cathode is greater than 0 V according to the small value of the forward current. Taking a value less than 0.7v,
For example, it is about 0.3v.

Therefore, when the vertical synchronizing signal SV supplied to the input terminal 21 has a negative polarity with an amplitude value of 1.0 V as shown in FIG. Since the duty ratio of Tb is small,
In the base level period Tb of the vertical synchronizing signal SV, the forward current flowing through the diode 24 takes a large value, whereby the forward voltage in the diode 24 becomes a substantially constant value of, for example, 0.7 V. It shall be taken. In such a case, since the vertical synchronization signal SV supplied to the input terminal 21 is of a negative polarity, the transistor 29 is turned off, whereby the potential of the connection point P Is set to, for example, 0.7 V, so that the vertical synchronization signal SVc obtained at the connection point Q and subjected to the ground value clamp is, as shown in FIG. Is the connection point P
Is obtained by subtracting the forward voltage of the diode 24, for example, 0.7 V from the potential of, for example, 0.7 V.
For example, it takes a normal value of 0v.

If the vertical synchronizing signal SV supplied to the input terminal 21 has a positive polarity with an amplitude value of 1.0 V, as shown in FIG. Since the duty ratio of Tb is large, the forward current flowing through the diode 24 during the base level period Tb of the vertical synchronizing signal SV takes a small value. The value is smaller than 7v, for example, about 0.3v. In such a case, since the vertical synchronization signal SV supplied to the input terminal 21 has a positive polarity, the transistor 29 assumes an impedance forming state. Potential is 0.7v
The vertical synchronization signal SVc having the ground value clamp obtained at the connection point Q is reduced to about 0.3 V, as shown in FIG. A normal value that is obtained by subtracting the forward voltage of the diode 24, for example, about 0.3 V from the potential of the connection point P, for example, about 0.3 V, for example, is 0 V. Will be taken.

As described above, in the example shown in FIG. 1, the vertical synchronizing signal SV supplied to the input terminal 21 is
In both cases of the negative polarity as shown in FIG. 2A and the positive polarity as shown in FIG. As shown in FIG. 2B or 2D, the clamp level of the clamped vertical synchronization signal SVc is assumed to be a normal value, for example, 0v. As a result, in the signal processing unit 28 to which the vertical synchronization signal SVc subjected to the base value clamp is supplied through the terminal 27, no inconvenience occurs in the signal processing there.

For example, in the signal processing unit 28, a threshold level is set for the vertical synchronizing signal SVc having the base value clamped, and the vertical synchronizing signal SVc is set.
When the process of removing the noise component mixed in the vertical synchronization signal SVc is performed, the noise included in the vertical synchronization signal
The threshold level set with reference to v is not reached, and the noise included in the vertical synchronization signal SVc having a positive polarity is 0 V with respect to the vertical synchronization signal SVc. The noise mixed into both the vertical synchronizing signal SVc of the negative polarity and the vertical synchronizing signal SVc of the positive polarity which does not exceed the set threshold level The removal of the components will be performed properly.

[0037]

As is apparent from the above description, in the vertical synchronization signal processing circuit according to the present invention, the vertical synchronization signal is supplied to one end of the vertical synchronization signal supplied to the input terminal. A ground value clamp is performed by the capacitor element and the first diode, and the other end of the capacitor element to which the cathode side of the first diode is connected obtains a vertical synchronization signal having the base value clamped. The clamp level of the clamped vertical synchronization signal is
From the potential on the anode side of the first diode to the potential obtained by subtracting the forward voltage generated by the first diode during the base level period of the vertical synchronization signal supplied to the input terminal. When the synchronization signal has a positive polarity, an impedance element for lowering the potential on the anode side of the first diode is provided, so that the vertical synchronization signal supplied to the input terminal has a positive polarity and has a base level. Even when the duty ratio of the period is large and the forward voltage generated by the first diode is small during the base level period of the vertical synchronization signal supplied to the input terminal, the other end of the capacitor element The vertical synchronization signal to which the base value clamp is applied is obtained in the same manner as when the vertical synchronization signal supplied to the input terminal is of a negative polarity. Is intended to clamp level takes a proper value.

Therefore, based on a relatively simple configuration including an impedance element, when the vertical synchronizing signal supplied to the input terminal is of a negative polarity, and when the vertical synchronizing signal supplied to the input terminal is Regardless of whether the sync signal has a positive polarity or not, the base level clamped vertical sync signal obtained at the other end of the capacitor element and supplied to the polarity discriminator is output when the clamp level is normal. Can be taken.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a vertical synchronization signal processing circuit according to the present invention.

FIG. 2 is a waveform chart used for describing an operation in the example shown in FIG. 1;

FIG. 3 is a block diagram showing a conventionally proposed vertical synchronization signal processing circuit.

FIG. 4 is a waveform chart for explaining the operation of the vertical synchronization signal processing circuit shown in FIG. 3;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 21 Input terminal 22 Capacitor element 23, 25 Resistance element 24, 26 Diode 28 Signal processing part 29 Transistor

Claims (4)

(57) [Claims] 1. One end is connected to an input terminal to which a vertical synchronizing signal is supplied, and the other end is connected to a first terminal via a first resistance element .
A capacitor element connected to a reference potential point; a first diode having a cathode connected to the other end of the capacitor element and an anode connected to a second reference potential point via a second resistance element; side is connected to the anode side of the first diode, a second diode having a cathode side connected to the first reference potential point above, is connected to the other end of the capacitor element, resulting in the other end of the capacitor element A polarity discriminating unit for discriminating whether the vertical synchronizing signal to be outputted has a positive polarity or a negative polarity, and connected between an anode side of the first diode and the first reference potential point. A vertical synchronization signal in which a discrimination output signal from the polarity discrimination unit is obtained at the other end of the capacitor element.
When indicating that the signal is of positive polarity,
The vertical output signal is obtained at the other end of the capacitor element.
When the signal indicates that the signal is of negative polarity.
A vertical synchronization signal processing circuit comprising: an impedance element configured to reduce a potential on the anode side of the first diode. 2. The method according to claim 1, wherein the impedance element is an emitter-collector.
The first transistor path is connected to the anode side of the first diode and the first reference voltage.
Connected to the ground point and discriminated from the polarity discriminator on the base
The output signal is supplied by the transistor
Vertical synchronizing signal processing circuit according to claim 1, characterized in that it is configured. 3. A transistor according to claim 1, wherein said transistor determines whether or not said polarity is determined by said transistor.
A vertical synchronization signal where the force signal is obtained at the other end of the capacitor element
The above-mentioned determination is made when the
Vertical synchronization in which a force signal is obtained at the other end of the capacitor element
Compared to when it indicates that the signal is of negative polarity
To reduce the impedance value of the emitter-collector path.
Vertical synchronizing signal processing circuit according to claim 2, wherein the eggplant. 4. A polarity discriminating unit is provided at the other end of the capacitor element.
When the vertical sync signal is negative and positive
The discrimination output signal that changes the level
Vertical synchronizing signal processing circuit according to claim 1, 2 or 3 wherein generating a degree.