JP3262099B2 - Buffer layout design apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design apparatus and method for laying out a buffer in a semiconductor circuit.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 7, one kind of insertion buffer 101 is prepared, and this insertion buffer 101 is prepared.
Is inserted into the insertion space S101 irrespective of the surrounding wiring.

As a layout design apparatus, there is one disclosed in Japanese Patent Application Laid-Open No. 9-293094.
A layout design apparatus disclosed in Japanese Patent Application Laid-Open No. 9-293094 is a layout design apparatus for arranging circuit elements and wiring between circuit elements to design a layout of a logic circuit. A path delay analyzing means for performing a delay analysis process on a layout result obtained by performing the layout design, and, if a delay error exists in the layout result as a result of the delay analysis process, performing a logic change of a logic circuit to reduce the delay error. Relay buffer inserting means for solving the problem; and incremental wiring means for rewiring the layout result in accordance with the result of the logical change by the relay buffer inserting means.

[0004]

However, in the conventional technique shown in FIG. 7 and the layout design apparatus disclosed in Japanese Patent Application Laid-Open No. 9-293094, if a buffer is inserted into a congested place, wiring Short-circuit error, etc., and it is necessary to re-wire the wiring including the surrounding wiring.Moreover, if the route of other wiring changes, the delay changes and a new route that does not meet the timing occurs. There is a problem that it becomes easier.

SUMMARY OF THE INVENTION An object of the present invention is to provide a buffer layout design apparatus and method which can reduce the influence of the insertion net itself and the path of the peripheral wiring being different from those before rewiring at the time of rewiring after buffer insertion. It is in.

Another object of the present invention is to provide a buffer which can hardly change the delay of the wiring around the inserted buffer and reduce the number of wirings newly violating timing constraints after rewiring. A layout design apparatus and method are provided.

[0007]

In order to solve the above-mentioned problems, according to the present invention, there is provided an information processing apparatus comprising: a list of a plurality of types of insertion buffers to be arranged and selected in advance; A storage device storing layout wiring data including output pin position information and a parameter indicating a range of the buffer insertion position to be searched from the insertion point of the buffer to the extent to which the buffer is inserted; and a storage device connected to the storage device. A central processing unit, an operation input device connected to the central processing unit, which determines a buffer insertion net and a buffer insertion point, and inputs these data to the central processing unit; A buffer layout design device connected to the device and having a display device for displaying data from the central processing unit. The device searches the range before and after the buffer insertion point based on the data of the buffer insertion net and the buffer insertion point from the operation input device and the arrangement and wiring data of the storage device, and searches under the wiring of the buffer insertion net. Insertable space search means for determining whether or not there is a space into which a buffer can be inserted, and insertion when the insertable space search means determines that there is a space where a buffer can be inserted under the wiring of the buffer insertion net. The appropriate buffer determining means for determining whether there is a buffer having an appropriate pin for the buffer insertion net on the possible space and the design relating to the buffer insertion at the insertion point of one buffer are completed. For each time, the data relating to this design is stored in the storage device as the placement and routing data. And a wiring data updating means, the placement and routing data, characterized in that the each the buffer insertion net group to be processed consisting of the insertion position parameter and the search range parameters and inserted in the list of the target buffer data .

According to a second aspect of the present invention, there is provided a list of a plurality of types of insertion buffers selected in advance from information on arrangement and wiring,
A storage device for storing placement and wiring data including position information of input / output pins of these insertion buffers and a parameter indicating a range of the buffer insertion position to be searched from the insertion point of the buffer up to a predetermined range; A central processing unit connected to the storage device, and an operation input for determining a buffer insertion net and a buffer insertion point connected to the central processing unit and inputting these data to the central processing unit. In a buffer layout design device having a device and a display device connected to the central processing unit and displaying data from the central processing unit, the central processing unit includes a buffer insertion net and a buffer from the operation input device. Based on the data at the insertion point and the placement and routing data of the storage device, An insertable space search unit that searches the front and rear ranges to determine whether there is a space into which a buffer can be inserted under the wiring of the buffered insertion net, An appropriate buffer judging means for judging whether or not there is a buffer having an appropriate pin for the buffered net above the insertable space when it is judged that there is a space into which the buffer can be inserted; Temporary wiring means for temporarily inserting a buffer of a list of insertion buffers and performing temporary wiring when it is judged by the buffer judgment means that there is no buffer having an appropriate pin for the buffer insertion net on the insertable space And whether there is a buffer that did not short-circuit with other nets when temporary wiring was performed by the temporary wiring means A determination unit or the determining, each time the design for the insertion of the buffer for the insertion point one buffer has been completed, and a placement and routing data updating means for storing data relating to the design in the storage device as the placement and routing data, The placement and routing data is characterized by comprising an insertion position parameter, a search range parameter, and data of a list of buffers to be inserted for each buffered net to be inserted to be processed.

According to a third aspect of the present invention, there is provided a list of a plurality of types of insertion buffers selected in advance from information on arrangement and wiring,
A storage device for storing placement and wiring data including position information of input / output pins of these insertion buffers and a parameter indicating a range of the buffer insertion position to be searched from the insertion point of the buffer up to a predetermined range; A central processing unit connected to the storage device, and an operation input for determining a buffer insertion net and a buffer insertion point connected to the central processing unit and inputting these data to the central processing unit. In a buffer layout design method for a buffer layout design device having a device and a display device connected to the central processing unit and displaying data from the central processing unit, the central processing unit inserts a buffer to be input from the operation input device. Based on net and buffer insertion point data and storage device placement and routing data Searching the range before and after the insertion point of the buffer to determine whether there is a space in which the buffer can be inserted under the wiring of the buffer insertion net; Determining whether there is a buffer having an appropriate pin for the buffer insertion net above the insertable space when it is determined that there is a space in which the buffer can be inserted; each time the design for an insertion of a buffer for the insertion point is completed, and a step of storing data relating to the design in the storage device as the placement and routing data, place and route data
Is the insertion position for each buffered net to be processed
Parameters and search range parameters and insertion target buffers
And a list of key lists.
I do.

[0010] According to a fourth aspect of the present invention, there is provided a list of a plurality of types of insertion buffers to be selected in advance and information of placement and wiring,
A storage device for storing placement and wiring data including position information of input / output pins of these insertion buffers and a parameter indicating a range of the buffer insertion position to be searched from the insertion point of the buffer up to a predetermined range; A central processing unit connected to the storage device, an operation input device connected to the central processing unit to determine a buffered net to be inserted and a buffer insertion point, and input these data to the central processing unit; A buffer layout design device connected to the central processing unit and having a display device for displaying data from the central processing unit, wherein the central processing unit includes a buffer insertion net from the operation input device; Based on the data at the buffer insertion point and the placement and wiring data in the storage device, A step of searching the range before and after the insertion point of the buffer to determine whether there is a space where a buffer can be inserted under the wiring of the buffered net; Determining whether there is a buffer having an appropriate pin for the buffer insertion net on the insertable space when it is determined that there is a space into which the buffer can be inserted, and a central processing unit Tentatively inserts a buffer in the list of insertion buffers and performs tentative wiring when it is determined that there is no buffer having an appropriate pin for the buffer insertion net on the insertable space. The central processing unit determines whether there is a buffer that has not short-circuited with another net when the buffer exists. Each time the design for an insertion of buffers for Ffa insertion point is completed, characterized by a step of storing data relating to the design in the storage device as the placement and routing data.

[0011]

Next, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, a buffer layout design device 1 according to a first embodiment of the present invention includes a storage device 2, a central processing unit 3, an operation input device 4, and a display device 5. The storage device 2, the operation input device 4, and the display device 5 are connected to the central processing unit 3. The buffer insertion device 6 is connected to the central processing unit 3.

The storage device 2 includes a list of placement and wiring information, a list of a plurality of types of insertion buffers to be selected, input / output pin position information of these insertion buffers, and a buffer insertion point. For the buffer insertion position is stored. The operation input device 4 is for the user to determine the buffer insertion net and the insertion point of the buffer, input these data, and give them to the central processing unit 3.

The central processing unit 3 has an insertable space search unit, an appropriate buffer determination unit, and a placement and routing data update unit. The insertable space search unit searches the range before and after the insertion point of the buffer based on the data of the buffer insertion net and the insertion point of the buffer from the operation input device 4 and the arrangement and wiring data of the storage device 2, and It is determined whether there is a space under the wiring of the insertion net where a buffer can be inserted. When the insertable space search unit determines that there is a space in which a buffer can be inserted below the wiring of the buffered net, the appropriate buffer determining unit determines an appropriate pin for the buffered insertion net on the insertable space. It is determined whether or not there is a buffer having a. The placement and routing data update unit
Each time a design relating to buffer insertion at one buffer insertion point is completed, data relating to this design is stored in the storage device as placement and wiring data.

The display device 5 displays data of the central processing unit 3 based on an instruction signal of the operation input device 4. The buffer insertion device 6 inserts a buffer into a predetermined position (space) of the semiconductor circuit according to the design data that is the operation result of the central processing unit 3.

In the buffer layout design apparatus 1 shown in FIG. 1, for example, as shown in FIG. 2A, a buffer insertion net is N1, a buffer insertion space is S,
As shown in FIG. 2B, the list b of the insertion buffer is set to b.
When the numbers are 1, b2, and b3, the design is such that b1 of the list b of the insertion buffer is selected and inserted into the buffer insertion space S as shown in FIG. When the buffer is inserted, the buffered net N1 is divided into nets N21 and N22 that are connected to the input / output terminals of the buffer and have been subjected to the buffer insertion process. The insertion buffer list b is not limited to the list shown in FIG. 2 and is a list of buffers having input / output pins at various positions. In FIG. 2 and FIG. 5, since the wirings in the vertical and horizontal directions and the terminals of the blocks exist in different wiring layers, no short circuit occurs even if they intersect.

Next, the operation of the buffer layout designing device 1 and the buffer inserting device 6 will be described with reference to FIGS.
This will be described in detail with reference to FIG. In step A1 of FIG. 4, the placement and wiring data is stored in the storage device 2. The placement and routing data includes placement and routing information, a list of a plurality of types of insertion buffers to be selected, input / output pin position information of these insertion buffers, and the extent to which the buffer is to be inserted. And whether to search for the buffer insertion position.

Next, in step A2, the user determines a buffer insertion net and a buffer insertion point, inputs these data through the operation input device 4, and gives the data to the central processing unit 3. Next, in step A3, the central processing unit 3 searches the range before and after the buffer insertion point based on the data of the buffer insertion point and the arrangement and wiring data of the storage device 2 (see FIG. 3). It is determined whether there is a space under the wiring of the buffer insertion net where a buffer can be inserted. In step A4, when there is a space under the wiring of the buffer insertion target net where a buffer can be inserted,
In step A5, the central processing unit 3 assigns appropriate pins to the buffered insertion net on the insertable space based on the data of the buffered insertion net and the buffer insertion point and the layout data of the storage device 2. It is determined whether or not there is a buffer held. In step A4, if information that can be inverted and rotated exists in the insertion buffer and the insertion space, this information is also considered in the search.

In step A5, when there is a buffer having appropriate pins for the buffer insertion net on the insertable space, in step A6, the buffer insertion unit 6 transmits the design data from the central processing unit 3 to the buffer. Then, an appropriate buffer is inserted into the insertable space on the basis of the buffer, and the net is divided before and after the buffer.
Go to 9. If there is a buffer having an appropriate pin for the buffer insertion net on the insertable space in step A5, in step A7, the central processing unit 3 determines whether or not the entire search range has been searched. Judge. If it is determined in step A7 that the search has not been performed for the entire search range, the process returns to step A3.

In step A4, when there is no space under which the buffer can be inserted under the wiring of the buffer insertion net, and when the search is performed in the entire search range in step A7, the buffer insertion device 6 performs the conventional operation in step A8. After performing the buffer insertion process, the process proceeds to step A9. In step A9, the central processing unit 3 determines whether or not the processing has been completed for the buffer insertion net for the insertion point of one buffer. If the processing has not been completed for the buffer insertion net for one buffer insertion point in step A9, the process returns to step A2. When the processing for the buffer insertion net for one buffer insertion point is completed in step A9, the central processing unit 3 in step A10 uses the data relating to the design of the buffer insertion as the layout data in the storage device 2
To memorize.

Next, in step A11, the central processing unit 3 determines whether or not the processing has been completed for the buffer insertion nets for the insertion points of all the buffers. If the processing has not been completed for the buffer insertion nets for all the buffer insertion points in step A11, the flow returns to step A2. When the processing has been completed for the buffer insertion nets for all the buffer insertion points in step A11, the central processing unit 3 determines in step A12 whether or not step A8 has been performed. Step A12
If it is determined in step A8 that step A8 has been performed, an ECO process is performed in step A13, and the operation ends. If it is not determined in step A12 that step A8 has been performed, the operation ends.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. In the second embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals. As shown in FIG. 1, a buffer layout design apparatus 1 according to a second embodiment of the present invention
Is a storage device 2, a central processing unit 3, and an operation input device 4.
And a display device 5. The storage device 2, the operation input device 4, and the display device 5 are connected to the central processing unit 3. The buffer insertion device 6 is connected to the central processing unit 3.

In the buffer layout designing apparatus 1 according to the second embodiment of the present invention, for example, FIG.
As shown in FIG. 5 (C), when the buffer insertion net is N1, the buffer insertion space is S, and the insertion buffer list b is b1, b2, b3 as shown in FIG. 5 (B). As shown in FIG. 5, b2 of the insertion buffer list b is selected and temporarily inserted into the buffer insertion space S.
As shown in (D), the temporary wiring is performed and the wiring is changed if there is no short circuit. When the buffer is inserted, the buffer-inserted net N1 is divided into nets N21 and N22 that are connected to the input / output terminals of the buffer and that have been subjected to the buffer insertion process.

Next, a buffer layout designing apparatus 1 and a buffer inserting apparatus 6 according to a second embodiment of the present invention.
Will be described in detail with reference to FIGS. 1 and 4 together with FIG. FIG. 6 shows a flow for explaining the operation of the buffer layout design device 1 as the second embodiment of the present invention. In FIG. 6, steps B1 and B2 are added to the flow of FIG. Step B added
1, B2 will be described.

In step A5, when there is no buffer having an appropriate pin for the buffer insertion net on the insertable space, the buffer of the list of insertion buffers is temporarily inserted by the buffer insertion device 6 in step B1. Perform temporary wiring. Next, in step B2, the central processing unit 3 determines whether or not there is a buffer in which a short has not occurred with another net. If a plurality of buffers correspond to each other in the determination in step B2, the length of the wiring route, the length of the portion adjacent to another wiring, etc.
It is preferable to use a selection process such as selecting one that minimizes the influence of the delay on the surroundings. If there is a buffer that has not been short-circuited with another net in step B2, the process goes to step A6. If there is no buffer in which no short-circuit has occurred with another net in step B2, the flow proceeds to step A7.

In the above embodiment of the present invention, the placement and routing data may be constituted by an insertion position parameter, a search range parameter, and a list of buffers to be inserted for each buffered net to be inserted to be processed.

In the above embodiment of the present invention, it is possible to reduce the influence that the route of the insertion net itself and the peripheral wiring is different from that before the rewiring at the time of the rewiring after the buffer is inserted.

In the above embodiment of the present invention,
The delay of peripheral wiring hardly changes,
After the rewiring, the number of wires that violate the timing constraint newly decreases, and the number of times of performing the buffer insertion process can be reduced.

Further, in the above embodiment of the present invention, by selecting an insertion buffer having an optimum pin arrangement in consideration of the result of the already arranged wiring, the path change at the time of rewiring can be reduced. Can be.

[0029]

According to the present invention, it is possible to reduce the influence that the route of the insertion net itself and the peripheral wiring is different from that before the rewiring at the time of the rewiring after the buffer is inserted.

Further, according to the present invention, the delay of the wiring around the inserted buffer hardly changes, and the number of wirings newly violating the timing constraint after rewiring can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a buffer layout design device according to a first embodiment of the present invention.

FIG. 2 is a diagram for explaining an example of the operation of the buffer layout design device of FIG. 1;

FIG. 3 is a diagram for explaining another example of the operation of the buffer layout design device of FIG. 1;

FIG. 4 is a flowchart for explaining the operation of the buffer layout design device of FIG. 1;

FIG. 5 is a diagram illustrating an example of an operation of a buffer layout design device as a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating an operation of a buffer layout design device according to a second embodiment of the present invention.

FIG. 7 is a diagram for explaining an example of the operation of a conventional buffer layout design device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer layout design device 2 Storage device 3 Central processing unit 4 Operation input device 5 Display device 6 Buffer insertion device

Claims (4)

(57) [Claims] 1. A list of a plurality of types of insertion buffers selected in advance from information on arrangement and wiring, and a range from the position information of input / output pins of these insertion buffers and the insertion point of the buffers to the extent of the front and rear. A storage device storing arrangement and wiring data including a parameter indicating whether to search for a buffer insertion position, a central processing unit connected to the storage device, and a buffered connection connected to the central processing unit. An operation input device for determining an insertion point of a net and a buffer and inputting the data to the central processing unit; and a display connected to the central processing unit and displaying data from the central processing unit A buffer layout design device having a device, wherein the central processing unit is configured to insert the buffer to be inserted from the operation input device. A space in which a buffer can be inserted under the wiring of the buffer insertion net by searching a range before and after the insertion point of the buffer based on the data of the insertion point of the buffer and the buffer and the arrangement and wiring data of the storage device. An insertable space search means for determining whether or not to insert a buffer, when the insertable space search means determines that there is a space into which a buffer can be inserted under the wiring of the buffered insertion net; Suitable buffer determining means for determining whether or not there is a buffer having an appropriate pin for the buffer insertion net; and Placement and routing data for storing design related data in the storage device as the placement and routing data And a data updating means, the placement and routing data is characterized in that it is intended to each be buffer insertion net group to be processed consisting of the insertion position parameter and the search range parameters and inserted in the list of the target buffer data Buffer layout design equipment. 2. A list of a plurality of types of insertion buffers selected in advance from placement and routing information, and input / output pin position information of these insertion buffers and the insertion point of the buffer, to what extent before and after the buffer. A storage device storing arrangement and wiring data including a parameter indicating whether to search for a buffer insertion position, a central processing unit connected to the storage device, and a buffered connection connected to the central processing unit. An operation input device for determining an insertion point of a net and a buffer and inputting the data to the central processing unit; and a display connected to the central processing unit and displaying data from the central processing unit A buffer layout design device having a device, wherein the central processing unit is configured to insert the buffer to be inserted from the operation input device. A space in which a buffer can be inserted under the wiring of the buffer insertion net by searching the range before and after the insertion point of the buffer based on the data of the insertion point of the buffer and the buffer and the arrangement and wiring data of the storage device. An insertable space search means for determining whether or not to insert a buffer, when the insertable space search means determines that there is a space into which a buffer can be inserted under the wiring of the buffered insertion net; Suitable buffer determining means for determining whether or not there is a buffer having an appropriate pin for the buffer-inserted net, and the buffer-inserted net on the insertable space by the appropriate buffer determining means. When it is determined that there is no buffer having an appropriate pin for the Temporary wiring means for temporarily inserting a temporary buffer and performing temporary wiring; determining means for determining whether or not there is a buffer that has not been short-circuited with another net when the temporary wiring is performed by the temporary wiring means; each time the design for an insertion of buffers for one buffer insertion point is completed, and a placement and routing data updating means for storing data relating to the design in the storage device as the placement and routing data, the placement and routing data, A buffer layout design apparatus comprising an insertion position parameter, a search range parameter, and data of a list of buffers to be inserted for each of the buffer insertion net groups to be processed. 3. A list of a plurality of types of insertion buffers selected in advance from placement and routing information, and input / output pin position information of these insertion buffers and the insertion point of the buffer, to what extent before and after the range. A storage device storing arrangement and wiring data including a parameter indicating whether to search for a buffer insertion position, a central processing unit connected to the storage device, and a buffered connection connected to the central processing unit. An operation input device for determining an insertion point of a net and a buffer and inputting the data to the central processing unit; and a data display unit connected to the central processing unit for displaying data from the central processing unit A buffer layout design method for a buffer layout design device having a display device, wherein the central processing unit is configured to perform the operation input. A search is made for a range before and after the insertion point of the buffer based on the data of the buffer insertion net and the insertion point of the buffer from the buffer and the placement and wiring data of the storage device, and a buffer is inserted under the wiring of the buffer insertion net. Determining whether there is a space in which a buffer can be inserted; and determining that there is a space in which a buffer can be inserted under the wiring of the buffered insertion net when the central processing unit determines that there is a space in which the buffer can be inserted. Determining whether or not there is a buffer having an appropriate pin for the above buffered net to be inserted; and each time the design for inserting a buffer at the insertion point of one buffer is completed, data and a step of storing in the storage device as the placement and routing data, said Place and route data, the buffer insertion network to be processed
Parameters and search range parameters for each group
And data from the list of buffers to be inserted
A buffer layout design method. 4. A list of a plurality of types of insertion buffers selected in advance from information on arrangement and wiring, a position information of input / output pins of these insertion buffers and an insertion point of the buffer, to what extent before and after. A storage device storing arrangement and wiring data including a parameter indicating whether to search for a buffer insertion position, a central processing unit connected to the storage device, and a buffered connection connected to the central processing unit. An operation input device for determining insertion points of a net and a buffer and inputting the data to the central processing unit; and a display device connected to the central processing unit and displaying data from the central processing unit Wherein the central processing unit is the operation input device. Searching the range before and after the insertion point of the buffer based on the data of the buffer insertion net and the buffer insertion point and the placement and wiring data of the storage device, and inserting a buffer below the wiring of the buffer insertion net. Judging whether or not there is a possible space; and when the central processing unit judges that there is a space into which a buffer can be inserted under the wiring of the buffered net, Determining whether there is a buffer having an appropriate pin for the buffered insertion net; and determining whether the central processing unit is appropriate for the buffered insertion net on the insertable space. When it is determined that there is no buffer having a new pin, the buffer of the insertion buffer list is temporarily inserted and temporarily inserted. Performing the wiring; and determining whether there is a buffer in which the central processing unit did not short-circuit with another net when the provisional wiring was performed. Storing the data relating to the design as the placement and routing data in the storage device each time the design relating to the insertion is completed.