JP3260010B2 - Charge coupled device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge-coupled device using a ferroelectric.

[0002]

2. Description of the Related Art A semiconductor memory is changed from a storage state to a RAM.
(Random Access Memory) and SAM (Sequential Acces)
s Memory), which are in principle reduced from storage operation to RWM (Read Write Memory) and ROM (Rea
d Only Memory), which does not require power to maintain the stored contents, does not lose the stored contents even when the power is turned off, and is a non-volatile memory, requires power to maintain the stored contents, and is stored when the power is turned off. Those that lose their contents are called volatile memory.

[0003] Among them, the RWM RAM is generally called "RAM", and the "RAM" is further divided into a static RAM (SRAM) and a dynamic RAM (DRAM) according to driving means. The SRAM is composed of a flip-flop circuit, and it is difficult to increase the degree of integration because of its complicated structure. However, since the storage state can be maintained with low power, the power consumption is low and the write / read operation is performed. Is fast.

On the other hand, a DRAM is composed of a capacitor as a storage unit and a transistor as an active unit for controlling the storage unit. An update operation called refresh is performed to maintain the charge stored in the capacitor. Although it has the disadvantage of relatively high power consumption because of its necessity, it has the advantage that the degree of integration can be increased due to the simple structure of the memory cell, and is widely used as a main storage device of a computer. .

On the other hand, ROM which is a non-volatile memory which does not require power for storage maintenance includes a mask ROM in which information is written at a manufacturing stage and a PROM (Programmable ROM) in which a user can write information later. . EPROM (UV-Erasable) which performs writing to this PROM electrically and erases it by irradiating it with ultraviolet rays.
PROM) and EEPROM for electrically writing / erasing
(Eletrically-Erasable PROM).

A semiconductor storage device used as an internal storage device of a computer or the like includes a ROM or DR which is a random accessory memory because of the operation of the computer.
AM is used, and no sequential access memory is used. However, in recent years, audio signals or video signals have been digitized and stored in a semiconductor memory in a television, an answering machine or a facsimile machine, and the control of writing / reading is simple. A sequential access memory is used as a storage device.

By the way, a charge coupled device (CCD: Charge) is used as a semiconductor device capable of performing a storage operation for accumulating electric charges and capable of sequentially transferring and reading out the accumulated electric charges.
Coupled Device) is known. This CCD is mainly used in facsimile machines or video cameras.
It is used to convert a linear or planar data written by light into a facsimile signal or a video signal by sequentially reading the data.

FIG. 1A shows a CC in which elements are linearly arranged.
2 shows a general structure and electrical connection relationship of D. Semiconductor single crystal substrates used for CCDs are in principle P-type and N-type.
Any type can be used, but since it is more convenient to use electrons as the carrier to transfer, a P-type single crystal substrate that easily uses electrons is often used. Therefore, the CCD shown here also uses a P-type substrate.

A CCD, which is a MOSFET having a large number of gate electrodes, has an n ⁺ source region 2 and an n ⁺ drain region 3 formed on the surface of a p-type silicon substrate 1 and covers the entire silicon substrate 1 and is made of silicon oxide. A gate insulating film 4 is formed, on which a source electrode S, an input gate electrode G _I , charge transfer gate electrodes G ₁ , G ₂ , G ₃ ... And an output gate electrode G _O , a reset electrode _RS, and a drain electrode. D are arranged in one row.

[0010] Of these electrodes, the source electrode S and the drain electrode D are formed directly on the P-type silicon substrate 1 without interposing a silicon oxide insulating film. Further, the source electrode S and the input gate electrode G on the surface of the P-type silicon substrate
_An n ⁺ source region 2 is provided between the gate electrode I and an n ⁺ drain region 3 between the reset electrode _RS and the drain electrode D. Similarly, an n ⁺ floating diffusion layer 5 is provided between the output gate electrode G _O and the reset electrode R _S.

The source electrode S of the CCD is grounded, and the drain electrode D is connected to a positive power supply. The charge transfer gate electrodes are divided into three groups. The charge transfer gate electrodes G ₁ , G ₄ , G _7, ... Constitute a _first phase group Φ _1, and the charge transfer gate electrodes G ₂ , G ₅ ,. G ₈ ... Are the second phase group Φ _2, and the charge transfer gate electrodes G ₃ ,
G ₆ , G _9, ... Are a group Φ ₃ of the third phase . The input gate electrode G _I is connected to an input signal source, and the output gate electrode G _O is connected to an output load.

A voltage waveform applied to each group of the charge transfer gate electrodes of the CCD shown in (a) and electrically connected as shown in (a) is shown in (b). The first phase group Φ ₁ has a clock pulse of φ ₁ waveform, the second phase group Φ ₂ has a clock pulse of φ ₂ waveform,
Clock pulses having a waveform of φ ₃ are applied to the phase group Φ ₃ , and these clock pulses are applied to the first phase group Φ ₁ , the second phase group Φ ₂ , and the third phase group Φ _3.
Are sequentially applied. Electrically or optically electrons are injected into the input gate electrode G ₁ by a pulse voltage as shown in the figure, the potential indicated by a broken line in which the clock pulses to each group is formed when it is applied by a clock pulse The injected electrons are transferred as the well moves.

In the CCD having such a configuration, the electrons injected into the input gate electrode G ₁ are gradually diffused into the P-type silicon substrate 1 and are lost. Therefore, the injected charges cannot be stored. In order to store the injected charge, it is conceivable to form a dielectric layer made of, for example, SiN _x in addition to the gate insulating film between the input gate and the silicon substrate. It cannot be increased. Therefore, in order to store the audio signal or the video signal which is data suitable for sequential access as described above, a storage device capable of sequential access is required in addition to the CCD as a data processing device. .

By the way, in recent years, a ferroelectric thin film is used instead of SiN _x as a dielectric of a capacitor used in a storage unit in combination with a MOS field effect transistor (MOSFET) in a DRAM, and this ferroelectric is polarized. The RAM for performing the storage operation by FRAM (Fe
It is called rroelectric RAM), which is non-volatile because it does not require power to maintain the memory while it is a RAM, it is suitable for integration because of its simple structure, it can be driven at low voltage, Time required 240ns
５００500 ns, which is shorter than EPROM,
Attention has been paid to a storage device replacing the RAM or the HDD.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and reduces the number of components of the entire apparatus by performing sequential data storage operation using a CCD which is a sequential data processing apparatus. The purpose is to let them. In order to achieve this object, in a CCD according to the present invention, a gate insulating film between an input gate electrode and a P-type silicon substrate is formed using a ferroelectric material.
With this configuration, it is possible to store the charge injected into the input gate electrode for a long time.

[0016]

An embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows a first embodiment of the ferroelectric charge transfer device according to the present invention. The ferroelectric charge transfer device of the first embodiment is similar to the conventional charge transfer device shown in FIG.
A source electrode S and charge transfer gate electrodes G ₁ , G ₂ , G are formed on a gate insulating film 2 made of silicon oxide formed on the surface of a P-type silicon substrate 1. ₃ and an output gate electrode G _O (not shown) , a reset electrode R _S (not shown), and a drain electrode D (not shown) are arranged in one row.
Although the control gate electrode G _C instead of the input gate electrode G _I is disposed between the source electrode S and the charge transfer gate electrodes G _1, the control gate electrode G _C is an input gate electrode G _I of the prior art In contrast, it is formed not directly on the gate insulating film 2 but via a ferroelectric film 6 formed on the gate insulating film.

Further, the source electrode S and the drain electrode D are formed directly on the P-type silicon substrate 1 without interposing a silicon oxide insulating film. An n ⁺ source region 2 is provided between the source electrode S and the input gate electrode G _{C on} the surface of the P-type silicon substrate, and an n ⁺ drain region is provided between the reset electrode and the drain electrode (not shown). I have.
Similarly, an n ⁺ floating diffusion layer 4 is provided between the output gate electrode G _O and the reset electrode R _S.

The source electrode S of the CCD is grounded, and the drain electrode D is connected to a positive power supply. The charge transfer gate electrodes are divided into three groups. The charge transfer gate electrodes G ₁ , G ₄ , G _7, ... Constitute a _first phase group Φ _1, and the charge transfer gate electrodes G ₂ , G ₅ ,. G ₈ ... Are the second phase group Φ _2, and the charge transfer gate electrodes G ₃ ,
G ₆ , G _9, ... Are a group Φ ₃ of the third phase . The input gate electrode G _C is the control signal source, the output gate electrode is connected to the output load.

The voltage shown in FIG. 1B is applied to each of the groups of the charge transfer gate electrodes of the CCD shown in FIG. 1A and thus electrically connected as in the prior art. . Clock pulse voltage to the group [Phi ₁ of the first phase phi ₁ the waveform, a clock pulse voltage to a group [Phi ₂ of the second phase phi ₂ waveforms, in the group [Phi ₃ of the third phase of phi ₃ A clock pulse voltage having a waveform is applied, and these voltages are sequentially applied to the first phase group Φ ₁ , the second phase group Φ ₂ , and the third phase group Φ ₃ . Electrons are electrically or optically injected into the control gate electrode G _C by a pulse voltage as shown in the figure, and when the clock pulse is applied to each group, the potential well formed by the clock pulse moves according to the movement of the potential well. The injected electrons are transferred.

The electrons injected into the input gate electrode G ₁ in the CCD of the first embodiment thus configured ferroelectric layer
6 is preserved by polarization. This charge is transferred by injecting a charge opposite to the accumulated charge, so that the electrons are transferred by a potential well where the electrons move.

FIG. 3 shows a second embodiment of the ferroelectric charge transfer device according to the present invention. The ferroelectric charge transfer device of this embodiment is different from the conventional example shown in FIG. 1 and the ferroelectric charge transfer device of the first embodiment of the present invention shown in FIG. On the other hand, it is composed of first and second two MOSFETs having many gate electrodes. Further, the control gate electrode G _C and the ferroelectric layer 6 are arranged between the gate electrode G ₃ of the first MOSFET and the gate electrode G ₄ of the second MOSFET, and the gate electrode G ₄ and the control gate electrode the source region 8 is formed between the G _C is, the drain region 7 is provided between the control gate electrode G _C and the gate electrode G _3. Further, the first MOSFET is provided with an input gate electrode G _I (not shown) as in the conventional example.

[0022] In the ferroelectric charge transfer device of the second embodiment constructed in this manner, electrons transferred through the input gate electrode G _I gate electrode is implanted in G _{1, G 2,} G ₃ is a ferroelectric The transfer is stopped by polarizing the body layer 6 and is preserved. This charge is transferred by injecting a charge opposite to the stored charge into the control gate electrode G _C , whereby electrons are transferred through a potential well where the electrons move.

[0023]

As is apparent from the above description, the ferroelectric CCD having the structure of the present invention and operating.
Can store the injected charge and, when reading out the data, read out the data at any time by inputting a read signal to the control gate electrode. As its use, there is no need to perform random access because the data is sequential,
The present invention can be applied to an audio memory, a video memory, and the like.

[Brief description of the drawings]

FIG. 1 is a structural explanatory diagram and an electric signal waveform diagram of a conventional example.

FIG. 2 is a structural explanatory view of the first embodiment of the present invention.

FIG. 3 is a structural explanatory view of a second embodiment of the present invention.

[Explanation of symbols]

1 P-type silicon substrate 2, 7 a source region 3,8 drain region 4 gate insulating film 5 floating diffusion layer 6 ferroelectric layer _{G 1, G 2, G 3} ··· gate electrode G _I input gate electrode G _O output gate Electrode G _C control gate electrode

Claims (2)

(57) [Claims] 1. A plurality of gate electrodes are provided on a silicon oxide insulating film formed on a silicon substrate, one of the gate electrodes serving as an input gate electrode, and the other gate electrode serving as a first phase and a second phase. And a third phase charge transfer gate electrode, wherein a ferroelectric film is formed between the input gate electrode and the silicon oxide insulating film. 2. A semiconductor device comprising: a plurality of gate electrodes provided on a silicon oxide insulating film formed on a silicon substrate; one of the gate electrodes serving as an input gate electrode; and the other gate electrode serving as a first phase and a second phase and the third phase charge transfer a charge coupled device which is a gate electrode, the following further control gate electrode of the third phase charge transfer gate electrode provided between the control gate electrode and the silicon oxide insulating film A ferroelectric film is formed on the charge coupled device.