JP3256128B2 - Light receiving / emitting diode array chip, light receiving / emitting diode array using the chip, and method of manufacturing the chip - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting and receiving diode array chip, a light emitting and receiving diode array using the chip, and a method of manufacturing the chip. The light receiving and emitting diode in the present invention means a light receiving diode and a light emitting diode.

[0002]

2. Description of the Related Art Light-emitting diode arrays are used, for example, as light sources for electrophotographic optical printers. Such a light emitting diode array is usually configured by arranging a large number of light emitting diode array chips in a straight line. Here, the light emitting diode array chip (hereinafter, “chip”)
Also called. ) Is a base made of a compound semiconductor of the first conductivity type, a number of impurity diffusion regions of the second conductivity type formed on the base at a predetermined pitch, individual electrodes for each impurity diffusion region, and a plurality of impurity diffusion regions. And a common common electrode. Each of the impurity diffusion regions in the chip often has a square planar shape, and the individual electrodes are connected to the regions by using a part of the impurity diffusion region (for example, see Japanese Unexamined Patent Application Publication No. 58-66370). A drive current is selectively supplied to each individual electrode from a constant current drive circuit provided in the drive IC. In the impurity diffusion region to which the drive current has been supplied, light emission occurs at the pn junction.

[0003]

By the way, a driving IC used for driving a light emitting diode array includes:
The output current can be controlled to a value within an allowable range up to a certain level of load resistance to the output terminal, but as long as the drive voltage of the IC is constant, the output current sharply decreases when the load resistance exceeds a certain value. . This is shown in FIG. In FIG. 12, the horizontal axis represents the load resistance (relative value) to the output terminal of the driving IC, and the vertical axis represents the driving IC.
Is the output current (relative value). FIG 12 As is apparent from, becomes a value R _X with a load resistance to the drive IC, the output current of the driving IC is rapidly lowered.

Here, as one factor for determining the load resistance for the driving IC, there is a contact resistance between the impurity diffusion region and the individual electrode in the light emitting diode array. One of the major factors that determine the contact resistance is the contact area between the impurity diffusion region and the individual electrode. Since the above contact resistance increases as the contact area decreases, the load resistance to the driving IC also increases. Therefore, if the contact area between the individual electrode and the impurity diffusion region is too small,
That is, if the contact area is reduced to such an extent that the load resistance to the driving IC exceeds the above-mentioned R _X , there arises a problem that the light emitting diode cannot be driven with a desired driving current.

On the other hand, there is a growing demand in the industry for a technique capable of forming high-quality images. Therefore, the appearance of a light receiving and emitting diode array with higher resolution is desired. However, the higher the resolution of the light emitting and receiving diode array, the narrower the pitch of the impurity diffusion regions must be. Therefore, the area of each impurity diffusion region is naturally reduced accordingly. As a result, the contact area between the impurity diffusion region and the individual electrode is reduced. Therefore, in the conventional structure in which the individual electrode is connected to the impurity diffusion region simply by using a part of the impurity diffusion region, the above-mentioned problem becomes remarkable as the resolution increases, so that the resolution can be increased. Naturally there are limits.

[0006] Even if the impurity diffusion region (also referred to as a light emitting / receiving section) is miniaturized with the increase in resolution of the light receiving / emitting diode array, a new structure capable of setting the contact resistance between the light emitting / receiving section and the individual electrode to a desired value. The advent of light receiving and emitting diode array chips is desired.

[0007]

[0008]

Further, as the resolution of the light emitting and receiving diode array increases, the area of each impurity diffusion region 3 becomes smaller. In such a case, if it is assumed that the positioning accuracy of the photomask used for forming the individual electrode is the same as the conventional one, the misalignment of the photomask greatly affects the impurity diffusion region 3. Is difficult to connect as desired. Improvement is also desired.

[0010]

According to a first aspect of the present invention, there is provided a base made of a compound semiconductor of the first conductivity type and a plurality of bases formed on the base at a pitch corresponding to a required resolution. In a light emitting and receiving diode array chip having a second conductivity type impurity diffusion region and a group of individual electrodes individually connected to these impurity diffusion regions, each impurity diffusion region is used as a light receiving and emitting unit. First
In relation to the first region of the other impurity diffusion region, the first region arranged at the pitch and the second region mainly used as a connection portion with the individual electrode. A second region which is continuous with the first region in a direction orthogonal to the arrangement direction and has at least an area where a desired contact can be made with the individual electrode (an area where a desired contact resistance is obtained). And the second region of each of the odd-numbered impurity diffusion regions among the impurity diffusion regions is a region on one side of the base divided by an array line of the first region. And the second region of each even-numbered impurity diffusion region is arranged on the other side of the base divided by the array line. Characterized that you have.

According to the first aspect of the invention, since there is no individual electrode on the first region used as the light emitting / receiving section, a decrease in aperture ratio due to the individual electrode of the light emitting / receiving section is prevented. You. Further, since the second region is mainly used as a connection portion of the individual electrode, the contact area between the impurity diffusion region and the individual electrode can be increased accordingly. In addition, the second region of the odd-numbered impurity diffusion region and the second region of the even-numbered impurity diffusion region
Are arranged in separate base regions with the arrangement line interposed therebetween, so that the pitch of the odd-numbered (even-numbered) second region in the arrangement direction is twice the pitch of the first region. And can be. Therefore, it is possible to make the dimension of the second region along the arrangement direction larger than that of the first region.

[0012]

Further, according to the second invention of this application, in manufacturing a light emitting and receiving diode array, a photomask is used as a photomask for forming an individual electrode with respect to a region of the impurity diffusion region to be connected to the individual electrode. It is characterized in that a photomask is used in which the pattern for the individual electrode is extended by an amount that takes into account the amount of misalignment that may occur during alignment. According to the second aspect of the present invention, the individual electrode can be formed such that any portion thereof is located on a region of the impurity diffusion region to be connected to the individual electrode if the photomask shift is within the allowable range.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. However,
The drawings used in the description are merely schematic representations for understanding the present invention. Further, in each of the drawings, the same components are denoted by the same reference numerals, and the duplicate description thereof may be omitted. In the following description, an example in which each invention of the present application is applied to a light-emitting diode array chip (hereinafter, sometimes referred to as a “chip”), which is one type of light-receiving and emitting diodes, will be described.

1. 1. Description of chip and light emitting diode array 1-1. First Embodiment FIG. 1 is a plan view of a main part for describing a configuration of a chip according to an embodiment, and FIG. 2A is a plan view showing an enlarged portion Q in FIG. 2B is a cross-sectional view of the portion shown in FIG. 2A taken along line II in FIG. 2A (however, a cross-sectional view showing only the cut end). Also,
FIG. 3 is an explanatory view mainly showing the planar shape of the first region 15a, and FIG.
5 is an explanatory view mainly showing the planar shape of the second region 15b, FIGS. 5 and 6 are explanatory views showing the positional relationship between the second region 15b and the individual electrodes 17, and FIG. 7 is a modification of the arrangement example of the impurity diffusion regions 15. It is explanatory drawing of an example.

In FIG. 1, reference numeral 11 denotes a base made of a compound semiconductor of the first conductivity type, 13 denotes a diffusion mask, 13a denotes an opening of the diffusion mask, 15 denotes an impurity diffusion region of the second conductivity type,
17 denotes an electrode (individual electrode) on the second conductive side, and 17a denotes a pad portion of the individual electrode. In FIG. 2B, reference numeral 19 denotes a common electrode. Note that, in FIG. 1, a portion 17 of individual electrode 17
c (contact portion 17c) is hatched to clarify it (the same applies to FIGS. 2 to 6 below).

The underlayer 11 is not limited to this, for example,
It can be composed of a base composed of an n-type GaAs substrate and a GaAsP layer or a GaAlAs layer epitaxially grown on the substrate.

The diffusion mask 13 is used as a mask when forming the impurity diffusion region 15 at the stage of manufacturing the chip, and is used as an insulating film for separating dots after completion of the chip. The diffusion mask 13 has an opening 13a at a portion substantially corresponding to the impurity diffusion region 15. This diffusion mask 13
Although not limited to this, for example, AlN (aluminum nitride)
It can be composed of a film. The opening 13a of the diffusion mask 13
And the size of the impurity diffusion region actually formed,
Although the lateral diffusion Xs (see FIG. 2B) is different, the dimensions of the opening of the diffusion mask are shown as the dimensions of the impurity diffusion region in each drawing used in the following description unless otherwise specified. Note that

The impurity diffusion region 15 is formed in the first region 1
5a and the second region 15b.

Here, the first region 15a is used as a light emitting portion, and is arranged at a predetermined pitch P according to the resolution in relation to the first region 15a of another impurity diffusion region. In the first embodiment, each impurity region 15 is arranged such that the first region 15a of each impurity diffusion region 15 is aligned. First area 15
Since a is dedicated to the light emitting unit, the individual electrodes 1
Since a structure having no 7 is obtained, it is possible to prevent the area of the light emitting section from being reduced due to the individual electrode 17. Note that, for convenience of the following description, the arrangement direction of the first region 15a (although it can be said that the arrangement direction of the impurity diffusion region 15 is of course) is represented by X in the drawings, and is sometimes referred to as the arrangement direction X.

The planar shape of the first region 15a is
It is preferable that the shape is such that the light emission spot from the region (1) is substantially circular (including a circle). In a high-resolution light-emitting diode array chip for which high-definition printing is expected, the influence of the shape of the light-emitting spot on the final printing quality is relatively large, but when the shape is substantially circular, high-definition is achieved. This is because printing is easy. If the light emitting spot has a substantially circular shape, the planar shape of the first region 15a can be an arbitrary shape such as a circle or a polygon. Typically,
As shown in the plan view of FIG. 3, the planar shape of the first region 15a is rectangular and the first region 15a
May have a rectangular shape having an aspect ratio (W1y / W1x) such that the light emission spot from the region 15a becomes substantially circular. Note that W1x is the direction X in the arrangement direction of the first region 15a.
W1y is the arrangement direction X of the first region 15a.
Is a dimension along the direction Y orthogonal to Further, the square shape here means not only a square (that is, W1y / W1x = 1), but also a certain range of rectangles other than the square (that is, W1y / W1x = 1).
1y / W1x ≠ 1) is also included. This aspect ratio (W1y /
W1x) may be determined experimentally, for example.

The dimension W1x of the first region 15a along the arrangement direction X is equal to the pitch P of the first region 15a,
A desired value or a value close to the desired value is determined in consideration of a margin (which is referred to as a diffusion margin) that allows the adjacent first regions 15a to be separated from each other even in consideration of manufacturing variations. That is, when the lateral diffusion amount of the impurity diffusion region 15 is Xs (see FIG. 2B), the dimension W1x can be a desired dimension on the assumption that W1x + 2Xs <P is satisfied and a diffusion margin can be secured.
For example, a description will be given of an example of configuring a chip having a resolution of 1200 DPI (dot per inch). In that case, the pitch P of the first region 15a is 21 μm
Becomes For example, it is assumed that the dimension in the X direction of the diffusion mask for forming the desired first region 15a is 5 μm. Further, it is assumed that the lateral diffusion amount Xs of the impurity diffusion region 15 is 1.5 μm. Then, X in the first area 15a
The dimension W1x along the direction is 5 + 1.5 × 2 = 8 μm. Then, for the relationship with the pitch P = 21, 21-
Since (diffusion margin) = 8 μm, the diffusion margin is good up to 13 μm. With such a diffusion margin, the adjacent first regions 15a can be sufficiently separated from each other, so that the first regions 15a of W1x = 8 μm (that is, 5 μm in terms of the opening size of the diffusion mask) can be formed. It turns out that.

On the other hand, the second region 15b is mainly used as a connection portion with the electrode 17 on the second conductive side, and the direction perpendicular to the arrangement direction with respect to the first region 15a (FIG. 1,
The electrode 1 which is continuous in the Y direction (FIG. 2) and on the second conductive side
7 has at least an area in which a desired contact can be made. The planar shape of the second region 15b can be any suitable shape, but in this embodiment, it is a square shape. The second region 15b of each of the odd-numbered impurity diffusion regions among the impurity diffusion regions 15 is the first region 15b.
So as to be located in the one side area 11a of the base divided by the arrangement line L (FIG. 1) of the area 15a, and
Region 1 on the other side of the base where second region 15 of each even-numbered impurity diffusion region is divided by array line L
Each impurity diffusion region 15 is arranged so as to be located at 1b. Therefore, the pitch P2 between the odd-numbered second regions 15b (even between the even-numbered second regions 15b) (see FIG. 1) is expanded to twice the pitch P of the first region 15a. Therefore, the dimension W2x of the second region 15b along the arrangement direction X can be larger than the dimension W1x of the first region 15a along the same direction. For example, the above 1200D
In the case of the PI, since it is given by W2x = 42-2 × 1.5− (diffusion margin), it can be made sufficiently larger than the dimension W1x of the first region 15a. In addition, a dimension W2y (see FIG. 2A) of the second region 15b along the Y direction can be made large. Therefore, the impurity diffusion region 15
The second region 15b having a large area effective for reducing the contact resistance between the second electrode 15b and the individual electrode 17 can be formed. Although not limited thereto, FIGS. 1 and 2 show an example of W2x = 2 · W1x.

As shown in FIG. 4, the second region 15b in the impurity diffusion region 15x at the chip end is a first region where the end 15be on the chip end side is continuous with the second region. It is preferable to arrange the terminal 15a so as not to extend from the terminal end 15ae on the chip end side to the chip end Ce side. This is to prevent an unnecessary impurity diffusion region from being present in a base portion between the chip end Ce and the impurity diffusion region 15x at the chip end. Furthermore, the planar shape of the second region 15b in the impurity diffusion region 15x at the chip end is the same as that of the second region 1b in the impurity diffusion region 15 other than the chip end.
It is preferable that the shape be different from the plane shape of 5b. More specifically, as shown in FIG. 4, the dimension W2x and W2y in the X and Y directions of the second region 15b in the impurity diffusion region 15 other than the chip end are different from the impurity diffusion region 15 at the chip end.
The dimensions of the second region 15b in x in the X and Y directions are W2xe (<W2x) and W2ye (> W2y). That is, the second region 15b is located on the chip end Ce side.
Cannot be formed, the dimension W of the second region in the Y direction
2ye is increased. In this case, the second area 15
The area b can be easily set to the area required for contact with the individual electrodes 17.

The arrangement relationship between the second region 15b and the individual electrode 17 may be, for example, as follows according to the purpose.

First, as shown in FIG.
Accordingly, the arrangement can be made such that the individual electrodes 17 are connected to the second region 15b while covering the second region 15b. With such an arrangement, the light does not exit from the second region 15b but exits only from the first region 15a.
Therefore, it is possible to prevent variations in light emission between dots. Furthermore, since the individual electrode 17 always contacts the entire second region 15b, the contact area between the impurity diffusion region 15 and the individual electrode 17 is substantially defined by the area of the second region 15b. In other words, even if the individual electrode 17 does not contact a part of the first region 15a for each dot, it can be said that this does not significantly affect the increase or decrease of the contact area. Therefore, the individual electrode 17 and the impurity diffusion region 15
There is also an effect that the contact resistance with the dots can be made uniform between the dots.

As another example, the arrangement may be as shown in FIG. That is, the area of the second region 15b is made larger than the area where the desired contact with the individual electrode 17 can be made. Then, the individual electrode 17 is connected to the second region 1.
Assuming that a desired contact area is secured with respect to the first region 15b of the second region 15b.
The parts 15bs on the a-side (see FIG. 6) are connected in an eccentric arrangement so as to be exposed. The reasons for this are as follows. In order to obtain a high-resolution light emitting diode array chip, the impurity diffusion region 15 has a shallow diffusion depth. This is because the deeper the diffusion depth, the greater the amount of diffusion in the lateral direction, so that a diffusion margin between adjacent impurity diffusion regions cannot be obtained. In general, the sheet resistance of the impurity diffusion region having a shallow diffusion depth is increased to some extent.
In particular, the light amount in the portion immediately adjacent to 7 increases. In such a case,
With the structure as shown in FIG. 6, the width of the portion in the vicinity of the individual electrode 17 in the impurity diffusion region becomes the dimension W2x in the X direction of the second region 15b. On the other hand, in the structure of FIG. 5, the width of the portion in the vicinity of the individual electrode 17 in the impurity diffusion region is the dimension W1x in the x direction of the first region 15a. Here W2x>
Since it is W1x, the structure of FIG. 6 has a larger area of a region with a larger amount of light than the structure of FIG. 5, so that a chip with good light extraction efficiency can be configured.

In general, a part of the individual electrode 17 is often used as a pad for connection to an external device. In that case, as shown in FIG. 1, when looking at the odd-numbered impurity diffusion regions, the individual electrodes 1 for each impurity diffusion region
7 are arranged in a staggered manner in the one side region 11a of the base and along the arrangement direction X, and when looking at even-numbered impurity diffusion regions, the individual electrodes 17a for each impurity diffusion region Pad part 17 in
a are preferably arranged in a staggered manner in the arrangement direction X within the other side region 11b of the base. By doing so, the pitch P of every other pad in the pad portion 17a for the odd-numbered (even-numbered) impurity diffusion regions is set.
3 (see FIG. 1) can be increased up to four times as large as the arrangement pitch P of the first regions 15a. Therefore, the area of the pad portion 17a is set to a sufficiently large pad portion suitable for, for example, wire bonding. And can be.

1-2. Second Embodiment In the above-described first embodiment, an example will be described in which the impurity diffusion regions 15 are arranged such that the first regions 15a in the respective impurity diffusion regions 15 are arranged at a pitch P in a straight line. did. However, these impurity diffusion regions 15 may be arranged as follows. That is, as shown in FIG. 7, the first region 15 of the odd-numbered impurity diffusion region 15u is formed.
a and the first region 15 of the even-numbered impurity diffusion region 15v
a is shifted in the direction Y by at least a dimension W1y along a direction Y orthogonal to the arrangement direction X of the first region 15a. In FIG. 7, in order to clarify the difference between the size of the impurity diffusion region 15 and the size of the opening 13a of the diffusion mask 13, the two are separately shown. In the case of the structure shown in FIG. 7, although the first regions 15a are arranged in a staggered manner along the X direction, the first regions 15a are arranged in the X direction directly. The area becomes 15a. For this reason, the constraint on the dimension W1x along the X direction of the first first region 15a is looser than that in the first embodiment, so that a design margin when designing a light emitting diode array chip with higher resolution is increased. The effect is obtained.

It is apparent that the various devices described in the first embodiment with reference to FIGS. 1 to 6 can be applied to the chip of the second embodiment.

The chip or the second embodiment of the first embodiment described above
The light emitting diode array can be obtained by linearly arranging the chips according to the embodiments on a wiring board (not shown).

2. Description of Manufacturing Method The above-described chip can be manufactured by, for example, the following procedure.
In the process of forming dicing line marks and the exposure process for forming the individual electrodes 17 in the manufacturing process, the present invention uses the following measures. 8 and 9 are process diagrams provided for the description, FIG. 10 is a diagram mainly illustrating a dicing line mark forming process, and FIG. 11 is a diagram mainly illustrating a process of forming an individual electrode 17.

As the underlayer 11, for example, a substrate obtained by epitaxially growing a GaAsP layer on a GaAs substrate is used. However, in each figure, a GaAs substrate and a GaAsP
It is shown as a single body without distinction from layers. This base 11
A diffusion mask 13 having an opening 13a for forming the impurity diffusion region 15 is formed thereon (FIG. 8A). The diffusion mask 13 can be formed, for example, by forming an AlN (aluminum nitride) film and then processing it by a known lithography technique and etching technique. Also,
When the diffusion mask 13 is formed, a predetermined portion of the mask constituent material, for example, an AlN film is removed to form a dicing line mark. At this time, the following treatment is performed. FIG. 10A is a plan view of a main part of FIG.
A description will be given with reference to a II line cross-sectional view of a Q portion in FIG. A portion 25a of the dicing line mark 25 formed by removing a part of the diffusion mask 13 and adjacent to the portion 27 where the impurity diffusion region is to be formed at the chip end in the dicing line mark 25 along the direction orthogonal to the longitudinal direction of the chip. Then, the diffusion mask 1 is formed between the dicing line mark 25 and the portion 27 where the impurity diffusion region is to be formed at the end of the chip such that the diffusion mask has a predetermined width W ₀ and remains.
3 is removed. Here, the predetermined width W ₀ is a dimension that is at least wider than the diffusion margin but wider than the width of the wafer portion remaining at the chip end after dicing. FIG.
In the example of the above, the dicing line mark 25 is
In FIG. 3A, the bent portion is located away from the portion 27 where the impurity diffusion region is to be formed. Of course, if there is no problem in dicing, the entire diffusion mask of the corresponding portion 25a may be left. If the above-described processing is performed during the formation of the dicing line mark 25, the dicing line mark 25
The impurity diffusion region formed at the end of the chip is not continuous with the impurity diffusion region at the end of the chip, and no unnecessary impurity diffusion region remains at the end of each chip divided by dicing.

Next, an impurity diffusion region is formed on the sample by a solid phase diffusion method. Therefore, in this embodiment,
First, a diffusion source thin film 21 and an annealing cap film 23 are formed on the sample in this order (FIG. 8B). For example, an SiO ₂ film containing ZnO can be used as the diffusion source thin film 21, and an AlN film can be used as the annealing cap film 23, for example.

Next, heat treatment is performed on the sample. For example, by performing a heat treatment at a temperature of 700 ° C. for one hour, an impurity diffusion region 15 having a diffusion depth of 1 μm, which is composed of a first region 15a and a second region 15b, Is formed (see also FIG. 8).
(B)). At this time, impurity diffusion regions are also formed at dicing line marks in various parts of the wafer. However, since the treatment described with reference to FIG. 10 is performed at the time of forming the dicing line marks, the The impurity diffusion region formed at the dicing line mark 25 along the direction perpendicular to the longitudinal direction of the chip is separated from the impurity diffusion region 15 at the chip end, and remains at the chip end after dicing. It is not formed on the wafer. In addition, since the diffusion mask is also left around the chip end side of the impurity diffusion region on the chip end side, the condition of the film stress caused by the diffusion mask in the impurity diffusion region on the chip end side is limited to the impurity other than the chip end. The effect of approaching the same condition of the diffusion region can also be obtained.

Next, the annealing cap film 23 and the diffusion source thin film 21 are removed (FIG. 8C). When an AlN film is used as the annealing cap film 23, it can be removed by, for example, heated phosphoric acid.
When an SiO ₂ film containing nO is used, it can be removed by, for example, buffered HF (hydrogen fluoride).

Next, an individual electrode 17 is formed on the sample (FIG. 9A). In forming the individual electrodes 17, although not shown, a thin film for forming an individual electrode is formed on a sample, a portion which is to be left as an individual electrode on the thin film is covered, and other portions are exposed. A method of forming a pattern and selectively etching the thin film, or forming a resist pattern on the sample where an individual electrode forming region is exposed and the other portion is covered, and then forming an individual electrode on the sample A method of removing unnecessary portions of the thin film for forming individual electrodes (lifting off) by forming a thin film for use and then removing the resist pattern is used. At this time, a photomask is used for forming a resist pattern,
As shown in FIG. 11, the photomask is individually divided by an amount corresponding to the positional deviation amounts Δx and Δy that would be generated when the photomask is aligned with the region 15 c to be connected to the individual electrode of the impurity diffusion region 15. A photomask 31 having an extended electrode pattern 33 is used. These positional deviation amounts Δx and Δy may be determined mainly in consideration of the performance of the exposure apparatus used and the characteristic specifications required for the light emitting diode array chip. When such a photomask 31 is used, any part of the individual electrode 17 always covers the region 15c of the impurity diffusion region to be connected to the individual electrode within the range of the expected misalignment amount of the photomask. Therefore, a desired contact area is secured when connecting the individual electrode 17 and the second region 15b.

Next, the underlayer 11 is polished from the back side to a predetermined thickness. Next, a common electrode 19 is formed on the back surface by a known method (FIG. 9B). Thereafter, the wafer is diced along the dicing line marks to divide the chips from the wafer.
Thereby, the chip according to the first invention is obtained.

In each of the above embodiments, an example has been described in which the diffusion mask 13 is also used as an interlayer insulating film. However, before forming an individual electrode, an interlayer insulating film is newly formed separately from the diffusion mask. Is also good. In this case, the insulation between the individual electrode 17 and the base 11 can be further improved.

In the above description, an example in which each invention according to this application is applied to a light emitting diode array chip has been described. However, the present invention is applicable to a light receiving diode array chip, a light emitting diode array, The present invention can be similarly applied to a light receiving diode array, and in each case, an effect similar to that of the embodiment can be obtained.

In the above description, the resolution is 1200
Although the example of the light emitting diode array chip of DPI was shown,
Of course, this is only an example. In the example shown in FIG. 1, when the resolution is, for example, 2400 DPI, the pitch P of the first region 15 a is 11 μm. Therefore, when the diffusion margin is 4 μm, the X of the first region 15 a is X.
The direction dimension W1x can be set to W1x = 11-4 = 8 μm. Here, assuming that the lateral diffusion amount Xs (see FIG. 2B) of the impurity diffusion region with respect to the opening of the diffusion mask 13 is 1.5 μm, the dimension of the opening of the diffusion mask in the X direction is 8- 2 × 1.5 = 5 μm. On the other hand, the pitch P2 of the second region 15b may be 22 μm because the pitch P2 may be twice the pitch P of the first region 15a. The actual dimension in the X direction of the second area 15b for realizing 2400 DPI is W2x = 22-2 · X
It is given by s- (diffusion margin). From these,
A light-receiving diode array chip of 2400 DPI can be sufficiently realized. Of course, the achievable resolution is not limited to the above example. By controlling the lateral diffusion amount Xs and the diffusion margin, the realization of a higher-resolution photodiode array chip can be expected.

[0042]

As is apparent from the above description, according to the light receiving / emitting diode array chip of the first invention, the base of the first conductivity type and the large number of the second conductivity types formed at a predetermined pitch on the base. In the light receiving / emitting diode array chip including the impurity diffusion regions and the individual electrode groups individually connected to the impurity diffusion regions, each of the impurity diffusion regions is provided with a predetermined first light emitting / receiving portion used as a light receiving / emitting portion. And a predetermined second region mainly used as a connection portion with the individual electrode, and among these impurity diffusion regions, odd-numbered impurity diffusion regions and even-numbered impurity diffusion regions respectively. Is a predetermined arrangement. For this reason, a decrease in the aperture ratio due to the individual electrodes of the light emitting / receiving section is prevented. Further, the second region may have an area sufficient to reduce the contact resistance with the individual electrode. Therefore, the realization of a light receiving and emitting diode array chip with higher resolution and a light receiving and emitting diode array using the same can be expected.

According to the second aspect of the present invention, the pattern of the photomask used for patterning the individual electrode is devised to be expanded as predetermined, so that the impurity diffusion region and the individual electrode can be separated from each other by a desired distance within the expected photomask shift range. Connection can be made with a contact area. According to the second aspect, it is possible to easily manufacture a light receiving and emitting diode array chip with higher resolution.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram (part 1) of a first embodiment of a light-emitting diode array chip.

FIG. 2 is an explanatory view (No. 2) of the first embodiment of the light-emitting diode array chip.

FIG. 3 is an explanatory view (No. 3) of the first embodiment of the light-emitting diode array chip.

FIG. 4 is an explanatory view (No. 4) of the first embodiment of the light-emitting diode array chip.

FIG. 5 is an example (part 1) of an arrangement relationship between a second region and an individual electrode.

FIG. 6 is an example (part 2) of an arrangement relationship between a second region and an individual electrode.

FIG. 7 is an explanatory diagram of a second embodiment of the light-emitting diode array chip.

FIG. 8 is a process chart (part 1) for explaining the embodiment of the manufacturing method;

FIG. 9 is a process chart (part 2) for explaining the embodiment of the manufacturing method;

FIG. 10 is an explanatory diagram of the embodiment.

FIG. 11 is an explanatory diagram of the embodiment.

FIG. 12 is an explanatory diagram of a problem.

[Description of Signs] 11: Underlayer made of a first conductivity type compound semiconductor 11a: One side of the underlayer separated by array line L 11b: The other side of the underlayer partitioned by array line L 13: Diffusion Mask 13a: Opening of diffusion mask 15: Impurity diffusion region 15a: First region 15b: Second region 17: Individual electrode 17a: Pad portion of individual electrode 17c: Contact portion 19: Common electrode X: Arrangement direction Y: Direction perpendicular to the arrangement direction X L: Array line

──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Yukio Nakamura 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-61-29562 (JP, A) JP-A JP-A-3-194977 (JP, A) JP-A-6-85319 (JP, A) JP-A-5-275738 (JP, A) JP-A-8-46243 (JP, A) JP-A-6-21512 (JP) JP-A-6-314817 (JP, A) JP-A-5-63231 (JP, A) JP-A-4-102379 (JP, A) JP-A-3-201490 (JP, A) 64-47041 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 33/00

Claims (11)

(57) [Claims] 1. A base made of a compound semiconductor of a first conductivity type, a plurality of impurity diffusion regions of a second conductivity type formed on the base at a pitch corresponding to a required resolution, and individual impurity diffusion regions A light-emitting and light-emitting diode array chip comprising a group of individual electrodes connected to each other, wherein each of the impurity diffusion regions is a first region used as a light-receiving and light-emitting portion, In relation to the first region, the first region arranged at the pitch and the second region mainly used as a connection portion with the individual electrode.
A region which is continuous with the first region in a direction orthogonal to the arrangement direction, and has a dimension along the arrangement direction larger than the same size of the first region, The individual electrode and a second region having at least an area where a desired contact can be made, and the second region of each of the odd-numbered impurity diffusion regions among the impurity diffusion regions is the second region. The second region of each of the even-numbered impurity diffusion regions is located on one side of the base divided by the arrangement line of the first region, and the second region of each of the even-numbered impurity diffusion regions is the other of the base divided by the arrangement line. Characterized in that these impurity diffusion regions are arranged so as to be located in the side region. 2. The light emitting and receiving diode array chip according to claim 1, wherein the second region in the impurity diffusion region at the chip end is:
A light-emitting / emitting diode array chip, wherein the chip end side end is disposed so as not to extend beyond the chip end side of the chip end side end of the first region which is continuous with the second region. . 3. The light receiving and emitting diode array chip according to claim 1, wherein the planar shape of the first region is such that a light emitting spot from the first region in a light emitting operation has a substantially circular shape. A light receiving / emitting diode array chip, comprising: 4. The light-receiving / emitting diode array chip according to claim 1, wherein the planar shape of the first region is a square, and a light-emitting spot from the first region during a light-emitting operation is substantially circular. A light receiving and emitting diode array chip having a quadrangular shape having an aspect ratio as follows. 5. The light emitting and receiving diode array chip according to claim 1, wherein said individual electrode is connected to said second area while covering said second area. Diode array chip. 6. The light emitting and receiving diode array chip according to claim 1, wherein an area of the second region is larger than an area where the desired contact can be made, and the individual electrode is arranged with respect to the second region. The connection is provided in such a manner that at least a portion of the second region on the side of the first region is unbalanced so as to expose the desired contact area. Light receiving and emitting diode array chip. 7. The light emitting and receiving diode array chip according to claim 1, wherein the individual electrode has a pad portion used for connection with an external device, and when the odd numbered impurity diffusion region is viewed, The pad portions of the individual electrodes for each impurity diffusion region are arranged in a staggered manner in the region on one side of the base and along the arrangement direction, and when viewing the even-numbered impurity diffusion regions, The light-emitting / receiving diode array chip, wherein the pad portions of the individual electrodes for each impurity diffusion region are arranged in a staggered manner in the other region of the base and along the arrangement direction. 8. The light emitting and receiving diode array chip according to claim 1, wherein each of the impurity regions is arranged so that the first region of each of the impurity diffusion regions is arranged in a straight line. Diode array chip. 9. The light emitting and receiving diode array chip according to claim 1, wherein the first region of the odd-numbered impurity diffusion region and the first region of the even-numbered impurity diffusion region are at least the first region. A light emitting / receiving diode array chip, wherein each impurity diffusion region is arranged so as to be shifted in a direction orthogonal to the arrangement direction of the region in the direction. 10. A light emitting and receiving diode array, comprising the light emitting and receiving diode array chip according to claim 1 linearly mounted on a substrate. 11. A base made of a compound semiconductor of the first conductivity type, a plurality of impurity diffusion regions of the second conductivity type formed on the base at a pitch according to a required resolution, and individual impurity diffusion regions. The method for manufacturing a light-receiving / emitting diode array chip according to any one of claims 1 to 9, further comprising: a group of individual electrodes connected to the photomask. A photomask used in a step of forming the individual electrodes. As a feature, a photomask in which an individual electrode pattern is extended by an amount corresponding to an amount of misalignment that may occur when the photomask is aligned with a region to be connected to an individual electrode in the impurity diffusion region is used. A method for manufacturing a light receiving and emitting diode array chip.