JP3255731B2 - Manufacturing method of capacitive element - Google Patents
Manufacturing method of capacitive elementInfo
- Publication number
- JP3255731B2 JP3255731B2 JP28855192A JP28855192A JP3255731B2 JP 3255731 B2 JP3255731 B2 JP 3255731B2 JP 28855192 A JP28855192 A JP 28855192A JP 28855192 A JP28855192 A JP 28855192A JP 3255731 B2 JP3255731 B2 JP 3255731B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- metal film
- high dielectric
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【０００１】[0001]
【産業上の利用分野】本発明は、高誘電率を有する誘電
体薄膜を上電極および下電極で挟んで形成した容量素子
の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitive element formed by sandwiching a dielectric thin film having a high dielectric constant between an upper electrode and a lower electrode.
And a method for producing the same.
【０００２】[0002]
【従来の技術】近年、強誘電体薄膜は自発分極や高誘電
率といった特徴を持つために不揮発性ＲＡＭ（Random A
ccess Memory）や高集積ＤＲＡＭ（Dynamic Random Acc
ess Memory）におけるデータ保持のための容量素子に用
いる容量絶縁膜としての応用を目指して研究が盛んに行
われている。2. Description of the Related Art In recent years, a ferroelectric thin film has characteristics such as spontaneous polarization and high dielectric constant.
ccess Memory) and highly integrated DRAM (Dynamic Random Acc)
Researches have been actively conducted with the aim of applying it as a capacitance insulating film used for a capacitance element for retaining data in an ess memory.
【０００３】以下従来の容量素子について説明する。図
３は従来の容量素子の要部断面図であり、集積回路が形
成された半導体基板上に形成された例について示してい
る。図３に示すように従来の容量素子は、集積回路が作
り込まれた支持基板３１の上に選択的に膜厚が１０〜４
０ｎｍのチタン（Ｔｉ）膜３２および膜厚が１００〜３
００ｎｍの第１の白金（Ｐｔ）膜３３が蒸着法またはス
パッタ法を用いて形成されており、その上に（ＢａxＳ
ｒ1-x）ＴｉＯ3 膜からなる高誘電率を有する誘電体薄
膜（以下高誘電体薄膜という）３４が塗布法、スパッタ
法またはＣＶＤ（Chemical Vapor Deposition ）法を用
いて形成されている。この高誘電体薄膜３４は温度６０
０〜８００℃で焼成されたものである。その上に第２の
Ｐｔ膜３５が第１のＰｔ膜３３および高誘電体薄膜３４
と略同一の形状で形成されている。Hereinafter, a conventional capacitive element will be described. FIG. 3 is a cross-sectional view of a main part of a conventional capacitive element, and shows an example in which an integrated circuit is formed on a semiconductor substrate. As shown in FIG. 3, the conventional capacitance element has a film thickness of 10 to 4 selectively on a support substrate 31 in which an integrated circuit is formed.
0 nm titanium (Ti) film 32 and a thickness of 100 to 3
First platinum (Pt) film 33 of 00nm is formed by vapor deposition or sputtering, on the (Ba x S
A dielectric thin film 34 having a high dielectric constant (hereinafter referred to as a high dielectric thin film) made of r 1-x ) TiO 3 film is formed by using a coating method, a sputtering method, or a CVD (Chemical Vapor Deposition) method. This high dielectric thin film 34 has a temperature of 60.
It was fired at 0 to 800 ° C. A second Pt film 35 is formed on the first Pt film 33 and the high dielectric thin film 34.
And is formed in substantially the same shape.
【０００４】[0004]
【発明が解決しようとする課題】しかしながら上記の従
来の構成では、第２のＰｔ膜３５の形成後に高誘電体薄
膜３４を熱処理した場合、第１のＰｔ膜３３および第２
のＰｔ膜３５の熱膨張による応力がそれぞれの端部に集
中し、支持基板３１を破壊するという課題を有してい
た。However, in the above-described conventional structure, when the high dielectric thin film 34 is heat-treated after the formation of the second Pt film 35, the first Pt film 33 and the second Pt film
The stress caused by the thermal expansion of the Pt film 35 is concentrated on each end, and the support substrate 31 is broken.
【０００５】本発明は上記の従来の課題を解決するもの
で、熱膨張による応力を分散させることで支持基板の破
壊を防止し、かつ第２の金属膜を形成した後の熱処理に
よって高誘電体薄膜および第２の金属膜の密着性を向上
させることのできる容量素子の製造方法を提供すること
を目的とする。SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems. Dispersion of stress due to thermal expansion prevents breakage of a supporting substrate and heat treatment after forming a second metal film to form a high dielectric material. It is an object of the present invention to provide a method for manufacturing a capacitor capable of improving the adhesion between a thin film and a second metal film.
【０００６】[0006]
【課題を解決するための手段】この目的を達成するため
に本発明の請求項１記載の容量素子の製造方法は、支持
基板上に第１の金属膜を形成し、この第１の金属膜をパ
ターニングした後、高誘電体薄膜または強誘電体薄膜を
前記第１の金属膜を有する前記支持基板上に形成し、第
２の金属膜の端部が前記第１の金属膜の端部より外側ま
たは内側に配置されるように第２の金属膜を前記高誘電
体薄膜または強誘電体薄膜上に形成し、その後前記高誘
電体薄膜または強誘電体薄膜を６００℃から８００℃で
熱処理することを特徴とするものである。また、本発明
の請求項２記載の容量素子の製造方法は、支持基板上に
第１の金属膜を形成し、この第１の金属膜をパターニン
グした後、高誘電体薄膜または強誘電体薄膜および第２
の金属膜を前記第１の金属膜上および前記支持基板上に
前記第１の金属膜より外側にまで配置されるように形成
し、前記高誘電体薄膜または強誘電体薄膜および前記第
２の金属膜を前記第1の金属膜の端部より外側または内
側に配置されるように同時にパターニングし、その後前
記高誘電体薄膜または強誘電体薄膜を６００℃から８０
０℃で熱処理を施すことを特徴とするものである。 In order to achieve this object, a method of manufacturing a capacitive element according to claim 1 of the present invention comprises the steps of:
A first metal film is formed on a substrate, and the first metal film is
After turning, a high dielectric thin film or ferroelectric thin film
Forming on the support substrate having the first metal film,
2 is such that the end of the metal film is outside the end of the first metal film.
Or the second metal film is placed on the high dielectric
Formed on a dielectric thin film or a ferroelectric thin film.
Electric thin film or ferroelectric thin film at 600 ° C to 800 ° C
It is characterized by heat treatment. In addition, the present invention
The method of manufacturing a capacitive element according to claim 2, wherein
A first metal film is formed, and the first metal film is patterned
After the high dielectric thin film or the ferroelectric thin film and the second
On the first metal film and the support substrate
Formed so as to be disposed outside the first metal film
And the high dielectric thin film or the ferroelectric thin film and the
The second metal film is located outside or inside the end of the first metal film.
Pattern at the same time to be placed on the side
The high dielectric thin film or the ferroelectric thin film is heated from 600 ° C to 80 ° C.
The heat treatment is performed at 0 ° C.
【０００７】[0007]
【作用】この構成によって、熱処理によって発生する応
力を支持基板上の異なる場所に分散させることができ、
容量素子形成後の熱処理が可能となり、良質の容量素子
を形成できる。With this configuration, the stress generated by the heat treatment can be dispersed to different places on the support substrate,
Heat treatment after the formation of the capacitor can be performed, and a high-quality capacitor can be formed.
【０００８】[0008]
【実施例】以下本発明の一実施例について、図面を参照
しながら説明する。図１は本発明の第1の実施例により
製造された容量素子の断面図である。図１に示すよう
に、集積回路が作り込まれた支持基板１の上に膜厚１０
〜４０ｎｍのＴｉ膜２と膜厚１００〜３００ｎｍの第１
のＰｔ膜３とを連続的に蒸着法またはスパッタ法により
形成する。この第１のＰｔ膜３を覆って（ＢａxＳ
ｒ1-x）ＴｉＯ3膜等の高誘電体薄膜４を塗布法、ＣＶＤ
法またはスパッタ法を用いて２０〜３００ｎｍの厚さに
形成する。さらに高誘電体薄膜４の上に膜厚１００〜３
００ｎｍで第２のＰｔ膜５を形成する。図１は容量素子
を形成する際に第２のＰｔ膜５および高誘電体薄膜４を
同時にパターニングした例で、第２のＰｔ膜５の端部が
第1のＰｔ膜３およびＴｉ膜２の端部を越えて離れた位
置に来るようにして形成されている例を示している。上
記の膜厚の関係からすると、第２のＰｔ膜５の端部が第
１のＰｔ膜３より５μｍ以上外側にあれば問題はない。An embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a first embodiment of the present invention
It is sectional drawing of the manufactured capacitive element . As shown in FIG. 1, a film having a thickness of 10
Ti film 2 having a thickness of 40 to 40 nm and a first film having a thickness of 100 to 300 nm
And the Pt film 3 is formed by continuously depositing or sputtering. By covering the first Pt film 3 (Ba x S
r 1-x ) High dielectric thin film 4 such as TiO 3 film , coating method, CVD
It is formed to a thickness of 20 to 300 nm by using a method or a sputtering method. Further, a film thickness of 100 to 3 is formed on the high dielectric thin film 4.
A second Pt film 5 is formed with a thickness of 00 nm. FIG. 1 shows an example in which the second Pt film 5 and the high-dielectric thin film 4 are simultaneously patterned when forming the capacitive element, and the end of the second Pt film 5 is formed of the first Pt film 3 and the Ti film 2. An example is shown in which it is formed so as to be located at a position beyond the end. In view of the above film thickness relationship, there is no problem if the end of the second Pt film 5 is at least 5 μm outside the first Pt film 3.
【０００９】なお図１に示す実施例では、第２のＰｔ膜
５の端部を第１のＰｔ膜３の端部の外側に来るように配
置した例を示したが、逆に第２のＰｔ膜５の端部が第１
のＰｔ膜３の内側に来るようにしても同様の効果が得ら
れる。すなわち、第１のＰｔ膜３の端部と第２のＰｔ膜
５の端部が一致しないようにすればよい。In the embodiment shown in FIG. 1, an example is shown in which the end of the second Pt film 5 is disposed outside the end of the first Pt film 3; The end of the Pt film 5 is the first
A similar effect can be obtained even if the inside of the Pt film 3 is provided. That is, the end of the first Pt film 3 and the end of the second Pt film 5 do not have to match.
【００１０】以上のように本実施例によれば、第１のＰ
ｔ膜３と第２のＰｔ膜５の端部をずらす構造とすること
により熱処理時の応力集中を避け、支持基板１の破壊を
防ぐことができる。As described above, according to this embodiment, the first P
By adopting a structure in which the end portions of the t film 3 and the second Pt film 5 are shifted, stress concentration at the time of heat treatment can be avoided, and destruction of the support substrate 1 can be prevented.
【００１１】次に本発明の第２の実施例により製造され
た容量素子について、図面を参照しながら説明する。図
２は同容量素子の断面図である。第２の実施例では、Ｔ
ｉ膜２３および第１のＰｔ膜２４の端部が支持基板２１
の段差部２２の内側にある。図２に示すように、集積回
路が作り込まれた支持基板２１の上に膜厚１０〜４０ｎ
ｍのＴｉ膜２３と膜厚１００〜３００ｎｍの第１のＰｔ
膜２４とを連続的に蒸着法またはスパッタ法により形成
する。この第1のＰｔ膜２４を覆って（ＢａxＳｒ1-x）
ＴｉＯ3膜等の高誘電体薄膜２５を塗布法、ＣＶＤ法ま
たはスパッタ法を用いて２０〜３００ｎｍの厚さに形成
する。さらに高誘電体薄膜２５の上に膜厚１００ｎｍ〜
３００ｎｍで第２のＰｔ膜２６を形成する。本実施例で
は、第２のＰｔ膜２６の端部が第１のＰｔ膜２４の端部
より５μｍ以上外側に、かつ段差部２２の端部より２μ
ｍ内側に来るように配置されている。以上のように本実
施例によれば、第１のＰｔ膜２４の端部、第２のＰｔ膜
２６の端部および機械的に弱い段差部２２の端部をそれ
ぞれずらせた構造となり、熱処理時の応力集中を避け、
段差部２２における支持基板２１の破壊を防ぐことがで
きる。Next, a semiconductor device manufactured according to the second embodiment of the present invention is manufactured.
The capacitance element will be described with reference to the drawings. FIG. 2 is a sectional view of the same capacitive element. In the second embodiment, T
The ends of the i film 23 and the first Pt film 24 are
Is located inside the step 22. As shown in FIG. 2, a film thickness of 10 to 40 n is formed on a support substrate 21 on which an integrated circuit is formed.
m Ti film 23 and first Pt having a thickness of 100 to 300 nm
Formed by the membrane 24 and the successive vapor deposition method or a sputtering method
I do . Covering the first Pt film 24 (Ba x Sr 1-x )
Coating a high dielectric thin film 25 such as TiO 3 film by CVD or sputtering a thickness of 20~300nm
I do . Further, a film thickness of 100 nm
300nm to the formation of the second Pt layer 26. In this embodiment, the end of the second Pt film 26 is at least 5 μm outside the end of the first Pt film 24 and 2 μm from the end of the step 22.
m. According to this embodiment, as described above, the end portion of the first Pt film 24, a second end and mechanically weak end the structure becomes that by shifting each of the step portion 22 of the Pt film 26, the heat treatment Avoid stress concentration of
The destruction of the support substrate 21 at the step 22 can be prevented.
【００１２】なお第１および第２の実施例では、容量素
子の電極用金属膜としてＰｔ膜を用いたが、Ｐｔ膜の代
わりに他の金属を用いても同様の効果があることはいう
までもない。In the first and second embodiments, a Pt film is used as a metal film for an electrode of a capacitive element. However, it is needless to say that the same effect can be obtained by using another metal in place of the Pt film. Nor.
【００１３】また第１および第２の実施例では、強誘電
体薄膜として（ＢａxＳｒ1-x）ＴｉＯ3 膜を用いたが、
他にＳｒＴｉＯ3 膜、ＢａＴｉＯ3 膜、ＰＺＴ膜または
ＰＬＺＴ膜など他の強誘電体薄膜を用いても同様の効果
が得られることはいうまでもない。In the first and second embodiments, the (Ba x Sr 1 -x ) TiO 3 film is used as the ferroelectric thin film.
Needless to say, the same effect can be obtained by using another ferroelectric thin film such as an SrTiO 3 film, a BaTiO 3 film, a PZT film or a PLZT film.
【００１４】[0014]
【発明の効果】以上のように本発明の製造方法によれ
ば、第１の金属膜の端部と第２の金属膜の端部とが一致
しない構成となり、支持基板の破壊を起こすことなく第
２の金属膜形成後に熱処理を行なうことができ、高誘電
体薄膜と第１および第２の金属膜との間の密着性が良い
優れた容量素子を実現できるものである。As described above , according to the manufacturing method of the present invention,
If the end of the first metal film coincides with the end of the second metal film
A heat treatment can be performed after the formation of the second metal film without destruction of the supporting substrate, and an excellent capacitance with good adhesion between the high dielectric thin film and the first and second metal films. An element can be realized.
【図１】本発明の第１の実施例により製造された容量素
子の断面図FIG. 1 is a sectional view of a capacitive element manufactured according to a first embodiment of the present invention.
【図２】本発明の第２の実施例により製造された容量素
子の断面図FIG. 2 is a sectional view of a capacitor manufactured according to a second embodiment of the present invention;
【図３】従来の容量素子の断面図FIG. 3 is a cross-sectional view of a conventional capacitive element.
１ 支持基板 ３ 第１のＰｔ膜（第１の金属膜） ４ 高誘電体薄膜（誘電体薄膜） ５ 第２のＰｔ膜（第２の金属膜） Reference Signs List 1 support substrate 3 first Pt film (first metal film) 4 high dielectric thin film (dielectric thin film) 5 second Pt film (second metal film)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 那須 徹 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (72)発明者 嶋田 恭博 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (72)発明者 上本 康裕 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (72)発明者 大槻 達男 大阪府門真市大字門真1006番地 松下電 子工業株式会社内 (56)参考文献 特開 平４−266062（ＪＰ，Ａ) 特開 平３−256358（ＪＰ，Ａ) 特開 平５−343612（ＪＰ，Ａ) 特開 平６−132482（ＪＰ，Ａ) 特開 平４−356958（ＪＰ，Ａ) ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Toru Nasu 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Denshi Kogyo Co., Ltd. (72) Inventor Yasuhiro Uemoto 1006 Kazuma Kadoma, Osaka Prefecture Inside Matsushita Denshi Kogyo Co., Ltd. Document JP-A-4-266606 (JP, A) JP-A-3-256358 (JP, A) JP-A-5-343612 (JP, A) JP-A-6-132482 (JP, A) JP-A-4- 356958 (JP, A)
Claims (2)
の第１の金属膜をパターニングした後、高誘電体薄膜ま
たは強誘電体薄膜を前記第１の金属膜を有する前記支持
基板上に形成し、第２の金属膜の端部が前記第１の金属
膜の端部より外側または内側に配置されるように第２の
金属膜を前記高誘電体薄膜または強誘電体薄膜上に形成
し、その後前記高誘電体薄膜または強誘電体薄膜を６０
０℃から８００℃で熱処理することを特徴とする容量素
子の製造方法。 A first metal film is formed on a support substrate, and after patterning the first metal film, a high dielectric thin film or a ferroelectric thin film is formed on the first metal film. A second metal film formed on the supporting substrate having a film, wherein the second metal film is disposed on the outside of or inside the edge of the first metal film. Alternatively, a high dielectric thin film or a ferroelectric thin film is formed on a ferroelectric thin film,
A method for manufacturing a capacitive element, wherein a heat treatment is performed at 0 ° C. to 800 ° C.
の第１の金属膜をパターニングした後、高誘電体薄膜ま
たは強誘電体薄膜および第２の金属膜を前記第１の金属
膜上および前記支持基板上に前記第１の金属膜より外側
にまで配置されるように形成し、前記高誘電体薄膜また
は強誘電体薄膜および前記第２の金属膜を前記第1の金
属膜の端部より外側または内側に配置されるように同時
にパターニングし、その後前記高誘電体薄膜または強誘
電体薄膜を６００℃から８００℃で熱処理を施すことを
特徴とする容量素子の製造方法。 2. A first metal film is formed on a supporting substrate, and after patterning the first metal film, a high dielectric thin film or a ferroelectric thin film and a second metal film are formed. Is formed on the first metal film and the support substrate so as to be disposed outside the first metal film, and the high dielectric thin film or the ferroelectric thin film and the The second metal film to the first gold
Patterned simultaneously <br/> to be positioned outside or inside the end portion of Shokumaku, the high-dielectric thin film or Tsuyo誘after its
A method for manufacturing a capacitive element, wherein a heat treatment is performed on an electric thin film at 600 to 800 ° C.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28855192A JP3255731B2 (en) | 1992-10-27 | 1992-10-27 | Manufacturing method of capacitive element |
| EP97106056A EP0789395B1 (en) | 1992-06-12 | 1993-06-14 | Manufacturing method for semiconductor device having capacitor |
| DE69333864T DE69333864T2 (en) | 1992-06-12 | 1993-06-14 | Manufacturing method for semiconductor device with capacitor |
| DE69317940T DE69317940T2 (en) | 1992-06-12 | 1993-06-14 | Semiconductor device with capacitor |
| EP93304609A EP0574275B1 (en) | 1992-06-12 | 1993-06-14 | Semiconductor device having capacitor |
| US08/778,953 US5717233A (en) | 1992-06-12 | 1997-01-06 | Semiconductor device having capacitior and manufacturing method thereof |
| US08/947,712 US6126752A (en) | 1992-06-12 | 1997-10-09 | Semiconductor device having capacitor and manufacturing apparatus thereof |
| US08/950,920 US6080617A (en) | 1992-06-12 | 1997-10-15 | Semiconductor device having capacitor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28855192A JP3255731B2 (en) | 1992-10-27 | 1992-10-27 | Manufacturing method of capacitive element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06140275A JPH06140275A (en) | 1994-05-20 |
| JP3255731B2 true JP3255731B2 (en) | 2002-02-12 |
Family
ID=17731714
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28855192A Expired - Fee Related JP3255731B2 (en) | 1992-06-12 | 1992-10-27 | Manufacturing method of capacitive element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3255731B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021149687A1 (en) * | 2020-01-20 | 2021-07-29 | 株式会社村田製作所 | Semiconductor device and module |
-
1992
- 1992-10-27 JP JP28855192A patent/JP3255731B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH06140275A (en) | 1994-05-20 |
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