JP3252386B2 - Manufacturing method of silicon single crystal wafer - Google Patents

Manufacturing method of silicon single crystal wafer

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Publication number
JP3252386B2
JP3252386B2 JP09772795A JP9772795A JP3252386B2 JP 3252386 B2 JP3252386 B2 JP 3252386B2 JP 09772795 A JP09772795 A JP 09772795A JP 9772795 A JP9772795 A JP 9772795A JP 3252386 B2 JP3252386 B2 JP 3252386B2
Authority
JP
Japan
Prior art keywords
silicon single
single crystal
heat treatment
temperature
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP09772795A
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Japanese (ja)
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JPH08273991A (en
Inventor
隆 小池
正隆 宝来
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Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
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Priority to JP09772795A priority Critical patent/JP3252386B2/en
Publication of JPH08273991A publication Critical patent/JPH08273991A/en
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Publication of JP3252386B2 publication Critical patent/JP3252386B2/en
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Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】この発明は、半導体材料に使用さ
れるシリコン単結晶ウェーハをチョクラルスキー法(C
Z法)により製造する方法の改良に係り、初期絶縁破壊
特性の向上のために引上げ速度を低速で行ったシリコン
単結晶ウェーハが経時絶縁破壊特性が劣る、すなわち、
ゲート酸化膜厚が薄い場合に特に経時絶縁破壊特性が劣
ることに鑑み、非酸化性雰囲気で特定の熱処理を施して
かかる問題を解消したシリコン単結晶ウェーハの製造方
法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon single crystal wafer used for a semiconductor material.
Z method), the silicon single crystal wafer obtained at a low pulling rate to improve the initial dielectric breakdown characteristics has poor dielectric breakdown characteristics over time, that is,
In particular, the present invention relates to a method for manufacturing a silicon single crystal wafer that solves such a problem by performing a specific heat treatment in a non-oxidizing atmosphere in view of the fact that the time-dependent dielectric breakdown characteristics are particularly poor when the gate oxide film thickness is small.

【0002】[0002]

【従来の技術】MOSデバイスの高集積化とともに、ゲ
ート酸化膜の信頼性向上が重要な課題となり、シリコン
単結晶ウェーハの酸化膜として、耐圧不良のない電気的
絶縁性の優れた高品質の酸化膜が要求されている。
2. Description of the Related Art Along with the high integration of MOS devices, it has become an important issue to improve the reliability of a gate oxide film. A membrane is required.

【0003】シリコン単結晶ウェーハの酸化膜絶縁特性
は、図1に示す構造のMOSダイオードを多数形成し、
ゲート電界を階段状に増加させ、リーク電流が一定値に
達した時の電界強度で絶縁破壊強度を決定し、これを初
期絶縁破壊(time zero dielectri
c breakdown : TZDB)特性と呼ぶ
(以下TZDB特性と称す)。
[0003] The oxide film insulation properties of a silicon single crystal wafer are determined by forming a large number of MOS diodes having the structure shown in FIG.
The gate electric field is increased stepwise, and the breakdown strength is determined based on the strength of the electric field when the leak current reaches a certain value, and the breakdown strength is determined based on an initial breakdown (time zero dielectric).
c breakdown: TZDB) characteristic (hereinafter referred to as TZDB characteristic).

【0004】また、酸化膜は一定の電界印加下で経時破
壊し、経時絶縁破壊(time dependent
dielectric breakdown : TD
DB)特性と呼び(以下TDDB特性と称す)、デバイ
スの信頼性の観点からは、きわめて重要なファクターで
ある。
[0004] Further, the oxide film is broken down with the lapse of time under the application of a constant electric field, and the dielectric breakdown with time (time dependent) is performed.
dielectric breakdown: TD
DB) characteristic (hereinafter referred to as TDDB characteristic), which is a very important factor from the viewpoint of device reliability.

【0005】近年、シリコン単結晶ウェーハの酸化膜耐
圧不良がシリコン単結晶の育成方法に依存することが明
らかになっており、不良低減を目的として結晶成長速度
を低速とすることが提案され、例えば、直径100mm
以上のシリコン単結晶を製造する方法において、結晶成
長速度を0.8mm/min以下とすることが提案(特
開平2−267195号公報)されている。
In recent years, it has been revealed that the oxide film breakdown voltage defect of a silicon single crystal wafer depends on the method of growing a silicon single crystal, and it has been proposed to reduce the crystal growth rate for the purpose of reducing the defect. , Diameter 100mm
In the above method of manufacturing a silicon single crystal, it has been proposed that the crystal growth rate be 0.8 mm / min or less (Japanese Patent Application Laid-Open No. 2-267195).

【0006】[0006]

【発明が解決しようとする課題】CZ法で育成したシリ
コン単結晶は、ウェーハを高温の酸化雰囲気で熱酸化処
理したときにリング状に発生するOSF発生領域が形成
される。結晶成長速度とリング状OSFのウェーハ内の
発生位置とは対応があり、成長速度が小さくなるにつれ
て、リング状OSFの径は小さくなり、結晶成長速度が
さらに小さくなるとリング状OSFはウェーハ中央部で
消滅する。
The silicon single crystal grown by the CZ method has a ring-shaped OSF generation region formed when a wafer is thermally oxidized in a high-temperature oxidizing atmosphere. There is a correspondence between the crystal growth rate and the position where the ring-shaped OSF is generated in the wafer. As the growth rate is reduced, the diameter of the ring-shaped OSF is reduced, and when the crystal growth rate is further reduced, the ring-shaped OSF is formed at the center of the wafer. Disappear.

【0007】リング状OSFの内側と外側ではTZDB
特性が大きく異なり、リング上OSFの外側はTZDB
特性が非常に優れており、リング状OSFの内側はTZ
DB特性の劣る部分である。ここで、低速引上結晶のT
ZDB特性がすぐれているのは、リング状OSFの径が
小さく、TZDB特性が優れているリング状OSFの外
側の面積が大きいためである(S. Shinoyam
a, M. Hasebe, and T.Yamau
chi: Oyo Buturi 60 (1991)
766)。
TZDBs inside and outside the ring-shaped OSF
The characteristics are significantly different, and the outside of the OSF on the ring is TZDB
The characteristics are very good, and the inside of the ring-shaped OSF is TZ
This is a part where the DB characteristics are inferior. Here, the T of the slow pulling crystal
The reason why the ZDB characteristics are excellent is that the diameter of the ring-shaped OSF is small and the area outside the ring-shaped OSF having the excellent TZDB characteristics is large (S. Shinoyam).
a, M.A. Hasebe, and T.S. Yamau
chi: Oyo Buturi 60 (1991)
766).

【0008】ところで、高温の酸化雰囲気で熱酸化処理
したときに、リング状に発生するOSF発生領域が結晶
中央部で消滅する低速引上シリコン単結晶ウェーハは、
TZDB特性は非常に良好であるが、TDDB特性はゲ
ート酸化膜厚が100〜300Åと厚い場合には不良率
は低いが、ゲート酸化膜厚が50〜70Åと薄い場合に
不良率が急増する問題があった。また、CMOS等の熱
プロセス後のTDDB特性やリーク特性も劣化するた
め、実デバイス歩留まりが低く実用化には到っていな
い。
By the way, when a thermal oxidation process is performed in a high-temperature oxidizing atmosphere, a low-speed pulling silicon single crystal wafer in which a ring-shaped OSF generation region disappears at the center of the crystal is:
Although the TZDB characteristic is very good, the TDDB characteristic is such that the defect rate is low when the gate oxide film thickness is as large as 100 to 300 °, but increases rapidly when the gate oxide film thickness is as thin as 50 to 70 °. was there. Further, the TDDB characteristics and the leak characteristics after thermal processing of a CMOS or the like are deteriorated, so that the actual device yield is low and the device has not been put to practical use.

【0009】この発明は、チョクラルスキー法(CZ
法)により製造するシリコン単結晶ウェーハにおいて、
TZDB特性が良好な低速引上シリコン単結晶のウェー
ハの欠点を解消し、酸化膜が薄い場合及び熱プロセス後
においても、TDDB特性がすぐれているシリコン単結
晶ウェーハを得ることが可能なシリコン単結晶ウェーハ
の製造方法の提供を目的としている。
The present invention relates to the Czochralski method (CZ).
Method), the silicon single crystal wafer produced by
A silicon single crystal that eliminates the drawbacks of a low-speed pulled silicon single crystal wafer with good TZDB characteristics, and that can provide a silicon single crystal wafer with excellent TDDB characteristics even when the oxide film is thin and after a thermal process. It aims to provide a method of manufacturing a wafer.

【0010】[0010]

【課題を解決するための手段】発明者は、TZDB特性
とが良好な低速引上シリコン単結晶のウェーハの欠点で
あるTDDB特性の劣化を解消するため、その原因につ
いて種々検討した結果、熱プロセス前には特性に影響を
およぼさなかったサイズの欠陥が熱プロセス中に特性に
影響を与えるサイズまで成長したためであることに着目
し、低速引上結晶中の小さなサイズの欠陥を低減あるい
は消滅させる方法についてさらに検討した結果、非酸化
性雰囲気で特定温度の熱処理を施すことにより、該欠陥
を低減消滅できることを知見し、この発明を完成した。
The inventor of the present invention has conducted various investigations on the cause of the degradation of the TDDB characteristic, which is a drawback of a low-speed pulling silicon single crystal wafer having a good TZDB characteristic, as a result. Focusing on the fact that defects of a size that did not affect the characteristics previously grew to a size that affected the characteristics during the thermal process, reducing or eliminating small-sized defects in the slowly pulled crystal As a result of further study on a method for causing the defects, it was found that the defects can be reduced and eliminated by performing a heat treatment at a specific temperature in a non-oxidizing atmosphere, and the present invention was completed.

【0011】すなわち、この発明は、チョクラルスキー
法によりシリコン単結晶を製造する方法において、高温
の酸化性雰囲気で熱酸化処理したときにリング状に発生
するOSF発生領域が結晶中央部で消滅する条件で引き
上げたシリコン単結晶のウェーハに、非酸化性雰囲気で
温度1000℃以上1250℃以下、時間10秒以上の
熱処理を施し、その熱処理時の昇温速度および降温速度
を1℃/秒以上とすることを特徴とする酸化膜の信頼性
の優れたシリコン単結晶ウェーハの製造方法である。
That is, according to the present invention, in a method of manufacturing a silicon single crystal by the Czochralski method, a ring-shaped OSF generation region which is generated in a ring shape when subjected to thermal oxidation treatment in a high-temperature oxidizing atmosphere disappears at the center of the crystal. The silicon single crystal wafer pulled under the conditions is subjected to a heat treatment in a non-oxidizing atmosphere at a temperature of 1000 ° C. or more and 1250 ° C. or less for a time of 10 seconds or more. A method for manufacturing a silicon single crystal wafer having excellent reliability of an oxide film.

【0012】また、この発明は、高温の酸化性雰囲気で
熱酸化処理したときにリング状に発生するOSF発生領
域が結晶中央部で消滅するシリコン単結晶のウェーハと
して、CZ法での引上げ速度(結晶成長速度)が0.5
mm/min以下であるウェーハを対象としている。
Further, the present invention provides a silicon single crystal wafer in which a ring-shaped OSF generation region which is generated in a ring shape when subjected to thermal oxidation treatment in a high-temperature oxidizing atmosphere disappears at the center of the crystal. Crystal growth rate) is 0.5
It is intended for wafers of not more than mm / min.

【0013】[0013]

【作用】この発明は、ゲート酸化膜厚が薄い場合のTD
DB特性の劣化の原因は、欠陥サイズに対して酸化膜厚
が十分厚いときには特性に影響をおよぼさないが、酸化
膜厚が薄くなり、酸化膜に取り込まれるシリコンウェー
ハ表面のシリコン厚が欠陥サイズと同程度になったとき
にTDDB特性の劣化の原因となること、また、熱プロ
セス後のTDDB特性やリーク特性の劣化は、熱プロセ
ス前には特性に影響を及ぼさなかったサイズの欠陥が熱
プロセス中に特性に影響を与えるサイズまで成長したた
めであることを知見し、これを特定の熱処理で解消した
ことを特徴としている。
According to the present invention, the TD in the case where the gate oxide film is thin is used.
The cause of the deterioration of the DB characteristics is that the characteristics are not affected when the oxide film thickness is sufficiently large with respect to the defect size, but the oxide film thickness becomes thin and the silicon thickness of the silicon wafer surface taken into the oxide film becomes defective. Deterioration of TDDB characteristics when the size is about the same as above, and deterioration of TDDB characteristics and leakage characteristics after thermal processing are caused by defects of a size that did not affect the characteristics before thermal processing. It was found that it was grown to a size that affected the properties during the thermal process, and this was resolved by a specific heat treatment.

【0014】すなわち、CZ法での低速引上シリコン単
結晶ウェーハには、小さなサイズの欠陥が多いためにT
DDB特性の劣化を引き起こしており、この小さなサイ
ズの欠陥を消滅あるいは少なくすることで、TDDB特
性を向上させることができる。この発明では、低速引上
シリコン単結晶ウェーハ中の小さなサイズの欠陥を低減
あるいは消滅させるために、非酸化性雰囲気で温度90
0℃以上、1250℃以下、時間10秒以上の熱処理を
施し、その熱処理時の昇温速度およ降温速度を1℃/秒
以上とすることで、ゲート酸化膜厚が薄い場合および熱
プロセス後でもTDDB特性やリーク特性の劣化がな
く、酸化膜の信頼性が非常に優れたウェーハの製造が実
現できる。
That is, a low-speed pulled silicon single crystal wafer by the CZ method has many small-sized defects.
The DDB characteristic is deteriorated, and the TDDB characteristic can be improved by eliminating or reducing the defect having the small size. According to the present invention, in order to reduce or eliminate small-sized defects in a low-speed pulled silicon single crystal wafer, a temperature of 90 ° C. in a non-oxidizing atmosphere is used.
A heat treatment of 0 ° C. or more, 1250 ° C. or less and a time of 10 seconds or more is performed, and the temperature increase rate and the temperature decrease rate at the time of the heat treatment are set to 1 ° C./second or more. However, there is no deterioration in TDDB characteristics and leak characteristics, and it is possible to realize the manufacture of a wafer having extremely excellent reliability of an oxide film.

【0015】この発明において、熱処理温度の下限を9
00℃としているが、これは900℃未満では欠陥を消
滅することができないためである。また、熱処理温度の
上限を1250℃としているが、これは1250℃を越
えると、ウェーハのスリップや汚染の問題があり、冷却
条件によっては急冷凍結欠陥が新たに発生し特性に悪影
響を及ぼすことがあるからである。熱処理時間について
は下限を10秒としているが、これは熱処理時に欠陥を
収縮させるために必要な最低の時間である。熱処理時の
昇温速度および降温速度を1℃/秒以上としているの
は、これ以下の速度での昇温および降温では、温度の変
化時に欠陥が成長し、特性に悪影響をおよぼすからであ
る。
In the present invention, the lower limit of the heat treatment temperature is 9
The temperature is set to 00 ° C., because defects cannot be eliminated below 900 ° C. The upper limit of the heat treatment temperature is set at 1250 ° C. If it exceeds 1250 ° C., there is a problem of wafer slip and contamination, and depending on the cooling conditions, rapid cooling defects may newly occur and adversely affect the characteristics. Because there is. The lower limit of the heat treatment time is set to 10 seconds, which is the minimum time required for shrinking defects during heat treatment. The reason why the heating rate and the cooling rate during the heat treatment are set to 1 ° C./second or more is that if the heating rate and the cooling rate are lower than this rate, defects grow at the time of temperature change, which adversely affects the characteristics.

【0016】この発明の熱処理において、好ましい温度
範囲は1050℃〜1200℃、好ましい熱処理時間は
2時間〜5時間である。熱処理時間の上限については特
に規定しない。しかし、非酸化性雰囲気で高温で長時間
の熱処理でウェーハ表面に無欠陥層をつくることができ
るが、長時間の処理はコストおよび生産性の問題がある
ので、ウェーハの使用されるデバイスでの熱処理条件に
より、必要に応じて時間を決定することが望ましい。ま
た、好ましい昇温および降温速度は、5℃/秒〜100
℃/秒である。
In the heat treatment of the present invention, a preferable temperature range is 1050 ° C. to 1200 ° C., and a preferable heat treatment time is 2 hours to 5 hours. The upper limit of the heat treatment time is not particularly defined. However, although a defect-free layer can be formed on the wafer surface by a long-term heat treatment at a high temperature in a non-oxidizing atmosphere, the long-term treatment has cost and productivity problems. It is desirable to determine the time as needed according to the heat treatment conditions. Further, the preferable temperature increase and decrease rates are 5 ° C / sec to 100 ° C.
° C / sec.

【0017】[0017]

【実施例】【Example】

実施例1 成長速度0.43mm/minで引上げたCZシリコン
単結晶のウェーハ(直径6インチ、ボロンドープP型、
比抵抗4.5〜6Ωcm、酸素濃度14〜16×1017
atoms/cc、面方位(100))、すなわち、熱
酸化処理したときに、リング状に発生するOSF発生領
域が結晶中央部で消滅する低速引上シリコン単結晶のウ
ェーハに、熱処理炉を用いて、非酸化性雰囲気で昇温お
よび降温速度を5℃/秒として850℃から1300℃
までの温度で3時間熱処理した後のスリップの発生状
況、および図2に示すCMOSデバイスの熱プロセスに
相当する熱処理後の赤外干渉法によるウェーハ表面から
0〜10μmの領域の欠陥密度を表1に示す。表1より
1300℃の熱処理ではスリップが発生し、850℃の
熱処理では欠陥が減少しないことが分かる。
Example 1 A CZ silicon single crystal wafer (diameter 6 inches, boron-doped P-type, pulled at a growth rate of 0.43 mm / min,
Specific resistance 4.5-6 Ωcm, oxygen concentration 14-16 × 10 17
atoms / cc, plane orientation (100)), that is, a low-speed pulling silicon single crystal wafer in which a ring-shaped OSF generation region disappears at the center of the crystal when subjected to thermal oxidation treatment, using a heat treatment furnace. 850 ° C. to 1300 ° C. at a rate of 5 ° C./sec in a non-oxidizing atmosphere
Table 1 shows the state of occurrence of slip after heat treatment for 3 hours at temperatures up to and a defect density of 0 to 10 μm from the wafer surface by infrared interferometry after heat treatment corresponding to the heat process of the CMOS device shown in FIG. Shown in It can be seen from Table 1 that the heat treatment at 1300 ° C. causes a slip and the heat treatment at 850 ° C. does not reduce defects.

【0018】[0018]

【表1】 [Table 1]

【0019】実施例2 成長速度0.43mm/minで引上げたCZシリコン
単結晶のウェーハ(直径6インチ、ボロンドープP型、
比抵抗4.5〜6Ωcm、酸素濃度14〜16×1017
atoms/cc、面方位(100))に、熱処理炉を
用いて2%の酸素を含む窒素雰囲気において昇温および
降温速度を5℃/秒として1200℃で2時間の熱処理
を施した。ウェーハの評価として、図1に示す構造のM
OSダイオードを、ゲート酸化を900℃乾燥酸素中で
行い、酸化膜厚70Å、電極としてボロンドープポリシ
リコンを5000Å厚みに、電極面積8mm2の条件で
作製した。TDDB特性の測定条件は、電流密度が1m
A/cm2、温度が室温、判定電圧が5V以下で、ゲー
ト酸化膜厚を70Åとして定電流TDDB特性を評価し
た。
Example 2 CZ silicon single crystal wafer (diameter 6 inches, boron-doped P-type, pulled at a growth rate of 0.43 mm / min)
Specific resistance 4.5-6 Ωcm, oxygen concentration 14-16 × 10 17
(atoms / cc, plane orientation (100)) was subjected to a heat treatment at 1200 ° C. for 2 hours at a rate of 5 ° C./sec in a nitrogen atmosphere containing 2% oxygen using a heat treatment furnace. As an evaluation of the wafer, M of the structure shown in FIG.
The OS diode was manufactured by performing gate oxidation at 900 ° C. in dry oxygen, an oxide film thickness of 70 °, boron-doped polysilicon as an electrode at 5000 ° thickness, and an electrode area of 8 mm 2 . The measurement condition of the TDDB characteristic is that the current density is 1 m
The constant current TDDB characteristics were evaluated with A / cm 2 , a temperature of room temperature, a determination voltage of 5 V or less, and a gate oxide film thickness of 70 °.

【0020】また、図2に示すヒートパターンのCMO
Sデバイスの熱プロセスに相当する熱処理を施した後、
ゲート酸化膜厚70Åのときの定電流TDDB特性を評
価した。比較のために、熱処理なしの従来の低速引上結
晶のウェーハの評価も実施した。従来例とこの発明のウ
ェーハの評価結果をまとめて表2に示す。ここでTDD
B特性を示す20%Qbdは、累積不良率が20%に達
するまでの通過電荷量(C/cm2)であり、この値が
大きいほどTDDB特性が優れていることを示す。
The CMO of the heat pattern shown in FIG.
After performing the heat treatment corresponding to the thermal process of the S device,
The constant current TDDB characteristic when the gate oxide film thickness was 70 ° was evaluated. For comparison, an evaluation of a conventional low-speed pulled crystal wafer without heat treatment was also performed. Table 2 summarizes the evaluation results of the conventional example and the wafer of the present invention. Where TDD
The 20% Qbd indicating the B characteristic is the amount of passing charge (C / cm 2 ) until the cumulative failure rate reaches 20%, and the larger the value, the better the TDDB characteristic.

【0021】表2より明らかなように、ゲート酸化膜厚
が70Åの場合、従来の低速引上結晶のウェーハ(サン
プルA)では20%Qbdが70であるのに対して、こ
の発明のウェーハ(サンプルB)では150まで増加し
ている。また、CMOS熱処理後では、従来の低速引上
結晶のウェーハ(サンプルC)では20%Qbdが6で
あるのに対して、本発明のウェーハ(サンプルD)では
132まで増加している。欠陥の低減効果の確認のた
め、表2のサンプルCとDについて赤外干渉法によりウ
ェーハ表面から0〜10μmの領域を評価した。比較例
のサンプルCでは3.6×107/cm3の欠陥が観察さ
れたのに対して、本発明のサンプルDでは1.2×10
5ケ/cm3まで減少しTDDB特性との対応が見られ
た。
As apparent from Table 2, when the gate oxide film thickness is 70 °, the 20% Qbd is 70 in the conventional low-speed pulling crystal wafer (Sample A), whereas the wafer of the present invention ( In sample B), it has increased to 150. Further, after the CMOS heat treatment, the 20% Qbd is 6 in the conventional low-speed pulling crystal wafer (sample C), while it is increased to 132 in the wafer of the present invention (sample D). To confirm the effect of reducing defects, samples C and D in Table 2 were evaluated in a region of 0 to 10 μm from the wafer surface by infrared interferometry. In sample C of the comparative example, a defect of 3.6 × 10 7 / cm 3 was observed, whereas in sample D of the present invention, 1.2 × 10 7 / cm 3.
The number was reduced to 5 / cm 3, and a correspondence with the TDDB characteristic was observed.

【0022】実施例3 成長速度0.48mm/minで引上たCZシリコン単
結晶のウェーハ(直径6インチ、ボロンドープP型、比
抵抗4.5〜6Ωcm、酸素濃度14〜16×1017
tomos/cc、面方位(100))に、ランプアニ
ール炉を用いて窒素雰囲気において、昇温および降温速
度を100℃/秒として1100℃で20秒のランプア
ニール処理を施した。ウェーハの評価として、実施例2
と同様の測定条件で、ゲート酸化膜厚を70Åとして定
電流TDDB特性を評価した。
Example 3 A CZ silicon single crystal wafer pulled up at a growth rate of 0.48 mm / min (diameter: 6 inches, boron-doped P type, specific resistance: 4.5 to 6 Ωcm, oxygen concentration: 14 to 16 × 10 17 a)
tomos / cc, plane orientation (100)), in a nitrogen atmosphere using a lamp annealing furnace, a lamp annealing treatment was performed at 1100 ° C. for 20 seconds at a temperature increase / decrease rate of 100 ° C./second. Example 2 for wafer evaluation
Under the same measurement conditions as those described above, the constant current TDDB characteristic was evaluated with a gate oxide film thickness of 70 °.

【0023】比較のために、ランプアニール処理なしの
従来の低速引上結晶のウェーハの評価も実施した。従来
例と本発明のウェーハの評価結果をまとめて表4に示
す。表4より明らかなように、ゲート酸化膜厚が70Å
の場合、従来の低速引上結晶のウェーハ(サンプルE)
では20%Qbdが63であるのに対して、本発明のウ
ェーハ(サンプルE)では169まで増加している。
For comparison, a conventional low-speed pulled crystal wafer without lamp annealing was also evaluated. Table 4 summarizes the evaluation results of the conventional example and the wafer of the present invention. As is clear from Table 4, the gate oxide film thickness was 70 °
In the case of, the wafer of the conventional slow pulling crystal (Sample E)
In this case, the 20% Qbd is 63, whereas the wafer (sample E) of the present invention has increased to 169.

【0024】[0024]

【表2】 [Table 2]

【0025】[0025]

【発明の効果】この発明は、熱プロセス中に特性に影響
を与えるサイズまで成長する低速引上結晶中の小さなサ
イズの欠陥を、実施例に示すごとく、非酸化性雰囲気で
特定温度の熱処理を施すことにより低減消滅するもの
で、この発明の方法によればゲート酸化膜厚が薄い場
合、および熱プロセス後でもTDDB特性の優れたシリ
コン単結晶ウェーハが得られ、特に高性能デバイス用と
して従来では得られなかった高品質のウェーハを容易に
得ることができる。
According to the present invention, a small-sized defect in a low-speed pulled crystal that grows to a size that affects properties during a thermal process can be subjected to a heat treatment at a specific temperature in a non-oxidizing atmosphere as shown in the embodiment. The method according to the present invention can provide a silicon single crystal wafer having excellent TDDB characteristics even when the gate oxide film thickness is small and after the thermal process. High quality wafers that could not be obtained can be easily obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】MOSダイオードの構造を示す説明図である。FIG. 1 is an explanatory diagram showing a structure of a MOS diode.

【図2】CMOS熱処理条件を時間と温度との関係で示
すヒートパターン図である。
FIG. 2 is a heat pattern diagram showing CMOS heat treatment conditions as a function of time and temperature.

フロントページの続き (56)参考文献 特開 平7−14755(JP,A) 特開 平5−213696(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/02 C30B 15/00 C30B 33/00 Continuation of the front page (56) References JP-A-7-14755 (JP, A) JP-A-5-213696 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H01L 21 / 02 C30B 15/00 C30B 33/00

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 チョクラルスキー法によりシリコン単結
晶を製造する方法において、高温の酸化性雰囲気で熱酸
化処理したときにリング状に発生するOSF発生領域が
結晶中央部で消滅する条件で引き上げたシリコン単結晶
のウェーハに、非酸化性雰囲気で温度900℃以上、1
250℃以下、時間10秒以上の熱処理を施し、その熱
処理時の昇温速度および降温速度を1℃/秒以上とする
ことを特徴とするシリコン単結晶ウェーハの製造方法。
In a method of manufacturing a silicon single crystal by a Czochralski method, a ring-shaped OSF generation region which is generated by thermal oxidation treatment in a high-temperature oxidizing atmosphere is pulled up under such a condition that it disappears at the center of the crystal. A temperature of 900 ° C. or more in a non-oxidizing atmosphere
A method for producing a silicon single crystal wafer, wherein a heat treatment is performed at a temperature of 250 ° C. or less for a time of 10 seconds or more, and a temperature increasing rate and a temperature decreasing rate during the heat treatment are set to 1 ° C./sec or more.
【請求項2】 請求項1において、シリコン単結晶ウェ
ーハの引上げ速度(結晶成長速度)が0.5mm/mi
n以下であることを特徴とするシリコン単結晶ウェーハ
の製造方法。
2. The method according to claim 1, wherein the pulling speed (crystal growth speed) of the silicon single crystal wafer is 0.5 mm / mi.
n. A method for producing a silicon single crystal wafer, wherein n is equal to or less than n.
JP09772795A 1995-03-29 1995-03-29 Manufacturing method of silicon single crystal wafer Expired - Fee Related JP3252386B2 (en)

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JP3252386B2 true JP3252386B2 (en) 2002-02-04

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JP6118765B2 (en) * 2014-07-03 2017-04-19 信越半導体株式会社 Heat treatment method for silicon single crystal wafer
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