JP3250143B2 - Simulated fault generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a simulated fault generating circuit, and more particularly to a circuit in which a maintenance person or a developer causes a simulated fault in a designated data line in block data transferred on a data transmission line.

[0002]

2. Description of the Related Art Conventionally, in a data transmission line of this type, line data obtained by dividing one block data in a fixed unit is continuously transferred, and a failure occurs in this data transmission line in a pseudo manner. Then, there is a method of checking whether the maintenance processing or the like operates normally.

As a method for generating the above-mentioned pseudo failure, an output register and an input register for storing and outputting divided line data in the middle of a data transmission line are arranged, and the output register and the input register are arranged. In some cases, a failure generating circuit is provided which edits line data output from the output-side register, converts the line data into line data which causes a failure, and transfers the line data to the input-side register.

[0004] This fault generating circuit is provided with a pseudo fault instruction (hereinafter, referred to as a pseudo fault instruction).
The conversion operation is performed when a false indication is received from the holding bit (which is referred to as a false indication). In addition, the false failure indication holding bit is used by maintenance personnel and developers for failure analysis,
Store and output a false fault instruction that intentionally causes a fault,
Invalidate false indication by external input.

The fault detecting circuit checks the line data output from the input register, and outputs a reset signal to a false fault indication holding bit when a fault exists on the line data.

When a maintenance person or a developer intentionally causes a fault, a false fault instruction is stored in the false fault instruction holding bit from the outside, so that the false fault instruction is continuously output to the fault generating circuit. When the line data is output from the output-side register, the failure generating circuit converts the line data into line data that causes a failure and outputs the line data to the input-side register.

[0007] The fault detection circuit checks the output of the input register to which the line data causing the fault is input, and when the fault is detected, notifies the fault occurrence to the pseudo fault indication holding bit by a reset signal. When the reset signal from the fault detection circuit is input to the false fault indication holding bit, the stored false fault indication is invalidated, so that only one fault can be intentionally given to the block data.

On the other hand, without modifying the data in advance,
Japanese Patent Application Laid-Open No. 63-19324 discloses a method of causing a pseudo failure for an arbitrary word during data transfer of words or more.
No. 8 discloses this.

As shown in FIG. 2, a circuit using this method includes a pseudo failure register 21 and a word setting register 22.
, A pseudo-failure generating circuit 23, a word-specific pseudo-failure timing generating circuit 24, error detecting circuits 25 and 26, and an error register 27. Data transfer of two or more words is possible by one memory access. The pseudo-failure is given to various error detection circuits in a simple storage device.

The pseudo fault register 21 is set with the pseudo fault to be generated, and the word setting register 22 is set with the word of the pseudo fault of the data. The word-based pseudo-failure timing generation circuit 24 generates a pseudo-failure timing based on the values of the pseudo-failure register 21 and the word setting register 22.

The simulated fault generating circuit 23 generates a simulated fault from the output of the simulated fault register 21 and the word-based simulated fault timing generating circuit 24, and generates error detecting circuits 25 and 26.
Detects various faults from the output of the pseudo fault generating circuit 23. The error register 27 holds error information detected by the error detection circuits 25 and 26.

In the above circuit, before the occurrence of the pseudo failure,
First, error data to be generated is set in the pseudo failure register 21, and the order of words in which a pseudo failure is to be generated is set in the word setting register 22.

When an access is made from the processing unit and data transfer is executed, a pseudo-failure timing generation circuit 2 for each word
Reference numeral 4 outputs a timing signal for generating a pseudo fault according to the error data set in the pseudo fault register 21 and the order of the words set in the word setting register 4. The simulated fault generating circuit 23 generates a simulated fault based on the value of the simulated fault register 21 and the output of the word-based simulated fault timing generating circuit 24. When this is detected by the error detecting circuits 25 and 26, error information is set in the error register 27. Is done.

[0014]

In the above-described conventional pseudo failure generation method, one failure can be artificially given to one block data. However, line data at an arbitrary position in the block data can be added to the block data. On the other hand, a failure cannot be simulated.

On the other hand, without modifying the data in advance,
In the case of a method in which a pseudo-failure is generated for an arbitrary word during data transfer of more than words, if a real failure occurs in a word other than the word in which a pseudo-failure is to be generated, error information when the pseudo-failure occurs is generated. Instead, the error information of the real failure is set in the error register, so that the intended result cannot be obtained.

Accordingly, an object of the present invention is to solve the above-mentioned problems, to make it possible to simulate a fault in line data at an arbitrary position in block data, and to obtain accurate error information. It is an object of the present invention to provide a simulated fault occurrence circuit that can perform the above-described steps.

[0017]

A simulated fault occurrence circuit according to the present invention generates a simulated fault in line data in a data transmission line for continuously transferring each line data obtained by dividing one block data into fixed units. A false failure generating circuit that counts the number of the line data transferred through the data transmission path, and that holds a position of the line data that is set in advance and that causes the false failure. Means, comparing means for comparing the count value of the counting means with the content held in the holding means, and a fault for converting the line data detected as coincident by the comparing means into line data causing the pseudo fault Generating means, a fault detecting means for detecting a fault in the line data, and a detection result of the fault detecting means corresponding to a comparison result of the comparing means. And a storage means for storing Te.

That is, the simulated fault generating circuit of the present invention comprises:
In order to solve the above problem, a line counter circuit that counts the number of line data being transferred, and a line instruction register that holds the count value of the line counter circuit and the position of line data that causes a pseudo failure And a circuit for separately storing error information in accordance with the result of the comparison circuit.

This makes it possible to cause a pseudo failure in line data at an arbitrary position in the block data, and to obtain accurate error information.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a pseudo failure generating circuit according to one embodiment of the present invention. In the figure, a pseudo failure generating circuit according to one embodiment of the present invention includes an output register 1, an input register 2, an output valid flag 3, an input valid flag 4, a line instruction register 5, a pseudo failure instruction, A bit (hereinafter referred to as false indication bit) 6, a line counter circuit 7, a comparison circuit 8,
The circuit includes AND circuits 9, 12, and 14, a failure generation circuit 10, a failure detection circuit 11, a NOT circuit 13, and an error register 15.

The simulated fault occurrence circuit according to one embodiment of the present invention has the above-described configuration, and thus a data transmission path (not shown) for continuously transferring each line data obtained by dividing one block data in a predetermined unit. ), A pseudo failure has occurred.

The output side register 1 exists in the middle of the data transmission path, and stores and outputs divided line data.
The input register 2 also exists in the middle of the data transmission path, and stores and outputs the line data output from the output register 1.

The false failure instruction bit 6 is set by a maintenance person and a developer to perform failure analysis, and stores and outputs a false failure instruction (hereinafter, referred to as a false failure instruction) for intentionally causing a failure. . The line instruction register 5 stores and outputs the position of the line data in the block data which is set by the maintainer, the developer, and the like, and which causes a pseudo failure.

The output side valid flag 3 is synchronized with the line data input to the output side register 1, and indicates that the line data in the output side register 1 is valid when the flag is set. If the output side valid flag 3 is not set, the line data in the output side register 1 is invalid (data transfer is not performed).
It is shown that.

The line counter circuit 7 counts up only when the output side valid flag 3 is set, and clears the count value when the flag is not set. The comparison circuit 8 compares the count value of the line counter circuit 7 with the value of the line instruction register 5 and, when indicating the same line data position, outputs the logical signal “1” (coincidence signal) to the NOT circuit 13 and the AND circuit 9. Output to

The NOT circuit 13 inverts the logical value from the comparison circuit 8. When receiving the coincidence signal from the comparison circuit 8, the AND circuit 9 outputs a false fault indication of the false fault indication bit 6 to the fault generating circuit 10 and the AND circuit 12.

The fault generating circuit 10 exists between the output side register 1 and the input side register 2 and usually transfers the line data output from the output side register 1 to the input side register 2 as it is. However, when the false fault instruction from the false fault instruction bit 6 is input via the AND circuit 9, the fault generating circuit 10 edits the line data output from the output side register 1 so that the fault data can be generated. And the line data is transferred to the input side register 2.

The fault detection circuit 11 checks the line data output from the input register 2 and, if a fault exists on the line data, outputs a fault occurrence signal to the AND circuit 1.
4 and to the AND circuit 12. AND circuit 14 is N
Based on the comparison result of the comparison circuit 8 input via the OT circuit 13, a failure occurrence signal from the failure detection circuit 11 is set in the error register 15. The AND circuit 12 generates a signal based on the comparison result of the comparison circuit 8 input via the AND circuit 9.
The fault occurrence signal from the fault detection circuit 11 is set in the error register 15.

The error register 15 individually holds a failure occurrence signal input via the AND circuit 14 or the AND circuit 12. Although not shown, the error register 15 can be read from a device that performs a failure process.

The operation of the pseudo failure generating circuit according to one embodiment of the present invention will be described with reference to FIG. When a maintenance person and a developer intentionally cause a failure, first, the position of the line data at which the failure is to be caused (the position from the beginning of a plurality of line data to be transferred) is set in the line instruction register 5. At the same time, when the maintenance person or the developer sets a false fault instruction in the false fault instruction bit 6, the false fault instruction bit 6 stores the false fault instruction and keeps outputting the false fault instruction to the AND circuit 9.

After the above settings are made in advance, if the line data is successively transferred to the data transmission path (output side register 1 → failure occurrence circuit 10 → input side register 2), the output valid flag 3 is set to the line Since the data is transferred continuously, the line counter circuit 7 counts up the number of line data that has passed through the output side register 1 and indicates the position from the head of the plurality of line data.

The comparison circuit 8 compares the count value of the line counter circuit 7 with the value of the line instruction register 5. When the comparison result of the comparing circuit 8 indicates a match, the false fault instruction continuously output from the false fault instruction bit 6 is output to the fault generating circuit 10 and the AND circuit 12 via the AND circuit 9. At this time, the NOT circuit 13 inverts the logic signal “1” (indicating a match) from the comparison circuit 8 and outputs a logic signal “0” to the AND circuit 14.

When the false fault instruction is input, the fault generating circuit 10 embeds a fault in the line data from the output register 1 and outputs the faulted line data to the input register 2.

In this case, since the fault detecting circuit 11 detects a fault from the line data passing through the input side register 2, the fault detecting circuit 11 outputs a fault occurrence signal (logical signal “1”) to the AND circuit 12.
And an AND circuit 14.

Since the AND circuit 14 receives the logic signal "0" from the NOT circuit 13, it does not output a fault occurrence signal to the error register 15, but the AND circuit 12 outputs
Since a false fault signal (logic signal “1”) is received from the D circuit 9, a fault occurrence signal is output to the error register 15. When a failure occurrence signal is output from the AND circuit 12, the error register 15 holds information indicating that a failure has occurred in a pseudo manner.

On the other hand, when the comparison result of the comparison circuit 8 indicates a mismatch, that is, when the data line does not intentionally cause a pseudo fault, a logic signal "0" indicating the mismatch is output from the comparison circuit 8. The false fault instruction continuously output from the false fault instruction bit 6 is not output from the AND circuit 9 to the fault generating circuit 10. Therefore, the fault occurrence circuit 10 does not embed a fault in line data other than the position indicated by the line instruction register 5.

Here, when a real fault occurs on the data line being transferred, the fault detecting circuit 11 detects the fault and outputs a fault occurrence signal to the AND circuit 12 and the AND circuit 14.

In this case, the AND circuit 12 does not receive the false fault signal (logic signal "1") from the AND circuit 9 because the comparison result of the comparison circuit 8 does not match. No output, but AND circuit 1
4 receives the logic signal “1” by the NOT circuit 13, and outputs a fault occurrence signal to the error register 15. When a failure occurrence signal is output from the AND circuit 14, the error register 15 holds information indicating that a failure has actually occurred.

As described above, the number of line data transferred via the data transmission path is counted by the line counter circuit 7, and the count value is compared with the position preset in the line instruction register 5 by the comparison circuit 8. Then, the line data for which the coincidence is detected is converted into line data in which a simulated fault occurs in the fault generating circuit 10, and the detection result of the fault detecting circuit 11 for detecting a fault in the line data is compared by the comparing circuit 8 Error register 1 corresponding to the result
5, the maintenance process and the developer can intentionally cause a failure process for a failure on any line data of the block data, so that the coverage of evaluation can be improved.

When a pseudo failure is to be generated for an arbitrary word at the time of data transfer of two or more words, even if a real failure occurs in a word other than the word for which the pseudo failure is to be generated, the pseudo failure may occur. Is set in the error register 15 in addition to the error information at the time of the occurrence of the error, it is possible to distinguish the intended pseudo failure from the unintended actual error.

Therefore, it is possible to discriminate the error information of the unintended real failure from the error information of the failure which is artificially generated intentionally, and it is possible to determine whether or not the error is the artificially generated failure. Therefore, accurate error information can be obtained.

Accordingly, it is possible to realize a pseudo-failure generating circuit capable of generating a pseudo-failure for line data at an arbitrary position in block data and obtaining accurate error information.

[0043]

As described above, according to the present invention, a pseudo-failure that causes a pseudo-failure in line data on a data transmission path for continuously transferring each line data obtained by dividing one block data in a predetermined unit. In the generation circuit,
The number of line data transferred via the data transmission path is counted, and the counted value is compared with a preset position of the line data that causes a pseudo-failure, and the line data indicating a match indicates that a pseudo-failure occurs. By converting the line data to the appropriate line data and storing the line data failure detection result in correspondence with the comparison result, it is possible to cause a pseudo failure in the line data at an arbitrary position in the block data. There is an effect that accurate error information can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a pseudo failure generating circuit according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a pseudo failure generating circuit according to a conventional example.

[Explanation of symbols]

 Reference Signs List 1 output-side register 2 input-side register 3 output-side valid flag 4 input-side valid flag 5 line instruction register 6 pseudo failure instruction bit 7 line counter circuit 8 comparison circuit 9, 12, 14 AND circuit 10 failure generation circuit 11 failure detection circuit 13 NOT circuit 15 Error register

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22 360 G06F 13/00 310

Claims (4)

(57) [Claims] 1. A pseudo-failure generating circuit for generating a pseudo-failure in line data in a data transmission path for continuously transferring line data obtained by dividing one block data in a predetermined unit, wherein the data transmission path Counting means for counting the number of the line data transferred via
A holding unit that holds a position of the line data that is set in advance and causes the pseudo failure; a comparing unit that compares a count value of the counting unit with a held content of the holding unit; and a match is detected by the comparing unit. Fault generating means for converting the obtained line data into line data causing the pseudo fault, fault detecting means for detecting a fault in the line data, and comparing the detection result of the fault detecting means with the comparing means. And a storage means for storing the pseudo-failure in accordance with (1). 2. The storage means according to claim 1, wherein said fault detecting means detects a fault in said line data when said comparing means detects a match and when said comparing means does not detect a match. 2. The simulated fault occurrence circuit according to claim 1, wherein the simulated fault occurrence circuit is configured to be stored separately. 3. The apparatus according to claim 1, wherein said counting means is configured to count the number of line data validated from outside of said line data transferred via said data transmission path. 3. The pseudo failure generating circuit according to claim 2. 4. The fault occurrence means is configured to convert the line data, for which the occurrence of the pseudo fault is instructed from the outside and a match is detected by the comparing means, into line data that causes the pseudo fault. 4. The simulated fault occurrence circuit according to claim 1, wherein: