JP3246909B2 - Manufacturing method of electronic circuit unit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic circuit unit which is suitable for miniaturization and can be mass-produced excellently. SOLUTION: This electronic circuit unit is manufactured in such a way that, after circuit elements containing capacitors C1-C7, resistors R1-R3, inductance elements L1-L3, etc., are formed on a large-sized alumina substrate 1A in the form of thin films, and a bare semiconductor chip of a diode D1 and a transistor Tr1 is wire-bonded, the substrate 1A is divided into strip-like substrates 1B, and end-face electrodes 3 are provided on both side faces of each divided strip-like substrate 1B. Then a continuous cover body 2A having a U-shaped cross section is put on each substrate 1B by sliding, and leg pieces 2a of the cover body 2A formed by bending the body 2A are soldered to the end-face electrodes 3 of each substrate 1B. Thereafter, the finished product of the electronic circuit unit having a cover 2 attached to each alumina substrate 1 are obtained by cutting the cover body 2A and substrate 1B at intervals in the lengthwise direction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an electronic circuit unit having a cover for shielding.

[0002]

2. Description of the Related Art Generally, an electronic circuit unit of this type is formed by soldering a chip component such as a resistor or a capacitor or a semiconductor component such as a transistor to a solder land of a conductive pattern provided on a rectangular flat board. , And these circuit components are schematically configured to be covered with a cover for shielding. The substrate is composed of a multi-layer substrate, and a microstrip line is provided in the inner layer between the ground conductors. A plurality of grounding electrodes, input electrodes and output electrodes are provided on the side surface of the substrate, and among these electrodes, the grounding electrode is soldered to a leg of a cover attached to the substrate. The input electrode and the output electrode are soldered to solder lands on a motherboard for surface mounting the electronic circuit unit. Usually, such a substrate is obtained by subdividing a large-sized substrate along a grid-like dividing line, and a cover is attached to each of the subdivided substrates.

[0003]

In recent years, techniques for miniaturizing circuit components such as chip components and semiconductor components have been remarkably advanced. For example, ultra-small chip resistors or chips having an outer dimension of about 0.6 × 0.3 mm have been developed. Capacitors have also been put to practical use. Therefore, in the prior art described above, if such small circuit components are used and these circuit components are mounted on a board with a reduced pitch between the components, the electronic circuit unit can be downsized to some extent. It becomes possible. However, there is a limit to the miniaturization of circuit components such as chip components and semiconductor components, and furthermore, when mounting a large number of circuit components on a substrate, it is necessary to prevent short-circuiting of the soldered portion of each circuit component. For this reason, there is a limit in narrowing the pitch between components, and these are factors that hinder further miniaturization of the electronic circuit unit. Further, when the external dimensions of the substrate and the cover are reduced with the miniaturization of the electronic circuit unit, the work of attaching the cover to the substrate becomes complicated, and there is a problem that mass productivity is reduced.

[0004] The present invention has been made in view of such a situation of the prior art, and an object of the present invention is to provide an electronic circuit unit suitable for miniaturization and excellent in mass productivity.

[0005]

In order to achieve the above object, a method of manufacturing an electronic circuit unit according to the present invention comprises:
After forming a thin film of a circuit element including a capacitor, a resistor and an inductance element and wire bonding a semiconductor bare chip on a large-sized substrate made of an alumina material, a step of dividing the large-sized substrate into a plurality of strip-shaped substrates,
Providing end surface electrodes on both side surfaces along the longitudinal direction of the strip-shaped substrate, and applying a cover continuum obtained by bending a metal plate to a U-shaped cross section on the strip-shaped substrate; Soldering the leg pieces bent on both sides in the direction to the end surface electrode, cutting the continuous cover and the strip-shaped substrate into a plurality at predetermined intervals in the longitudinal direction after soldering, and Obtaining a finished product in which a cover is attached to an alumina substrate.

According to such a structure, a circuit element including a capacitor, a resistor and an inductance element is formed with high precision by using a thin film technique, and a semiconductor element is formed by wire bonding a bare chip. The required circuit components are mounted at a high density, and a surface mount type electronic circuit unit suitable for miniaturization can be realized. Further, after combining and integrating the strip-shaped substrate and the cover continuous body, the both are cut by laser, dicing, or the like, so that a completed electronic circuit unit is obtained, so that mass productivity can be improved.

In the above arrangement, when combining the strip-shaped substrate and the cover continuum, one of the cover continuum and the strip-shaped substrate is slid in the longitudinal direction with respect to the other, so that the leg of the cover continuity is moved. It is preferable to insert a strip-shaped substrate between the pieces, so that deformation of the leg pieces of the continuous cover can be prevented. in this case,
By providing an insertion guide wider than the width of the strip-shaped substrate along the width direction at the longitudinal end of the continuous cover, the strip-shaped substrate can be smoothly inserted between the legs of the continuous cover. .

In the above structure, if a notch extending in the lateral direction is formed in advance in the cover continuum while leaving the connecting portion, the cut portion of the cover continuum can be only the connecting portion. And the strip-shaped substrate can be easily cut at once.

[0009]

1 is a perspective view of an electronic circuit unit, FIG. 2 is a plan view of an alumina substrate showing a circuit configuration layout, and FIG. 4 is a back view of the alumina substrate, FIG. 4 is an explanatory view of a circuit configuration, FIG. 5 is a perspective view showing an end face electrode, FIG. 6 is a sectional view of the end face electrode, FIG. 7 is an explanatory view showing a relationship between a semiconductor bare chip and a connection land. FIG. 8 is an explanatory diagram showing a manufacturing process until a strip-shaped substrate is obtained, and FIG. 9 is an explanatory diagram showing a manufacturing process until a completed electronic circuit unit is obtained from the strip-shaped substrate and the continuous cover.

The electronic circuit unit according to the present embodiment is an example of application to a frequency tuning type booster amplifier, and this frequency tuning type booster amplifier improves the reception performance (particularly, reception sensitivity and anti-jamming characteristics) of a portable television device. It has a function of selecting a TV signal of a desired frequency, amplifying the selected TV signal and inputting the amplified signal to the UHF tuner.

FIG. 1 shows an appearance of such a frequency tuning type booster amplifier (electronic circuit unit). As shown in FIG. 1, the frequency tuning type booster amplifier includes an alumina substrate 1 on which circuit components described later are mounted, and It comprises a shield cover 2 attached to the alumina substrate 1 and is a surface mount component to be soldered to a mother substrate (not shown). The alumina substrate 1 is formed in a rectangular flat plate shape. The alumina substrate 1 is obtained by cutting a large-sized substrate into strip-shaped divided pieces, and further subdividing the divided pieces. The cover 2 is obtained by cutting a continuous cover made of a metal plate.
Covered by

As shown in FIG. 2, circuit components and conductive patterns for connecting them are provided on the front surface of the alumina substrate 1, and as shown in FIG. A conductive pattern as an electrode is provided. The frequency tuning type booster amplifier according to the present embodiment has a tuning circuit and an amplifier circuit for selecting and amplifying a TV signal, and has a circuit configuration as shown in FIG.
Each circuit component shown in FIG. 2 is denoted by a reference numeral corresponding to the circuit diagram of FIG. However, FIG. 4 shows an example of the circuit configuration, and the present invention can be applied to an electronic circuit unit having another circuit configuration.

As shown in FIG. 4, the frequency tuning type booster amplifier includes capacitors C1 to C7, resistors R1 to R3, inductance elements L1 to L3, a diode D1, a transistor T1 which are circuit components of a tuning circuit and an amplifier circuit.
r 1, conductive paths S 1, S 2, etc., and these circuit components and the conductive patterns connecting them are provided on the surface of the alumina substrate 1. This conductive pattern is formed, for example, of Cr, Cu, or the like by using a thin film technique such as sputtering, and is denoted by a symbol P in FIG.

The circuit configuration of the frequency tuning type booster amplifier will be briefly described. In order to select and amplify a TV signal of a desired frequency, a tuning circuit including inductance elements L2 and L3, capacitors C3 and C4 and a diode D1; It comprises an amplifier circuit comprising a transistor Tr1, its peripheral circuit elements (resistors R1 to R3, capacitor C6) and an unbalanced / balanced conversion element T. TV signals of a plurality of frequencies are input to the tuning circuit via the capacitor C1. Since the tuning frequency (resonance frequency) of the tuning circuit is variable by controlling the voltage (Vctl) applied to the cathode of the diode D1, by matching the frequency of the desired TV signal, only the desired TV signal is selected and the capacitor C5 is selected. Through the transistor T of the amplifier circuit
Input to the base of r1. A bias voltage is applied to the base bias voltage dividing resistors R1 and R2 at the base of the transistor Tr1, and the collector current (≒ emitter current) of the transistor Tr1 is set by the resistance value of the emitter resistor R3. The TV signal amplified by the transistor Tr1 is output from a collector, and the collector is provided with an unbalanced / balanced conversion element T. The unbalanced / balanced conversion element T is constituted by an inductance element composed of a pair of conductive paths S1 and S2 coupled to each other.
2 output a balanced TV signal from both ends of the UHF
Input to the tuner.

As shown in FIG. 2, the ground electrode (GND) and the input electrodes (Vcc, Vct)
1, RFin) and an output electrode (RFout), which are formed by a part of the conductive pattern P. The ground electrode, the input electrode, and the output electrode are formed only on the two long sides facing each other of the rectangular alumina substrate 1, and are not formed on the other two short sides facing each other. That is, GND electrodes are formed at both corners (corners) on one long side of the alumina substrate 1, and a Vcc electrode, an RFin electrode, and a Vctl electrode are formed between these GND electrodes. In addition, GND electrodes are formed at both corners on the other long side of the alumina substrate 1 and three places near the two corners, and two RFout electrodes are formed between these GND electrodes. As will be described later, the two long sides of the alumina substrate 1 correspond to the dividing lines when the large-sized substrate is cut into strip-shaped divided pieces, and the two short sides of the alumina substrate 1 further connect the divided pieces. It corresponds to the division line when subdividing.

On the other hand, as shown in FIG.
The conductive pattern P1 (rear electrode) provided on the back surface of each of the ground electrodes (GND) and the input electrodes (Vcc, V
ctl, RFin) and the output electrode (RFout), and both are electrically connected via the end face electrode 3 as shown in FIGS. The end face electrode 3 is obtained by sequentially laminating a Ni base plating layer and an Au plating layer on an Ag thick film layer, and the lowermost Ag thick film layer is made of Ag containing no glass component.
After the paste is formed into a thick film, the paste is made of a low-temperature fired material fired at about 200 ° C. The intermediate Ni plating layer facilitates the adhesion of the Au plating layer, and the uppermost Au plating layer is formed when the end face electrode 3 is soldered to a solder land of a mother substrate (not shown). This is for preventing the lower layer Ag from depositing on the solder. Then, in a completed electronic circuit unit in which the cover 2 is attached to the alumina substrate 1, a leg piece 2a formed by bending the side surface of the cover 2 is connected to the ground electrode (GND).
, And the cover 2 is connected to the 4
The corner is grounded.

Among the above-described circuit components, the capacitors C1 to C7 are formed by laminating an upper electrode on a lower electrode via a dielectric film such as SiO ₂ , and these are formed as thin films by sputtering or the like. ing. C on the surface of the upper electrode
A u layer is provided, and the Q of the resonance circuit is increased by the Cu layer. The lower electrode and the upper electrode of the capacitors C1 to C7 are connected to the conductive pattern P, and as shown in FIG. 2, the conductive pattern P between the capacitor C7 and the Vcc electrode, the conductive pattern P between the capacitor C7 and the RFout electrode, Each of the conductive patterns P between the C2 and Vctl electrodes is provided with a proximity part (air gap) G for discharge. The proximity portion G is constituted by a pair of protrusions provided on each of the conductive patterns P arranged side by side facing each other, and the tips of both protrusions face each other with a predetermined gap. . In this case, the conductive pattern P
In addition, since the dimensional accuracy of the gate electrode and the GND electrode is improved by the thin film technology, the gap dimension of the adjacent portion G can be narrowed, and discharge at a low voltage is possible. Further, among the capacitors C1 to C7, the capacitors C1 and C3 to C5
Is formed in a simple square shape, but the capacitors C2 and C7 are formed in different shapes by combining two or more square shapes. That is, the capacitor C2 has a concave shape in which two rectangles protrude from one side of one rectangle, and the capacitor C7 has a shape in which three rectangles are successively shifted in the long side direction. These capacitors C2 and C7 are grounding capacitors that require a relatively large capacitance value. When the grounding capacitors C2 and C7 are formed in such irregular shapes, the limited space on the alumina substrate 1 is effectively used, A capacitor having a desired capacitance value can be mounted at a high density.

Further, among the capacitors C1 to C7,
The capacitor C6 is composed of two grounding capacitors having different sizes, and both are connected in parallel via a pair of conductive patterns P separated from each other. That is, as shown in FIG. 2, each one electrode portion of both grounding capacitors C6 is connected to the grounding conductive pattern P connected to the GND electrode, while each other electrode portion of both grounding capacitors C6 is The transistor Tr1 is connected to the connection land SL of the transistor Tr1 via two conductive patterns P separated from each other. As is clear from FIG. 4, the capacitor C6 is provided between the emitter of the transistor Tr1 and the ground, and the connection land SL is a place where the emitter electrode of the transistor Tr1 is wire-bonded.
The capacitance value of the capacitor C6 is set by two grounding capacitors connected in parallel via the conductive patterns P separated from each other. Accordingly, the inductance of the entire conductive pattern P from the emitter electrode of the transistor Tr1 to the ground via the capacitor C6 is reduced, and the grounding effect of the connection land SL by the grounding capacitor C6 is improved. Since the parasitic oscillation frequency caused by the capacitor C6 and each conductive pattern P increases, the parasitic oscillation can be eliminated by setting this frequency to be equal to or higher than the operating point frequency of the transistor Tr1.

The resistors R1 to R3 are each formed by forming a resistive film such as TaSiO ₂ by using a thin film technique such as sputtering, and a dielectric film such as SiO ₂ is provided on the surface thereof as required. As shown in FIG. 2, three resistors R1 to R3
Among them, the resistors R1 and R2 are formed as thin films side by side at positions close to each other on the alumina substrate 1, and the remaining resistor R3 is formed as a thin film at positions away from the resistors R1 and R2.
As described above, since the resistors R1 and R2 are formed as thin films at positions close to each other, even if the resistance values of the resistors R1 and R2 vary from a desired value, the ratio of the variation of the entire resistors R1 and R2 is reduced. Can be the same. As is clear from FIG. 4, the resistors R1 and R2 are voltage dividing resistors for the base bias of the transistor Tr1, and R1 / (R1 + R2)
A voltage of × Vcc is applied to the base of the transistor Tr1. Here, a resistor R which is a voltage dividing resistor for base bias is used.
As described above, the ratio of the variation between the resistors R1 and R2 is always the same, so that it is not necessary to trim the resistance values of the resistors R1 and R2. On the other hand, the resistor R3 is an emitter resistor of the transistor Tr1, and a current flows from the Vcc electrode to the collector and the emitter of the transistor Tr1, and is further grounded through the resistor R3. Here, each of the resistors R1 to R
3, the emitter R3 has the largest contribution to the amplification of the transistor Tr1. Therefore, only the resistor R3 is trimmed to adjust the output so that the current value is constant.

The inductance elements L1 to L3 and the conductive paths S1 and S2 are made of Cr, Cu, or the like by using a thin film technique such as sputtering, and are connected to the conductive pattern P. A Cu layer is provided on the surface of each of the inductance elements L1 to L3, and the Cu layer enhances the Q of the resonance circuit. Each of the inductance elements L1 and L2 is formed in a rectangular spiral shape, and one end of each is wire-bonded to a Vctl electrode or a conductive pattern P for grounding. The inductance element L2 is for setting a resonance frequency for setting an approximate resonance frequency, and the inductance element L3 is for setting the inductance element L.
2 is continuous with the other end. The inductance element L3 is an adjustment conductive pattern for adjusting the resonance frequency,
As shown by the broken line in FIG. 2, the inductance element L3
Are increased to adjust the resonance frequency. In this case, the trimmed inductance element L3
Is the inductance element L2 for setting the resonance frequency.
, The characteristic impedances of the inductance element L2 and the inductance element L3 do not change, and oscillation with a good C / N ratio can be obtained.

As described above, the unbalanced / balanced conversion element T
Is formed by an inductance element composed of a pair of conductive paths S1 and S2 coupled to each other.
S2 is formed on the alumina substrate 1 as a thin film. These conductive paths S1 and S2 are spirally formed on the alumina substrate 1 so as to face each other with a predetermined gap therebetween. Both ends of one conductive path S1 are connected to the collector electrode of the transistor Tr1 and the capacitor C7. The other end of the other conductive path S2 is connected to a pair of RFout electrodes. In this case, since the dimensional accuracy of the conductive paths S1 and S2 formed as a thin film is high, both the conductive paths S1 and S2
A desired coupling degree can be ensured by narrowing the gap between them, and a small unbalanced / balanced conversion element T can be provided in a limited space on the alumina substrate 1.

The diode D1 and the transistor Tr
Reference numeral 1 denotes a semiconductor bare chip mounted on a connection land of a conductive pattern P formed as a thin film on an alumina substrate 1, and the semiconductor bare chip is wire-bonded to the conductive pattern P. That is, as shown in FIG. 2, the semiconductor bare chip of the diode D1 has a square shape, and one electrode provided on the lower surface thereof is fixed to the connection land using a conductive adhesive such as cream solder or conductive paste. The other electrode provided on the upper surface of the semiconductor bare chip is wire-bonded to a predetermined portion of the conductive pattern P.
The semiconductor bare chip of the transistor Tr1 also has a square shape, a collector electrode provided on the lower surface thereof is fixed to a connection land using a conductive adhesive, and a base electrode and an emitter electrode are wire-bonded to predetermined portions of the conductive pattern P. Have been. Similarly to the end face electrode 3 described above, a Ni base plating layer and an Au plating layer are sequentially laminated on these connection lands. Here, as shown in FIG. 7A or 7B, the area of the connection land 5 is formed to be smaller than the lower area of the semiconductor bare chip 4, and by adopting such a configuration, the semiconductor bare chip 4
, A reservoir of the conductive adhesive is secured below the semiconductor chip 4, so that an accident that the conductive adhesive protrudes from the outer shape of the semiconductor bare chip 4 and short-circuits with the surrounding conductive pattern P can be prevented beforehand. Further, an opening 5a is provided in the connection land 5, and since an excess of the conductive adhesive is accumulated in the opening 5a, it is possible to more reliably prevent the conductive adhesive from protruding. .

Next, the manufacturing process of the electronic circuit unit configured as described above will be described mainly with reference to FIGS.

First, a large plate substrate 1A made of an alumina material having division grooves extending vertically and horizontally in a grid pattern is prepared.
As shown in (a), the entire surface of the large substrate 1A is covered with Ta.
After sputtering of SiO ₂ or the like, this is etched into a desired shape to form the resistance film 6, thereby forming the resistances R 1 to R 1.
A part corresponding to R3 is configured. Next, as shown in FIG. 8B, Cr or Cu or the like is sputtered from above the resistive film 6, and is etched into a desired shape to form the lower electrode 7, and as shown in FIG. Then, SiO ₂ or the like is sputtered from above the lower electrode 7 and etched into a desired shape to form a dielectric film 8. Next, as shown in FIG. 8D, after sputtering Cr, Cu, or the like from above the dielectric film 8, this is etched into a desired shape to form the upper electrode 9. As a result, the conductive pattern P and the inductance element L1 are formed by the lower electrode 7 or the upper electrode 9.
L3 and the portions corresponding to the conductive paths S1 and S2 are formed, and the laminated body of the lower electrode 7, the dielectric film 8 and the upper electrode 9 forms the portions corresponding to the capacitors C1 to C7. Next, after a Cu layer is formed on the surfaces of the portions corresponding to the inductance elements L1 to L3, the capacitors C1 to C7, and the conductive paths S1 and S2 by plating or thin film technology, as shown in FIG. The protective film 10 is formed in a portion excluding P. Next, as shown in FIG.
After sputtering Cr, Cu, or the like on the entire back surface of the large plate substrate 1A, this is etched into a desired shape to form a back electrode 1
By forming No. 1, a portion corresponding to the conductive pattern P1 on the back surface side is formed.

The steps of FIGS. 8A to 8F described above are performed on the large-size substrate 1A.
Steps (g) to (j) are performed by cutting the large substrate 1A along the one-way dividing groove.
Is performed on

That is, after dividing the large-sized substrate 1A into a plurality of strip-shaped substrates 1B, as shown in FIG. 8 (g), Ag layers are formed on both end surfaces of the alumina substrate 1 which is a divided surface of the strip-shaped substrate 1B. 12 is formed as a thick film, and the grounding electrodes (GN) of the conductive patterns P and P1 provided on the front and back surfaces of the alumina substrate 1 are formed.
D), the input electrode (Vcc, Vctl, RFin) and the output electrode (RFout) are electrically connected through the Ag layer 12. The Ag layer 12 corresponds to the Ag thick film layer of the end face electrode 3 described above, and is a low-temperature fired material made of an Ag paste containing no glass component. Note that the thick film forming step of the Ag layer 12 can be performed on one strip-shaped substrate 1B. However, if a plurality of strip-shaped substrates 1B are overlapped with a slight gap therebetween, , Ag layer 12 and a plurality of strip-shaped substrates 1
B can be simultaneously formed into a thick film, which is suitable for mass production. Next, after a Ni underlayer and an Au layer are sequentially plated on each surface of the connection land on which the Ag layer 12 and the semiconductor bare chip are mounted, as shown in FIG. 8H, a diode D1 and a transistor are provided on each connection land. The semiconductor bare chip of Tr1 is fixed using a conductive adhesive such as cream solder or conductive paste. In this case, as described above, since the area of the connection land is formed smaller than the lower area of the semiconductor bare chip, the conductive adhesive is prevented from protruding from the semiconductor bare chip, and the conductive adhesive is applied to the semiconductor bare chip. Undesired short circuit with the surrounding conductive pattern P is prevented. Next, as shown in FIG. 8 (i), after each semiconductor bare chip is wire-bonded to a predetermined portion of the conductive pattern P, as shown in FIG. 8 (j), a resistor R3 which is an emitter resistor is trimmed and output. At the same time, the resonance frequency is adjusted by trimming the inductance element L3, which is an adjustment conductive pattern. In this case, the adjustment of the resonance frequency is performed in the state of the strip-shaped substrate 1B before being divided into the individual alumina substrates 1, and since the grounding electrode (GND) is provided at the corner of each alumina substrate 1, Electrodes (Vcc, Vctl, RFin) and output electrodes (RFout) provided on the alumina substrate 1
The ground electrode (GND) is always located between them,
Adjustment of the resonance frequency does not adversely affect the circuit of the adjacent alumina substrate 1.

After all the necessary circuit components and end face electrodes 3 are formed on the strip-shaped substrate 1B in this manner, FIG.
As shown in (a), the cover continuous body 2A is attached to the strip-shaped substrate 1B by sliding the cover continuous body 2A in the arrow direction with respect to the strip-shaped substrate 1B. The cover continuous body 2A is formed by bending a metal plate into a U-shaped cross section, and a plurality of leg pieces 2a are formed at bent portions on both sides in the longitudinal direction. In the cover continuous body 2A, a plurality of connecting portions 2b are formed at predetermined intervals in the longitudinal direction, and cutouts 2c extending in the lateral direction are formed on both sides of each connecting portion 2b. Further, one end of the continuous cover 2A in the longitudinal direction is an insertion guide 2d, and the insertion guide 2d is formed to be somewhat wider than the width W of the strip-shaped substrate 1B in the short direction. Therefore, when the cover continuous body 2A is slid and inserted into the strip-shaped substrate 1B from the insertion guide 2d side, the cover continuous body 2A
Can be smoothly inserted into the strip-shaped substrate 1B, and deformation of the leg 2a can be prevented.

After the continuous cover 2A is attached to the strip-shaped substrate 1B as described above, the leg piece 2a of the continuous cover 2A is connected to the end face electrode 3 which is electrically connected to the ground electrode (GND) of the strip-shaped substrate 1B. Solder using. After a while
As shown in FIG. 9 (b), the cover continuous body 2A and the strip-shaped substrate 1B are cut in a direction indicated by a two-dot chain line in FIG. The substrate 1B is divided into a plurality of alumina substrates 1, and the cover continuous body 2A is divided into a plurality of covers 2, thereby obtaining a completed electronic circuit unit in which the cover 2 is attached to each alumina substrate 1. 1). In this case, since the cover continuous body 2A is cut along the cuts 2c, only the connecting portion 2b needs to be cut, and the cover continuous body 2A and the strip-shaped substrate 1B can be easily and collectively cut. It should be noted that the entire length of the continuous cover 2A is set to be slightly longer than the rectangular substrate 1B, and only the insertion guide 2d is moved from the rectangular substrate 1B while the continuous cover 2A is attached to the rectangular substrate 1B. If it is made to protrude, the insertion guide 2d can be discarded by cutting.

According to the electronic circuit unit according to the above embodiment, circuit elements such as capacitors C1 to C7, resistors R1 to R3, inductance elements L1 to L3, conductive paths S1 and S2, and these circuit elements are formed on the alumina substrate 1. And a semiconductor bare chip of a transistor Tr1 are wire-bonded on the alumina substrate 1 and a grounding electrode of the conductive pattern and an input terminal are formed on the side surface of the alumina substrate 1. Since the end face electrode 3 connected to the electrode and the output electrode is provided, required circuit components can be mounted on the alumina substrate 1 at a high density by using thin film technology and wire bonding of a semiconductor element, thereby reducing the size. A suitable surface-mount type electronic circuit unit can be realized. Further, after combining and integrating the strip-shaped substrate 1B and the cover continuous body 2A, the both are cut by laser, dicing, or the like, so as to be divided into a plurality of alumina substrates 1 and the cover 2. A plurality of completed electronic circuit units to which is attached can be obtained at the same time, and mass productivity can be improved. Furthermore, when combining the strip-shaped substrate 1B and the cover continuous body 2A, the cover continuous body 2A is slid in the longitudinal direction with respect to the strip-shaped substrate 1B, so that the strip-shaped substrate 1B
Is inserted, the leg piece 2 of the cover continuum 2A is inserted.
a can be prevented, and the insertion guide 2d wider than the width of the strip-shaped substrate 1B is formed at the insertion end of the cover continuum 2A.
Can be smoothly inserted into the strip-shaped substrate 1B.
Furthermore, since the cut 2c extending in the lateral direction is formed in the cover continuum 2A, leaving the connecting portion 2b, the cut portion of the cover continuum 2A is only the connecting portion 2b, and the cover continuum 2A and the strip shape are formed. The substrate 1B can be easily cut at once.

In the above-described embodiment, the case where the continuous cover 2A is slid in the longitudinal direction with respect to the strip-shaped substrate 1B has been described.
B may be slid in the longitudinal direction with respect to the cover continuum 2A. Further, the continuous cover 2A and the strip-shaped substrate 1B do not need to be cut at once by the same means. For example, after cutting the continuous cover 2A with a laser, the strip-shaped substrate 1B may be cut by dicing. . Alternatively, instead of forming the insertion guide 2d in the cover continuous body 2A, both sides of the insertion end of the strip-shaped substrate 1B may be chamfered in a tapered shape, and the chamfered portion may function as an insertion guide.

[0031]

The present invention is embodied in the form described above and has the following effects.

Circuit elements including capacitors, resistors and inductance elements are formed with high precision using thin film technology, and the semiconductor elements are formed by wire bonding of bare chips, so that circuit components required on an alumina substrate are required. It is possible to realize an electronic circuit unit suitable for miniaturization, which is mounted at high density, and furthermore, after a completed product of such an electronic circuit unit is integrated by combining a strip-shaped substrate and a cover continuous body, Since both are obtained by cutting each into an alumina substrate and a cover, mass productivity can be improved.

[Brief description of the drawings]

FIG. 1 is a perspective view of an electronic circuit unit according to an embodiment of the present invention.

FIG. 2 is a plan view of an alumina substrate showing a circuit configuration layout.

FIG. 3 is a rear view of the alumina substrate.

FIG. 4 is an explanatory diagram of a circuit configuration.

FIG. 5 is a perspective view showing an end face electrode.

FIG. 6 is a sectional view of an end face electrode.

FIG. 7 is an explanatory diagram showing a relationship between a semiconductor bare chip and connection lands.

FIG. 8 is an explanatory view showing a manufacturing process until a strip-shaped substrate is obtained.

FIG. 9 is an explanatory diagram showing a manufacturing process until a completed electronic circuit unit is obtained from a strip-shaped substrate and a continuous cover.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Alumina substrate 1A Large plate 1B Strip-shaped substrate 2 Cover 2A Cover continuous body 2a Leg piece 2b Connecting part 2c Cut 2d Insertion guide 3 End face electrode 4 Semiconductor bare chip 5 Connection land 6 Resistive film 7 Lower electrode 8 Dielectric film 9 Upper electrode DESCRIPTION OF SYMBOLS 10 Protective film 11 Back electrode 12 Ag layer 13 Laser processing machine C1-C7 Capacitor R1-R3 Resistance L1-L3 Inductance element Tr1 Transistor S1, S2 Conduction path P, P1 Conduction pattern

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 25/00 H01L 23/12

Claims (4)

(57) [Claims] 1. After forming a thin film of a circuit element including a capacitor, a resistor, and an inductance element on a large substrate made of an alumina material and wire bonding a semiconductor bare chip, the large substrate is divided into a plurality of strip-shaped substrates. Performing a step of providing end electrodes on both side surfaces along the longitudinal direction of the strip-shaped substrate; and applying a cover continuous body obtained by bending a metal plate to a U-shaped cross section on the strip-shaped substrate. Soldering the leg pieces bent on both sides in the longitudinal direction of the continuum to the end surface electrode; and arranging the cover continuum and the strip-shaped substrate after soldering into a plurality at predetermined intervals in the longitudinal direction. Cutting and obtaining a finished product with a cover attached to each alumina substrate,
A method for manufacturing an electronic circuit unit, comprising: 2. The strip-shaped substrate according to claim 1, wherein the strip-shaped substrate is inserted between legs of the cover-continuous body by sliding the cover-continuous body and the strip-shaped substrate relatively in the longitudinal direction. A method for manufacturing an electronic circuit unit, comprising: 3. The electronic device according to claim 2, wherein an insertion guide wider than a width of the strip-shaped substrate along a width direction is provided at an end in a longitudinal direction of the cover continuum. A method for manufacturing a circuit unit. 4. The cover continuum according to any one of claims 1 to 3, wherein a cut is formed in the cover continuum, extending in the lateral direction while leaving a connection portion, and the connection portion is cut. A method for manufacturing an electronic circuit unit, comprising: obtaining the cover from a substrate.