JP3244845B2 - Control method of PWM inverter and control device using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage type PWM for driving an induction motor or a synchronous motor of an electric vehicle, for example.
The present invention relates to a PWM inverter control method for controlling a switching operation of a variable voltage variable frequency inverter and a control device using the same.

[0002]

2. Description of the Related Art Conventionally, a gate signal applied to a switching element for controlling a switching operation of a voltage-type PWM inverter for driving an induction motor of an electric vehicle is switched from one pulse to three pulses, or from three pulses to one pulse. The control method for switching to is as shown in FIG. 7 and FIG. That is, the gate signal obtained by comparing the modulated sine wave A and the carrier triangular wave B as shown in FIG.
As shown in FIG. 7, when the angle reaches an integral multiple of 60 °, the U, V, and W phases are simultaneously switched. However, in FIG. 8, the angle α and the modulation rate AL (= peak value of modulated wave A /
The following relationship exists between the peak values of the carrier B).

[0003]

Α = 60 · (1−AL) (deg) (1) The waveform diagram in FIG. 7 is a waveform when switching from three pulses to one pulse is performed at an electrical angle of 60 °. is there.

However, when such a conventional modulation method and switching method are used, a waveform (a shaded portion) in the middle of switching for one cycle including 180 ° before and after the switching angle is three times. Compared with the pulse waveform and the one-pulse waveform, the U, V, and W phases have different voltage areas.

The U phase in this section is divided into three pulses,
When the pulse and the waveform in the middle of switching are expanded into a Fourier series, the fundamental wave component is expressed by the following equations (2) to (4).

(Equation 2) However, here, the ON voltage of the gate signal is E volt,
The off voltage is -E volts.

From equation (4), it can be seen that the waveform during switching includes a DC component. This is the same in the case of switching from one pulse to three pulses.

Therefore, a new modulation method using a modulated square wave C and an inverted trapezoidal wave D as shown in FIG. 9 has been proposed and is currently used. However, the relationship between the angle α and the modulation factor AL in FIG. 9 is the same as in the expression (1).

However, even if a gate signal according to the new modulation method is used, the same problem still remains in a method in which the U, V, and W phases are simultaneously switched at an integral multiple of 60 °.
That is, as shown in FIG. 10, when switching is performed at 60 °,
Comparing one cycle including 180 ° before and after the switching point, the U-phase and the V-phase have the same voltage area before and after the switching, and the V-phase has a different voltage area. That is, when the above waveform is expanded into a Fourier series in the same manner as described above, the fundamental wave components for the U phase (the same applies to the W phase) and the V phase are expressed by the following equations (5) to (7), respectively. Equations (8) to (10) are obtained.

[0009]

(Equation 3) Here, however, the on voltage of the gate signal is set to E volts, and the off voltage is set to −E volts.

From this, the waveform during the switching between the U-phase and the W-phase does not include a DC component, and there is no phase shift compared to before and after the switching, but in the V-phase, the waveform during the switching includes the DC component. It can be seen that a phase shift has occurred compared to before and after the switching.

Although FIG. 10 illustrates switching at 60 °, in all cases where switching is performed at an angle that is an integral multiple of 60 °, any one of the phases includes a DC component in the voltage being switched as described above, and a phase shift occurs. Happens. The same applies when switching from one pulse to three pulses.

As described above, in the conventional PWM inverter control method, the DC component is included in the output voltage when the gate signal is switched from one pulse to three pulses or from three pulses to one pulse in the synchronous mode. However, there is a problem that the positive and negative voltages become unbalanced, which causes the main transformer to be demagnetized and generates an overcurrent. In some cases, the output voltage may cause a phase shift.

Conventionally, as a control method of a voltage-type PWM variable voltage variable frequency inverter for driving an induction motor or a synchronous motor of an electric vehicle, a gate signal applied to a switching element of the inverter is controlled by a synchronous mode of three pulses and an asynchronous mode. There is also known a method of switching between and.

In the control method for switching between the synchronous mode and the asynchronous mode of the gate signal applied to the switching element of the PWM inverter, the switching between the synchronous mode and the asynchronous mode is performed simultaneously in the three phases U, V and W by an electrical angle of 60 °.
(= Π / 3). FIG. 11 shows a gate signal waveform of a typical example. In FIG. 11, the waveform of the gate signal in the synchronous mode of each phase is the waveform of the three-pulse mode shown in FIG. 9 described above, and the waveform of the gate signal in the asynchronous mode of each phase is FIG.
2 is generated by the PWM shown in FIG. That is, as shown in FIG. 12A, the carrier B 'has a frequency of 1 kHz, the modulation wave A' has a frequency of 90 Hz, the minimum arc extinguishing period of the inverter is 50 μs, and the modulation factor AL is 90%.
When the carrier wave B ′ is modulated by the modulated wave A ′,
By performing M, a gate signal in the asynchronous mode as shown in FIG.

Therefore, when the waveform of the gate signal is f (x) and this f (x) is expanded into a Fourier series, the constant term, that is, the DC term Bo is expressed by the following equation (11).

[0016]

(Equation 4) This equation (11) indicates that it is equal to the area of the waveform f (x) divided by the period. That is, Bo
Is equal to the average height over one cycle of the waveform f (x). Therefore, the carrier wave B 'and the modulated wave A' are
In the case of the positional relationship as shown in (a), the coordinates of the intersection of the carrier wave and the modulated wave are obtained using Newton's method, and the angles θ1 to θ of the respective pulses of the gate signal waveform shown in FIG.
When 18 is obtained, the respective values are as follows.

[0017]

Θ1 = 0.33 (rad) θ2 = 0.18 θ3 = 0.45 θ4 = 0.07 θ5 = 1.08 θ6 = 0.07 θ7 = 0.45 θ8 = 0.18 θ9 = 0 .33 θ10 = 0.33 θ11 = 0.18 θ12 = 0.45 θ13 = 0.07 θ14 = 1.08 θ15 = 0.07 θ16 = 0.45 θ17 = 0.18 θ18 = 0.33 FIG. In the waveform of the gate signal in the synchronous mode shown in FIG. 9, the relationship between the modulation factor AL and the angle α is as shown in Expression (1). When this is expressed in radians (rad),

(Equation 6) Becomes Since the modulation rate AL is assumed to be 90%, α = 0.1 (rad).

Therefore, using these values, the DC component Bo of each waveform in FIG.
(1), the following is obtained.

[0019]

## EQU00007 ## U-phase asynchronous waveform: BUa ≒ 0 Synchronous waveform: BUs = 0 Asynchronous-synchronous switching waveform: BUas ≒ 0 V-phase asynchronous waveform: BVa ≒ 0 Synchronous waveform: BVs = 0 Asynchronous-synchronous switching waveform: BVas ≒- 0.55 W phase Asynchronous waveform: BWaa0 Synchronous waveform: BWs = 0 Asynchronous-synchronous switching waveform: BWas ≒ 0 From the above calculation results, it can be seen that a negative DC component is superimposed on the V phase in this case. . When the U, V, and W phases are simultaneously switched at an electrical angle that is an integral multiple of 60 ° (= π / 3), the polarity of the gate signal of any one phase becomes unbalanced, and this is the bias of the main transformer. There was a problem that caused magnetism.

[0020]

As described above, the conventional P
In the control method of the WM inverter, a gate signal to be given to a switching element of the inverter is one pulse in a synchronous mode,
When switching between the three-pulse mode and when switching between the synchronous mode and the asynchronous mode, all phases are switched at the same time at a certain electrical angle, so that the output voltage includes a DC component and the positive and negative voltages become unbalanced. However, there has been a problem that the main transformer is demagnetized to generate an overcurrent, and a phenomenon that the output voltage causes a phase shift sometimes occurs.

The present invention has been made in view of the above-mentioned conventional problems. When switching from three pulses to one pulse, or when switching from one pulse to three pulses, a DC component is added to the fundamental wave component of the gate signal. It is an object of the present invention to provide a PWM inverter control method capable of switching so as not to cause a phase shift and a control device using the same.

Another object of the present invention is to provide a PWM inverter control method and a control apparatus using the same, which can switch the gate signal so as not to include a DC component when switching between the synchronous mode and the asynchronous mode. Aim.

[0023]

A PWM according to the first aspect of the present invention.
The inverter control method includes a modulation method for comparing a modulated square wave and a carrier inverted trapezoidal wave in a synchronous mode in which the number of pulses in a half cycle is constant when generating a gate signal for controlling a switching operation of a PWM inverter, or The switching from three pulses to one pulse or the switching from one pulse to three pulses is performed for each of the U, V, and W phases using a modulation method that generates a voltage pattern equivalent to the signal obtained by the pulse and the frequency command. This is performed individually at a timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached.

According to a second aspect of the present invention, a PWM inverter control device includes a three-pulse gate signal generation circuit, a one-pulse gate signal generation circuit, and a gate signal from these gate signal generation circuits. By the AND logic of the switching common command and the individual switching command pulse signals of the U, V, and W phases, the one-pulse gate signal and the three-pulse gate signal reach the maximum value or the minimum value of the fundamental wave component of each phase. U, V, which are mutually switched at the timing and output
And an output gate signal switching circuit for each W phase.

According to a third aspect of the present invention, there is provided a PWM inverter control method for controlling a switching operation by switching a gate signal for controlling a switching operation of a PWM inverter between a synchronous mode and an asynchronous mode. W
Synchronous mode gate signal and asynchronous mode gate signal at the timing when the maximum value or minimum value of each fundamental wave component is reached for each phase of U, V, W individually after inputting the synchronous mode and asynchronous mode switching command common to each phase Are mutually switched.

According to a fourth aspect of the present invention, there is provided the PWM inverter control method according to the third aspect, wherein the on-pulse of the PWM inverter that is shorter than the minimum arc extinguishing period is turned off and the off-pulse that is shorter than the minimum arc extinguishing period is turned on. The mode switching is executed at a timing when a modulation rate exceeding a predetermined value is reached near the mode switching point.

According to a fifth aspect of the present invention, there is provided a PWM inverter control device, comprising: a gate signal switching signal in a synchronous mode and an asynchronous mode; and an AND logic of a switching signal at a switching angle for each of U, V, and W phases. A switching signal generation circuit for each of U, V, and W phases that outputs a switching signal of a synchronous mode and an asynchronous mode at a timing when the maximum value or the minimum value of the fundamental wave component is reached, and a synchronous gate signal and an asynchronous gate signal for each phase U, when a switching signal is inputted from the switching signal generating circuit for each phase, a synchronous gate signal or an asynchronous gate signal is switched to a new asynchronous gate signal or a synchronous gate signal and outputted.
And an output gate signal switching circuit for each of the V and W phases.

[0028]

According to the PWM inverter control method of the present invention, the gate signals of the U, V, and W phases are not switched between one pulse and three pulses at a uniform switching angle.
By switching at each point where the voltage area is equal, the DC component is not included in the fundamental wave component of the output voltage, and the phase shift is achieved by switching at the point of the maximum or minimum value of the fundamental wave of the same gate signal. Generate no gate signal,
Thereby, the gate control of the PWM inverter can be performed.

In the control device for a PWM inverter according to a second aspect of the present invention, the output gate signal switching circuit for each of the U, V, and W phases outputs the gate signal from each of the pulse gate signal generation circuit and the one-pulse gate signal generation circuit. The one-pulse gate signal and the three-pulse gate signal are mutually switched and output according to the AND logic of the common command of the one-pulse / 3-pulse switching and the individual switching command pulse signal of each of U, V and W phases. Thus, the U, V, and W phases can be individually performed at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached.

According to the PWM inverter control method of the present invention, when the gate signal for controlling the switching operation of the PWM inverter is switched between the synchronous mode and the asynchronous mode, the synchronous mode common to the U, V, and W phases can be used. After the asynchronous mode switching command is input, the DC component is switched by switching between synchronous mode and asynchronous mode at the timing when the maximum value or the minimum value of each fundamental wave component is individually reached for each phase of U, V, and W. A gate signal that does not include and does not have a phase shift is generated, whereby gate control of the PWM inverter can be performed.

In the method of controlling a PWM inverter according to the fourth aspect of the present invention, a correction is made such that an ON pulse of the PWM inverter that is shorter than a minimum arc extinguishing period is turned off and an off pulse that is shorter than the minimum arc extinguishing period is turned on. By executing the mode switching at the timing when the modulation rate exceeds the predetermined value, the command value near the center of the half cycle of the gate signal of each phase can be set to the minimum value or the maximum value, and the DC component can be surely obtained. And a gate signal having no phase shift can be generated to control the gate of the PWM inverter.

In the control device for a PWM inverter according to a fifth aspect of the present invention, the output gate signal switching circuit for each of the U, V, and W phases comprises a gate signal synchronous mode / asynchronous mode switching signal and an individual phase switching angle. Of the switching signal at
When a synchronous mode / asynchronous mode switching signal is fetched from a switching signal generating circuit for each phase of U, V, W which outputs a synchronous mode / asynchronous mode switching signal by D logic, the synchronous gate signal or asynchronous signal before that is taken. By switching from a gate signal to a new asynchronous gate signal or a synchronous gate signal and outputting the same, the synchronous mode and the asynchronous mode are performed at the timing when the maximum value or the minimum value of each fundamental wave component is individually reached for each of U, V, and W phases. Switching between the gate signals can be performed.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1 and 2 show a circuit of an embodiment of the PWM inverter control device according to the second aspect of the present invention, which uses the PWM inverter control method according to the first aspect. In the circuit diagrams of FIGS. 1 and 2, the voltage and the frequency are adjusted so that an output signal equivalent to that obtained by the modulation method of comparing the modulated square wave C and the carrier inverted trapezoidal wave D as shown in FIG. 9 is obtained. P that generates a gate signal pattern in response to a command
Of all the digital circuits of the control device of the WM inverter,
In particular, a circuit configuration of a portion for switching the number of pulses is shown.

In this control device, 1 and 2 are data buses, 3 is a latch for storing one pulse width data,
Reference numeral 4 denotes a latch for storing the pulse width of three pulses, and reference numerals 5 and 6 denote data buses for transmitting the data of these latches. W-phase switching circuits 7u, 7
v, 7w. Each of these switching circuits 7u, 7v, 7w switches data at the timing of the switching angle of each phase, and has the circuit configuration of FIG. 2 as described later.

Timing signals 8u, 8v, 8w for giving a switching trigger to each of the switching circuits 7u, 7v, 7w are inputted, and a 1-pulse / 3-pulse switching command signal 9 is commonly inputted. It has become. Therefore, when the 1-pulse / 3-pulse switching command signal 9 is input to each of the switching circuits 7u, 7v, and 7w, the U-phase timing signal 8u becomes 30 ° or 21 °.
At 0 °, the V-phase timing signal 8v is -30 ° or 1
50 °, and the W-phase timing signal 8w is 270 °
Alternatively, the pulse width is switched by triggering each at 90 °, and then the pulse width is counted, and the U-phase,
It outputs rising or falling detection signals 10u, 10v, and 10w of the V-phase and W-phase gate signals.

The switching circuits 7u, 7v and 7w have the same configuration as shown in FIG.
2 (corresponding to data buses 5 and 6 in FIG. 1), each phase switching angle timing signal 73 (signal 8u,
A 1-pulse / 3-pulse switching command signal 74 (corresponding to the signal 9 in FIG. 1) is input and a 1-pulse pulse width data register 75 and a 3-pulse pulse width data register 76 are input. , Internal data bus 7
7, 78, a multiplexer 79, a data bus 710, and a down counter 711. The down counter 711 detects a rise or fall of a gate signal of each phase from a signal 712 (output signals 10u, 10 in FIG. 1).
v, 10w) is output.

Next, a method of controlling the PWM inverter by the PWM inverter control device having the above configuration will be described.

The pulse width data of one pulse sent from the data bus 1 is stored in the latch 3, the pulse width data of three pulses sent from the data bus 2 is stored in the latch 4, and these are stored in the data bus 5. , 6 to the switching circuits 7u, 7v, 7w for each phase. Switching circuit 7 for each phase
u, 7v, and 7w include a 1-pulse / 3-pulse switching command signal 9 and a switching timing signal 8u (30 ° or 210, which is the maximum or minimum angle of the U-phase fundamental wave).
°), 8v (-30 ° or 1 which is the same angle of V phase)
50 °) and 8w (similar angles of the W phase, 90 ° or 270 °).

The operation of each of the switching circuits 7u, 7v and 7w will be described with reference to FIG. 2. One pulse width data is loaded into the register 75 via the data bus 71 by each phase switching timing signal 73. ,
The register 76 is loaded with pulse width data of three pulses via the data bus 72.

The pulse width data loaded into these registers 75 and 76 is sent to a multiplexer 79 through data buses 77 and 78, and any one of the data is transferred to the data bus in response to a 1-pulse / 3-pulse switching command signal 74. The data is loaded into the down counter 711 via 710.

The down counter 711 counts down the pulse width data to be loaded, and outputs a borrow signal 712 when the count value becomes zero. This signal 712 is a signal for detecting the rise or fall of the gate signal of each phase of U, V, and W in FIG. 1 (when switching occurs at the maximum value of the fundamental wave component of the gate signal, the fall of the pulse is detected. Signal, when the switching occurs at the minimum value, a pulse rising detection signal) 10u, 10v, 10
w.

In the one-pulse / 3-pulse switching process performed by using the PWM inverter control device, as shown in FIG. 4, the U-phase, V-phase and W-phase are respectively at 30 ° and -30 °.
The angle is switched from 3 pulses to 1 pulse with a switching angle of 90 ° and 90 °, and a portion in the middle of the switching of one cycle including the 180 ° before and after each switching angle at this time (shaded portion) is 3 pulses Comparing the three waveforms, the waveform, the pulse waveform, and the waveform switched in the middle, shows that the voltage areas are all equal.

This will be described taking the U phase as an example.
When one cycle of these three types of waveforms is expanded into a Fourier series, the fundamental wave components are all (5) to (7).
The formula is the same as that of the above, and it can be seen that the DC component is not included in the fundamental wave component of the output voltage in any waveform during switching, before switching, and after switching, and that there is no phase shift.

In the above embodiment, the method of switching from three pulses to one pulse has been described. However, the same applies to the case of switching from three pulses to one pulse.

An embodiment of the control method of the PWM inverter according to the third and fourth aspects of the present invention will be described. FIG. 5 shows the gate signal waveform in the asynchronous mode, the gate signal waveform in the synchronous mode, and the gate signal waveform during the asynchronous-synchronous switching of the U, V, and W phases according to the embodiment of the present invention. As shown in FIG. 12A, the asynchronous waveform of each phase is as follows.
In this embodiment, the waveform shown in FIG. 2B is obtained as a result of performing PWM on a carrier wave B 'of 1 kHz by a modulated wave A' of 90 Hz. Further, in this case, the off pulse γ of about 50 μs or less, which is the minimum arc extinguishing period of the PWM inverter,
1 and the on-pulse γ2 which is shorter than the minimum arc extinguishing period.
Is corrected so that the command value near the center of the half cycle of the fundamental wave becomes the maximum value or the minimum value.

As shown in FIG. 9, the synchronous waveform is obtained by performing PWM on the square carrier C using the inverted trapezoidal modulated wave D.

Therefore, in this embodiment, the asynchronous mode-synchronous mode switching command for all phases U, V, and W is
(Rad), whereas in the U phase, the actual switching is performed at an angle π / 6 (rad) (in this case, the minimum value) as the timing at which the fundamental wave takes the maximum value or the minimum value. Is done. In the V phase, an angle of 5π / 6 (rad) is used as a timing at which the maximum value or the minimum value of the fundamental wave is obtained.
) (In this case, the minimum value is taken), the actual switching is performed, and in the W phase, the actual switching is carried out at the angle π (rad) (in this case, the maximum value is taken).

When the switching timing of the gate signal between the asynchronous mode and the synchronous mode is set in this way,
The switching waveform does not include a DC component, and does not include a DC component that causes the main transformer to be demagnetized. The reason is as follows. When the gate waveform is symmetric according to the above equation (11), that is, when the area of the negative half-wave is equal to the area of the positive half-wave, the average area is also equal to 0, and the constant The term, and therefore the DC component, is also zero. Since the gate waveform is a square wave, from this equation (11), if the total of the on-pulse angle and the total of the off-pulse angle of the gate waveform in one cycle are equal, and if each is π radian, the DC component is not included. Become.

In the case of the above embodiment, the left and right areas are equal because they are symmetrical about the maximum or minimum value of the fundamental wave of each phase of U, V and W. And asynchronous mode,
Since no DC component is included in any of the gate waveforms in the synchronous mode, no DC component is included in the switching waveform. Therefore, the switching waveform does not cause a magnetic bias in the main transformer circuit of the PWM inverter for which the switching control is performed.

Further, the maximum value or the minimum value of the fundamental wave of each phase is near the center of the half-wave, where the on-pulse γ2 or the off-pulse γ1 for a very short time appears, but about 50 μs or less of the minimum extinction time of the inverter. By turning off the on-pulse or off-pulse, the command value near the center of the half cycle can be set to the maximum value or the minimum value.

FIG. 6 is a circuit block diagram of one embodiment of the control device according to the fifth aspect of the present invention which uses the PWM inverter control method of the above embodiment. In this control device, a mode switching signal 11 commonly applied to each phase is used as a D input, and a mode switching signal 12u, 1
2v, 12w are provided as clock inputs, and flip-flop circuits 13u, 13v, 13w are provided which output an "H" signal by both inputs. The outputs of the flip-flop circuits 13u, 13v, 13w are S inputs, the synchronous mode gate signals 14u, 14v, 14w for each phase shown in FIG. 5 are A inputs, and the asynchronous mode gate signals for each phase. 15u, 15v, 15w
Is a B input, and every time an “H” signal is input to the S input, A
The input and B inputs are switched to each other, and the gate signals 16u, 16
multiplexers 17u and 17 for outputting as v and 16w
v, 17w.

In the control device for a PWM inverter having the above configuration, each of the flip-flop circuits 13u, 13v, 13
Asynchronous-synchronous mode switching signal is input to electrical angle 0 common to w. Pulse waveforms 12u, 12v, and 12w that are turned on at the maximum value or the minimum value of the fundamental wave component for each phase.
Is provided as a clock input. And in this case, U
The phase waveform 12u is π / 6 (= 30 °) or 7π / 6
(= 210 °), the V-phase waveform 12v is 5π / 6 (= 15
0 °) or 11π / 6 (= 330 °), W-phase waveform 1
2w is 3π / 2 (= 270 °) or π / 2 (= 90 °).
°) respectively.

Then, the common mode switching signal 11 is input, and the flip-flop circuits 13u, 13v, 13
If the pulse waveforms 12u, 12v, and 12w are input for each w, the "H" signal is output from each of the flip-flop circuits 13u, 13v, and 13w at the timing of the maximum value or the minimum value of each of the multiplexers 17u, 17v, and 17w.
17w is provided to each S input.

As a result, each of the multiplexers 17u, 17
v, 17w, the above timing, that is, as shown in FIG. 5, in the U phase, π / 6 (= 30 °) or 7π / 6
(= 210 °), 5π / 6 (= 150 °) or 11π / 6 (= 330 °) in the V phase, and 3π / 2 (= 2
The gate signals 16u, 16v, and 16w whose asynchronous-synchronous modes have been switched at 70 °) or π / 2 (= 90 °) are output. The gate signal of each of these phases does not include a DC component, and does not include a DC component that causes the main transformer to be polarized.

[0055]

As described above, according to the first aspect of the present invention,
Using a modulation method that compares a modulated square wave with a carrier inverted trapezoidal wave, or a modulation method that generates a voltage pattern equivalent to a signal obtained by a voltage and frequency command,
Switching from pulse to 1 pulse or from 1 pulse to 3
The switching to the pulse is performed at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is individually reached for each of the U, V, and W phases.
During switching, there is no change in the voltage area after switching, the DC component is not included in the fundamental wave component of the gate signal, and switching can be performed without causing a phase shift, and the positive and negative voltages become unbalanced as in the past, which is the main transformer. The phenomenon that overcurrent is generated by causing the magnetism of the device is prevented, and stable gate control can be performed.

According to the second aspect of the present invention, the output gate signal switching circuit for each of the U, V, and W phases takes in the gate signals from the pulse gate signal generation circuit and the one-pulse gate signal generation circuit, and outputs one pulse. Since the one-pulse gate signal and the three-pulse gate signal are mutually switched and output by the AND logic of the common command of the / 3 pulse switching and the individual switching command pulse signals of the U, V, and W phases, The U, V, and W phases can be performed individually at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached. The DC component is not included in the fundamental wave component of the gate signal.
Switching without causing a phase shift can be performed.

According to the third aspect of the invention, when the gate signal for controlling the switching operation of the PWM inverter is switched between the synchronous mode and the asynchronous mode, switching between the synchronous mode and the asynchronous mode common to the U, V, and W phases is performed. After the input of the command, the synchronous mode and the asynchronous mode are switched at the timing when the maximum value or the minimum value of each fundamental wave component is individually reached for each phase of U, V, and W. Therefore, even if the mode of the gate signal is switched, A gate signal that does not include a DC component can be generated, and the positive and negative voltages become unbalanced as in the past, which prevents the phenomenon that the main transformer is demagnetized and an overcurrent is generated, and a stable gate is prevented. Can control.

According to the fourth aspect of the present invention, the on-pulse of the PWM inverter that is shorter than the minimum arc extinguishing period is turned off and the off-pulse that is shorter than the minimum arc extinguishing period is turned on, and a predetermined value is set near the mode switching point. Mode switching is performed when the modulation rate exceeds the maximum, so that the command value near the center of the half cycle of the gate signal of each phase can be set to the minimum or maximum value, and even if the mode of the gate signal is switched, A gate signal that does not include a DC component can be generated, and the conventional phenomenon of causing an overcurrent by causing the main transformer to be deflected can be reliably prevented.

According to the fifth aspect of the present invention, the output gate signal switching circuit for each of the U, V, and W phases is used to switch the synchronous mode and the asynchronous mode of the gate signal and the switching signal at the individual switching angle of each phase. When a synchronous mode / asynchronous mode switching signal is fetched from a switching signal generating circuit for each phase of U, V, and W which outputs a synchronous mode / asynchronous mode switching signal by AND logic, a synchronous gate signal or asynchronous signal is output. Since the gate signal is newly switched to an asynchronous gate signal or a synchronous gate signal to be output, the synchronous mode is set at the timing when the maximum value or the minimum value of each fundamental wave component is reached for each of U, V, and W phases individually. The gate signal can be switched between the asynchronous mode and the gate signal which does not include the DC component even when the mode of the gate signal is switched. Can generate positive and negative voltage is unbalanced as in the prior art, it is possible to prevent a phenomenon that generates an overcurrent causing biased magnetization of the main transformer.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a detailed internal configuration of a switching circuit in the control device.

FIG. 3 is a waveform chart showing the principle of the control method according to the first embodiment.

FIG. 4 is a timing chart showing one embodiment of the invention of claim 1;

FIG. 5 is a timing chart showing one embodiment of the invention according to claims 3 and 4;

FIG. 6 is a circuit block diagram of one embodiment of the invention of claim 5;

FIG. 7 is a timing chart illustrating a conventional example.

FIG. 8 is a waveform diagram illustrating a modulation method for comparing a modulated sine wave and a carrier triangular wave according to a conventional example.

FIG. 9 is a waveform diagram illustrating a modulation method for comparing a modulated square wave and a carrier inverted trapezoidal wave according to a conventional example.

FIG. 10 is a timing chart illustrating another conventional example.

FIG. 11 is a timing chart illustrating another conventional example.

FIG. 12 is a waveform chart for explaining the principle of generating a gate signal in an asynchronous mode according to another conventional example.

[Explanation of symbols]

1, 2 Data bus 3, 4 Latch 5, 6 Data bus 7u, 7v, 7w Switching circuit 8u, 8v, 8w Switching angle timing signal 9 Switching command signal 10u, 10v, 10w Gate signal rising or falling detection signal 71 , 72 Data bus 73 Switching angle timing signal 74 Switching command signal 75, 76 Register 77, 78 Data bus 79 Multiplexer 710 Data bus 711 Down counter 712 Output signal 11 Switching command signal 12u, 12v, 12w Switching angle timing signal 13u, 13v, 13w flip-flop circuit 14u, 14v, 14w Synchronous gate signal 15u, 15v, 15w Asynchronous gate signal 16u, 16v, 16w Gate signal 17u, 17v, 17w Multiplexer

────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Ujiie 1 Toshiba-cho, Fuchu-shi, Tokyo Inside the Fuchu factory, Toshiba Corporation (56) References JP-A-4-125070 (JP, A) JP-A-62- 77064 (JP, A) JP-A-2-311197 (JP, A) JP-A-2-42815 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 7/48 B60L 9 / 16 H02P 7/63

Claims (5)

(57) [Claims] When generating a gate signal for controlling a switching operation of a PWM inverter, in a synchronous mode in which the number of pulses within a half cycle is constant, a modulation method for comparing a modulated square wave with a carrier inverted trapezoidal wave, or by this, Switching from three pulses to one pulse or switching from one pulse to three pulses is performed individually for each phase of U, V, and W using a modulation method that generates a voltage pattern equivalent to the obtained signal by a command of voltage and frequency. A PWM inverter control method which is performed at a timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached. 2. A three-pulse gate signal generation circuit, a one-pulse gate signal generation circuit, fetching gate signals from these gate signal generation circuits, a common command for one-pulse / 3-pulse switching, and U, V, W more aND logic of a separate switch command pulse signal phase, 1 pulse gate signal and 3
The maximum value of the fundamental wave component of each phase
Control apparatus for a PWM inverter comprising comprising U, V, and an output gate signal switching circuit for each W-phase that outputs another changeover timing to reach the minimum value. 3. A PWM inverter control method for controlling a switching operation by switching a gate signal for controlling a switching operation of a PWM inverter between a synchronous mode and an asynchronous mode, wherein the method is common to U, V, and W phases. U, V, W after input of switching command of synchronous mode and asynchronous mode
A PW characterized in that a synchronous mode gate signal and an asynchronous mode gate signal are mutually switched at a timing when a maximum value or a minimum value of a fundamental wave component is reached for each phase individually.
Control method of M inverter. 4. The method of controlling a PWM inverter according to claim 3, wherein the on-pulse of the PWM inverter that is shorter than a minimum arc extinguishing period is turned off, and the off-pulse that is shorter than the minimum arc extinguishing period is turned on. A method for controlling a PWM inverter, comprising: performing mode switching at a timing when a modulation rate exceeding a predetermined value is reached near a switching point. Synchronous mode wherein a gate signal, Ri by switching signal and U asynchronous mode, V, to the AND logic of the switching signal in the W-phase individual switching angle, the phase of the fundamental wave component top
A switching signal generation circuit for each phase of U, V, W which outputs a switching signal of a synchronous mode and an asynchronous mode at a timing when the maximum value or the minimum value is reached, and a synchronous gate signal and an asynchronous gate signal for each phase are inputted; When a switching signal is input from the switching signal generating circuit for each phase, the U, V, and W phases which are switched from a synchronous gate signal or an asynchronous gate signal to a new asynchronous gate signal or a synchronous gate signal and output. And an output gate signal switching circuit for each of the PWM inverters.