JPH0678558A - Controlling of pwm inverter and controller using that controlling method - Google Patents

Abstract

PURPOSE:To do a switching operation without a phase shift by switching from three pulses to one pulse or vice versa at a specified timing separately for each of the U, V and W phases when controlling a switching operation of a PWM inverter. CONSTITUTION:A latch 3 which stores one-pulse pulse width data and a latch 4 which stores three-pulse pulse width data are installed on data buses 1, 2. Through data buses 5, 6, the data of each of the latches 3 and 4 is output to U-phase, V-phase and W-phase switching circuits 7u, 7v and 7w. Due to an AND logic of timing signals 8u-8w which provide a switching trigger and a one-pulse/three-pulse switching command signal 9, a one-pulse gate signal and a three-pulse gate signal are output, being shifted, from the switching circuits 7u-7w. The switching from the one-pulse gate signal to the three-phase one or vice versa is conducted at a timing when the maximum value or the minimum value of a fundamental wave component of each phase is reached. By this method, the switching can be done without a phase shift.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a voltage source PWM for driving an induction motor or a synchronous motor of an electric car, for example.
The present invention relates to a PWM inverter control method for controlling the switching operation of a variable voltage variable frequency inverter and a control device using the same.

[0002]

2. Description of the Related Art Conventionally, a gate signal applied to a switching element for controlling a switching operation of a voltage type PWM inverter for driving an induction motor of an electric vehicle is switched from 1 pulse to 3 pulses or from 3 pulses to 1 pulse. The control method for switching to was as shown in FIGS. 7 and 8. That is, as shown in FIG. 8, a gate signal obtained by comparing the modulated sine wave A and the carrier triangular wave B is
As shown in FIG. 7, when the angle reaches an integral multiple of 60 °, the U, V, and W phases are simultaneously switched. However, in FIG. 8, the angle α and the modulation rate AL (= the peak value of the modulated wave A /
The following relationship exists between the peak value of the carrier wave B).

[0003]

## EQU1 ## α = 60 (1-AL) (deg) (1) Then, the waveform diagram of FIG. 7 shows a waveform when switching from 3 pulses to 1 pulse is performed at an electrical angle of 60 °. is there.

However, when such a conventional modulation method and switching method are used, the waveform (hatched portion) during switching for one cycle including 180 ° before and after the switching angle is 3 When compared with a pulse waveform or a one-pulse waveform, the U, V, and W phases have different voltage areas.

The U-phase portion of this section has 3 pulses and 1 pulse, respectively.
When the pulse and the waveform in the middle of switching are expanded to the Fourier series, the fundamental wave component becomes as shown in the following equations (2) to (4),

[Equation 2] However, here, the ON voltage of the gate signal is E volt,
The off voltage is set to -E volt.

From equation (4), it can be seen that the waveform in the middle of switching contains a DC component. This is also the case when switching from one pulse to three pulses.

Therefore, a new modulation method using a modulation square wave C and a carrier inverse trapezoidal wave D as shown in FIG. 9 has been proposed and is currently used. However, the relationship between the angle α and the modulation rate AL in FIG. 9 is the same as in the equation (1).

However, even if the gate signal according to this new modulation method is used, the same problem still remains in the method in which the U, V and W phases are simultaneously switched at an integral multiple of 60 °.
That is, as shown in FIG. 10, when switching is performed at 60 °,
Comparing one cycle including 180 ° before and after centering on the switching point, the U-phase and the V-phase have the same voltage area before and after the switching, but the V-phase has a different voltage area. That is, when the above waveform is expanded into a Fourier series in the same manner as described above, the fundamental wave components for the U phase (the same for the W phase) and the V phase are respectively expressed by the following equations (5) to (7), Expressions (8) to (10) are obtained.

[0009]

[Equation 3] However, the on-voltage of the gate signal is set to E volt and the off-voltage of the gate signal is set to -E volt also here.

From now on, the waveform in the middle of switching between the U phase and the W phase does not include a DC component, and there is no phase shift compared to before and after switching, but in the V phase, the waveform during switching is inclusive of a DC component. Also, it can be seen that there is a phase shift compared to before and after switching.

Although FIG. 10 exemplifies 60 ° switching, when switching is performed at an angle that is an integral multiple of 60 °, any one phase includes a DC component in the voltage during switching as described above, and the phase shift occurs. Happens. The same applies when switching from one pulse to three pulses.

As described above, in the conventional PWM inverter control method, the DC voltage is included in the output voltage when the gate signal is switched from one pulse to three pulses or from three pulses to one pulse in the synchronous mode. However, there is a problem that the positive and negative voltages become unbalanced, which causes the main transformer to be demagnetized, resulting in overcurrent. In addition, a phenomenon may occur in which the output voltage is out of phase.

Further, conventionally, as a control method of a voltage type PWM variable voltage variable frequency inverter for driving an induction motor or a synchronous motor of an electric vehicle, a gate signal applied to a switching element of the inverter is a synchronous mode and an asynchronous mode of the above three pulses. A method of switching between and is also known.

Also in the control method for switching the synchronous mode and the asynchronous mode of the gate signal applied to the switching element of the PWM inverter, the switching between the synchronous mode and the asynchronous mode is performed at the electrical angle of 60 ° at the U, V and W3 phases simultaneously.
It was performed at the timing when it reached an integral multiple of (= π / 3). FIG. 11 shows a typical example of the gate signal waveform. In FIG. 11, the waveform of the gate signal in the synchronous mode of each phase is the waveform of the 3-pulse mode shown in FIG. 9, and the waveform of the gate signal of the asynchronous mode in each phase is shown in FIG.
It is generated by the PWM shown in FIG. That is, as shown in FIG. 12A, the carrier wave B ′ has a frequency of 1 kHz, the modulated wave A ′ has a frequency of 90 Hz, the minimum arc extinction period of the inverter is 50 μs, and the modulation rate AL is 90%.
Assuming that the carrier wave B ′ is PW by the modulated wave A ′,
By performing M, a gate signal in the asynchronous mode as shown in FIG.

Therefore, when the waveform of the gate signal is f (x) and this f (x) is expanded to the Fourier series, the constant term, that is, the DC term Bo is expressed by the following equation (11).

[0016]

[Equation 4] This expression (11) is equal to the area of the waveform f (x) divided by the period. That is, Bo
Is equal to the average height of the waveform f (x) over one cycle. Therefore, the carrier wave B ′ and the modulated wave A ′ are shown in FIG.
In the case of the positional relationship as shown in (a), the coordinates of the intersection of the carrier wave and the modulated wave are obtained by using the Newton method, and the angles θ1 to θ of each pulse of the gate signal waveform shown in FIG.
When 18 is obtained, the respective values are as follows.

[0017]

Θ1 = 0.33 (rad) θ2 = 0.18 θ3 = 0.45 θ4 = 0.07 θ5 = 1.08 θ6 = 0.07 θ7 = 0.45 θ8 = 0.18 θ9 = 0 .33 θ10 = 0.33 θ11 = 0.18 θ12 = 0.45 θ13 = 0.07 θ14 = 1.08 θ15 = 0.07 θ16 = 0.45 θ17 = 0.18 θ18 = 0.33 The above figure In the waveform of the gate signal in the synchronous mode shown in FIG. 9, the relationship between the modulation rate AL and the angle α is as shown in the equation (1). If this is expressed in radians (rad),

[Equation 6] Becomes Since the modulation rate AL is assumed to be 90% here, α = 0.1 (rad).

Therefore, using these values, the DC component Bo of each waveform in FIG. 11 is 180 ° (=
When it is obtained for one cycle including π), it becomes as follows.

[0019]

[Formula 7] U-phase Asynchronous waveform: BUa ≈ 0 Synchronous waveform: BUs = 0 Asynchronous-synchronous switching waveform: BUas ≈ 0 V-phase Asynchronous waveform: BVa ≈ 0 Synchronous waveform: BVs = 0 Asynchronous-synchronous switching waveform: BVas ≈- 0.55 W phase Asynchronous waveform: BWa ≈ 0 Synchronous waveform: BWs = 0 Asynchronous-synchronous switching waveform: BWas ≈ 0 From the above calculation results, it can be seen that the negative DC component is superimposed on the V phase in this case. . In this way, when the U, V, and W phases are simultaneously switched at an electrical angle that is an integral multiple of 60 ° (= π / 3), the positive / negative of the gate signal of any one phase becomes unbalanced, which causes the deviation of the main transformer. There was a problem that caused magnetism.

[0020]

As described above, the conventional P
In the control method of the WM inverter, the gate signal given to the switching element of the inverter is 1 pulse in the synchronous mode,
When switching between the three-pulse modes, or when switching between the synchronous mode and the asynchronous mode, all phases were switched at the same electrical angle at the same time, so the output voltage contains a DC component and the positive and negative voltages become unbalanced. However, there is a problem that the main transformer is biased and an overcurrent is generated, and there is also a problem that the output voltage may cause a phase shift.

The present invention has been made in view of such conventional problems, and a DC component is added to the fundamental wave component of the gate signal when switching from 3 pulses to 1 pulse and when switching from 1 pulse to 3 pulses. It is an object of the present invention to provide a control method of a PWM inverter which does not include the above and can be switched without causing a phase shift and a control device using the same.

The present invention also provides a control method of a PWM inverter and a control device using the same, which can switch a gate signal so as not to include a DC component when switching between a synchronous mode and an asynchronous mode. To aim.

[0023]

The PWM of the invention of claim 1
The inverter control method is a modulation method that compares a modulated square wave with an inverse carrier trapezoidal wave in a synchronous mode in which the number of pulses in a half cycle is constant when generating a gate signal that controls the switching operation of a PWM inverter, or Using a modulation method that generates a voltage pattern equivalent to the signal obtained by the command of voltage and frequency, switching from 3 pulses to 1 pulse or from 1 pulse to 3 pulses is performed for each U, V, W phase. It is performed individually at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached.

According to a second aspect of the present invention, there is provided a PWM inverter control device in which a 3-pulse gate signal generation circuit, a 1-pulse gate signal generation circuit, and gate signals from these gate signal generation circuits are fetched and 1-pulse / 3-pulse switching is performed. Of the U pulse, the V pulse, the W pulse, and the W pulse that individually output the switching command pulse signals of the U, V, and W phases. And an output gate signal switching circuit.

According to a third aspect of the present invention, there is provided a PWM inverter control method for controlling a switching operation by switching a gate signal for controlling a switching operation of a PWM inverter between a synchronous mode and an asynchronous mode. W
Synchronous mode gate signal and asynchronous mode gate signal at the timing when the maximum value or the minimum value of the fundamental wave component of each U, V, W phase is individually reached after inputting the synchronous mode / asynchronous mode switching command common to each phase. To switch between each other.

According to a fourth aspect of the present invention, in the control method for the PWM inverter according to the third aspect, correction is performed such that an ON pulse of a PWM arc inverter having a minimum arc extinction period or less is turned OFF, and an OFF pulse of the minimum arc extinction period or less is turned ON, The mode switching is executed at the timing when the modulation rate exceeds a predetermined value near the mode switching point.

According to a fifth aspect of the present invention, there is provided a PWM inverter control device in which the switching signal for switching between the synchronous mode and the asynchronous mode of the gate signal and the switching signal for the individual switching angles of each phase are AN.
A switching signal generation circuit for each phase of U, V, and W that outputs a switching signal for synchronous mode and asynchronous mode by D logic, and a synchronous gate signal and an asynchronous gate signal for each phase are input, and a switching signal for each phase When the switching signal is input from the generation circuit, the output gate signal for each phase of U, V, and W which is output by switching from the synchronous gate signal or the asynchronous gate signal up to that time to the asynchronous gate signal or the synchronous gate signal is output. Be prepared.

[0028]

According to the control method of the PWM inverter of the first aspect of the invention, the gate signals of the U, V and W phases are not switched to one pulse or three pulses at a uniform switching angle, but to each other.
By switching at the point where the voltage area becomes equal for each phase, the DC component is not included in the fundamental wave component of the output voltage, and the phase shift occurs by switching at the maximum or minimum value of the fundamental wave of the same gate signal. Generate a gate signal without
This allows gate control of the PWM inverter.

In the control device for the PWM inverter according to the second aspect of the present invention, the output gate signal switching circuit for each phase of U, V and W outputs the gate signals from the pulse gate signal generating circuit and the one pulse gate signal generating circuit. Capture and output 1-pulse gate signal and 3-pulse gate signal by mutually switching by AND logic of common command for 1-pulse / 3-pulse switching and U-, V-, and W-phase individual switching command pulse signals. Thus, the U, V, and W phases can be individually performed at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached.

According to the control method of the PWM inverter of the third aspect of the invention, when the gate signal for controlling the switching operation of the PWM inverter is switched between the synchronous mode and the asynchronous mode, the synchronous mode common to each phase of U, V and W, After inputting the command to switch the asynchronous mode, the U, V, and W phases are switched individually between the synchronous mode and the asynchronous mode at the timing when the maximum value or the minimum value of the fundamental wave component is reached. It is possible to generate a gate signal that is not included and has no phase shift, thereby performing the gate control of the PWM inverter.

According to the control method of the PWM inverter of the fourth aspect of the present invention, the ON pulse of the PWM extinguishing period less than the minimum extinction period is turned off, and the OFF pulse of the extinguishing period less than the minimum extinction period is turned on to perform correction in the vicinity of the mode switching point. By executing the mode switching at the timing when the modulation rate that exceeds the specified value is reached, the command value near the center of the half cycle of the gate signal of each phase can be set to the minimum value or the maximum value, and the DC component can be reliably It is possible to perform gate control of the PWM inverter by generating a gate signal that does not include phase shift and does not include phase shift.

In the control device for the PWM inverter of the fifth aspect of the present invention, the output gate signal switching circuit for each phase of U, V and W includes a switching signal for switching the gate signal between the synchronous mode and the asynchronous mode and a switching angle for each phase. Of the switching signal in
When the synchronous mode / asynchronous mode switching signal is fetched from the switching signal generation circuit for each phase of U, V, W which outputs the synchronous mode / asynchronous mode switching signal by D logic, the synchronous gate signal or asynchronous By switching from the gate signal to the asynchronous gate signal or the synchronous gate signal and outputting the new signal, the synchronous mode or the asynchronous mode is executed at the timing when the maximum value or the minimum value of each fundamental wave component of each of U, V, and W phases is reached. Mutual switching of gate signals can be performed.

[0033]

Embodiments of the present invention will now be described in detail with reference to the drawings. 1 and 2 show a circuit of an embodiment of a control device for a PWM inverter according to a second aspect of the invention, which uses the method for controlling a PWM inverter according to the first aspect of the invention. In the circuit diagrams of FIGS. 1 and 2, the voltage and the frequency are adjusted so that an output signal equivalent to that obtained by the modulation method of comparing the modulated square wave C and the carrier inverse trapezoidal wave D as shown in FIG. 9 is obtained. P that generates a gate signal pattern in response to a command
Of all the digital circuits of the controller of the WM inverter,
In particular, the circuit configuration of the portion for switching the number of pulses is shown.

In this control device, 1 and 2 are a data bus, 3 is a latch for storing pulse width data of 1 pulse,
Reference numeral 4 is a latch for storing the pulse width of 3 pulses, and 5 and 6 are data buses for transmitting the data of these latches. The data buses 5 and 6 enable the data of the latches 3 and 4 to be U phase, V phase, Switching circuits 7u, 7 for each W phase
It is designed to be sent to v, 7w. Each of the switching circuits 7u, 7v, 7w switches data at the timing of the switching angle of each phase, and has the circuit configuration of FIG. 2 as described later.

Timing signals 8u, 8v, 8w for giving a switching trigger are input to the switching circuits 7u, 7v, 7w, respectively, and a 1-pulse / 3-pulse switching command signal 9 is commonly input. It is like this. Therefore, when the 1-pulse / 3-pulse switching command signal 9 is input to each of the switching circuits 7u, 7v, and 7w, the U-phase timing signal 8u is 30 ° or 21 °.
At 0 °, the V phase timing signal 8v is −30 ° or 1
At 50 °, the W-phase timing signal 8w is 270 °
Alternatively, the pulse width is switched by each triggering at 90 °, and then the pulse width is counted and the U phase,
The rising or falling detection signals 10u, 10v, 10w of the V-phase and W-phase gate signals are output.

The switching circuits 7u, 7v, 7w have the same configuration as shown in FIG.
2 (corresponding to the data buses 5 and 6 in FIG. 1), each phase switching angle timing signal 73 (the signal 8u in FIG. 1,
8 v, 8 w), 1 pulse / 3 pulse switching command signal 74 (corresponding to signal 9 in FIG. 1) as an input, 1 pulse pulse width data register 75, 3 pulse pulse width data register 76 , Internal data bus 7
7, 78, a multiplexer 79, a data bus 710, and a down counter 711. From the down counter 711, a signal 712 for detecting rising or falling of each phase gate signal (output signals 10u, 10 in FIG. 1).
(corresponding to v, 10w) is output.

Next, a method of controlling the PWM inverter by the controller for the PWM inverter having the above structure will be described.

The pulse width data of 1 pulse sent from the data bus 1 is stored in the latch 3, the pulse width data of 3 pulses sent from the data bus 2 is stored in the latch 4, and these are stored in the data bus 5. , 6 to send to the switching circuits 7u, 7v, 7w of each phase. Switching circuit for each phase 7
u, 7v, and 7w include a 1-pulse / 3-pulse switching command signal 9 and a switching timing signal 8u (angle of 30 ° or 210 that is the maximum or minimum value of the U-phase fundamental wave).
°), 8v (similar angle of V phase -30 ° or 1
50 °), 8w (similar angle of W phase: 90 ° or 270 °).

The operation of each of the switching circuits 7u, 7v, 7w will be described with reference to FIG. 2. One phase of pulse width data is loaded into the register 75 by the phase switching timing signal 73 via the data bus 71. ,
The pulse width data of 3 pulses is loaded into the register 76 via the data bus 72.

The pulse width data loaded in these registers 75 and 76 is sent to the multiplexer 79 through the data buses 77 and 78, and any one of the data is transmitted in accordance with the 1-pulse / 3-pulse switching command signal 74. It is loaded into the down counter 711 via 710.

The down counter 711 counts down the pulse width data to be loaded and outputs a borrow signal 712 at the timing when the count value becomes zero. This signal 712 is a signal for detecting the rising or falling of the gate signal of each phase of U, V and W in FIG. 1 (when the switching occurs at the maximum value of the fundamental wave component of the gate signal, the detection of the falling edge of the pulse). Signal, pulse rise detection signal when switching occurs at the minimum value) 10u, 10v, 10
w.

In the 1-pulse / 3-pulse switching process performed using the above PWM inverter controller, as shown in FIG. 4, the U-phase, V-phase, and W-phase are 30 ° and −30, respectively.
Switching from 3 pulses to 1 pulse with a switching angle of 90 ° and 90 °, 3 pulses for the part in the middle of switching for one cycle including the 180 ° before and after each switching angle (hatched part) Comparing three waveforms, a pulse waveform and a waveform switched in the middle, it can be seen that the voltage areas are all equal.

If this is explained using the U phase as an example,
When the above-mentioned one period of these three kinds of waveforms is expanded into a Fourier series, all the fundamental wave components are (5) to (7).
It becomes the same as the expression, and it can be seen that the DC component is not included in the fundamental wave component of the output voltage in any waveform during switching, before switching, and after switching, and there is no phase shift.

In the above embodiment, the method of switching from 3 pulses to 1 pulse has been described, but the same applies to the case of switching from 3 pulses to 1 pulse.

An embodiment of the control method of the PWM inverter according to the invention of claims 3 and 4 will be described. FIG. 5 shows a gate signal waveform in the asynchronous mode, a gate signal waveform in the synchronous mode, and a gate signal waveform in the middle of asynchronous-synchronous switching for each of U, V, and W phases according to an embodiment of the present invention. The asynchronous waveform of each phase is as shown in FIG.
In this embodiment, the carrier wave B'of 1 kHz has a waveform as shown in FIG. 9B obtained as a result of PWM by the modulated wave A'of 90 Hz. Further, in this case, the off-pulse γ of about 50 μs or less, which is the minimum extinction period of the PWM inverter,
ON pulse 1 and ON pulse γ2 less than the minimum extinction period
Is corrected so that the command value near the center of the half cycle of the fundamental wave becomes the maximum value or the minimum value.

The synchronizing waveform is obtained by PWMing the square carrier C with the inverted trapezoidal modulated wave D as shown in FIG.

Therefore, in this embodiment, the asynchronous mode-synchronous mode switching command for all U, V and W phases is 0 electrical angle.
In the U phase, the actual switching is performed at the angle π / 6 (rad) (which takes the minimum value in this case) as the timing when the fundamental wave takes the maximum value or the minimum value. To be done. In the V phase, the angle of 5π / 6 (rad
) (Which takes the minimum value in this case) and the actual switching is performed in the W phase at an angle π (rad) (which takes the maximum value in this case).

When the switching timing of the gate signal between the asynchronous mode and the synchronous mode is set in this way,
The switching waveform does not include a DC component, and thus does not include a DC component that causes bias magnetization of the main transformer. Explaining the reason for this, from the above equation (11), when the gate waveform is symmetric, that is, when the area of the negative half-wave is equal to the area of the positive half-wave, the average area is also equal to 0 and the constant The term, and therefore the DC component, is also zero. Since the gate waveform is a square wave, if the sum of the on-pulse angles and the sum of the off-pulse angles of the gate waveform in one cycle are equal and the respective π radians are used, the DC component is not included. Become.

In the case of the above-described embodiment, the areas are the same on the left and right sides because they are symmetrical with respect to the maximum or minimum value of the fundamental wave of each phase of U, V and W. And asynchronous mode,
Since no DC component is included in any gate waveform in the synchronous mode, no DC component is included in the switching waveform. Therefore, this switching waveform does not cause magnetic bias in the main transformer circuit of the PWM inverter whose switching is controlled.

Further, the maximum value or the minimum value of the fundamental wave of each phase is near the center of the half wave, and the on-pulse γ2 or the off-pulse γ1 of a minute time appears here, but the minimum extinction time of the inverter is about 50 μs or less. By deleting the on-pulse or off-pulse of, the command value near the center of the half cycle can be set to the maximum value or the minimum value.

FIG. 6 shows a circuit block diagram of an embodiment of the controller of the invention of claim 5 which uses the control method of the PWM inverter of the above embodiment. In this control device, the mode switching signal 11 commonly given to each phase is used as the D input, and the mode switching signals 12u, 1 are set at the individual electrical angles of each phase.
2v, 12w are provided as clock inputs, and flip-flop circuits 13u, 13v, 13w for outputting an "H" signal are provided by these two inputs. The outputs of the flip-flop circuits 13u, 13v, and 13w are used as S inputs, the synchronous mode gate signals 14u, 14v, and 14w for each phase shown in FIG. 5 are input to A, and the asynchronous mode gate signals for each phase are input. 15u, 15v, 15w
Is the B input, and A is input each time the "H" signal is input to the S input.
The gate signals 16u and 16 are switched by switching between the input and the B input.
multiplexers 17u and 17 for outputting as v and 16w
It is equipped with v and 17w.

In the control device for the PWM inverter having the above configuration, each flip-flop circuit 13u, 13v, 13
The asynchronous-synchronous mode switching signal is input to the electrical angle 0 in common with w. Further, pulse waveforms 12u, 12v, 12w that are turned on at the maximum value or the minimum value of the fundamental wave component for each phase
Are provided as clock inputs. And in this case U
Phase waveform 12u is π / 6 (= 30 °) or 7π / 6
(= 210 °), the V-phase waveform 12v is 5π / 6 (= 15
0 °) or 11π / 6 (= 330 °), W phase waveform 1
2w is 3π / 2 (= 270 °) or π / 2 (= 90)
Each becomes "H" at °).

Therefore, the common mode switching signal 11 is inputted, and the respective flip-flop circuits 13u, 13v, 13 are inputted.
If the above-mentioned pulse waveforms 12u, 12v, 12w are input for each w, the "H" signal from each of the flip-flop circuits 13u, 13v, 13w at the timing of the maximum value or the minimum value of each waveform, the multiplexers 17u, 17v,
17w is given to each S input.

As a result, each multiplexer 17u, 17
From v, 17w to the above timing, that is, π / 6 (= 30 °) or 7π / 6 in the U phase as shown in FIG.
(= 210 °), 5π / 6 (= 150 °) or 11π / 6 (= 330 °) in V phase, 3π / 2 (= 2 in W phase)
70 °) or π / 2 (= 90 °), the gate signals 16u, 16v, 16w whose asynchronous-synchronous modes are switched are output. The gate signal of each of these phases does not include a direct current component, and thus does not include a direct current component that may cause the magnetic bias of the main transformer.

[0055]

As described above, according to the invention of claim 1,
A modulation method that compares a modulated square wave with an inverted trapezoidal carrier wave, or a modulation method that generates a voltage pattern equivalent to the signal obtained by the voltage and frequency commands is used.
Switching from pulse to 1 pulse, or from 1 pulse to 3
Since switching to pulse is performed for each U, V, W phase individually at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached, before pulse switching in each phase,
During switching, there is no change in the voltage area after switching, the DC component is not included in the fundamental wave component of the gate signal, and it is possible to switch without causing phase shift, and the positive and negative voltages become unbalanced as in the past, and this is the main transformer. Stable gate control can be achieved by preventing the phenomenon that overcurrent is generated by causing the magnetism of the device.

According to the second aspect of the present invention, the output gate signal switching circuit for each of the U, V and W phases fetches the gate signals from the pulse gate signal generating circuit and the one pulse gate signal generating circuit and outputs one pulse. Since a common command for / 3 pulse switching and an individual switching command pulse signal for each of U, V, and W phases are ANDed, the 1-pulse gate signal and the 3-pulse gate signal are switched and output. The U, V, and W phases can be individually performed at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached, and the fundamental wave component of the gate signal does not include a DC component,
Switching can be done without causing phase shift.

According to the third aspect of the invention, when the gate signal for controlling the switching operation of the PWM inverter is switched between the synchronous mode and the asynchronous mode, the synchronous mode and the asynchronous mode common to each of U, V and W phases are switched. After inputting the command, the synchronous mode and asynchronous mode are switched at the timing when the maximum value or the minimum value of the fundamental wave component of each U, V, W phase is reached, so that even if the gate signal mode is switched. A gate signal that does not include a DC component can be generated, and the positive and negative voltages become unbalanced as in the past, which prevents the phenomenon that the main transformer is biased and overcurrent is generated. You can control.

According to the fourth aspect of the present invention, correction is performed by turning on the ON pulse of the minimum extinction period or less of the PWM inverter and turning on the off pulse of the minimum extinction period or less, and setting a predetermined value near the mode switching point. Since the mode switching is executed at the timing when the modulation rate exceeds the limit, the command value near the center of the half cycle of the gate signal of each phase can be set to the minimum value or the maximum value. It is possible to generate a gate signal that does not include a direct current component, and it is possible to reliably prevent the conventional phenomenon that the main transformer is biased and an overcurrent is generated.

According to the fifth aspect of the present invention, the output gate signal switching circuit for each phase of U, V and W is provided with a switching signal for switching between the synchronous mode and the asynchronous mode of the gate signal and a switching signal at a switching angle for each phase. When the synchronous mode / asynchronous mode switching signal is fetched from the switching signal generation circuit for each phase of U, V, W that outputs the synchronous mode / asynchronous mode switching signal by AND logic, the synchronous gate signal or asynchronous Since the gate signal is newly switched to the asynchronous gate signal or the synchronous gate signal for output, the synchronous mode is performed at the timing when the maximum value or the minimum value of the fundamental wave component of each U, V, W phase is reached. , Asynchronous mode The gate signal can be switched between each other, and even if the gate signal mode is switched, the gate signal does not include the DC component. Can generate positive and negative voltage is unbalanced as in the prior art, it is possible to prevent a phenomenon that generates an overcurrent causing biased magnetization of the main transformer.

[Brief description of drawings]

FIG. 1 is a circuit block diagram of an embodiment of the invention of claim 2;

FIG. 2 is a block diagram showing a detailed internal configuration of a switching circuit in the control device.

FIG. 3 is a waveform diagram showing the principle of the control method according to the first aspect of the invention.

FIG. 4 is a timing chart showing an embodiment of the invention of claim 1;

FIG. 5 is a timing chart showing an embodiment of the inventions of claims 3 and 4.

FIG. 6 is a circuit block diagram of an embodiment of the invention of claim 5;

FIG. 7 is a timing chart illustrating a conventional example.

FIG. 8 is a waveform diagram illustrating a modulation method for comparing a modulated sine wave and a carrier triangular wave of a conventional example.

FIG. 9 is a waveform diagram illustrating a modulation method for comparing a modulated square wave and a carrier inverse trapezoidal wave of a conventional example.

FIG. 10 is a timing chart illustrating another conventional example.

FIG. 11 is a timing chart illustrating another conventional example.

FIG. 12 is a waveform diagram illustrating the principle of generating another asynchronous mode gate signal according to another conventional example.

[Explanation of symbols]

1, 2 Data bus 3, 4 Latch 5, 6 Data bus 7u, 7v, 7w Switching circuit 8u, 8v, 8w Switching angle timing signal 9 Switching command signal 10u, 10v, 10w Detection signal of rising or falling of gate signal 71 , 72 data bus 73 switching angle timing signal 74 switching command signal 75, 76 register 77, 78 data bus 79 multiplexer 710 data bus 711 down counter 712 output signal 11 switching command signal 12u, 12v, 12w switching angle timing signal 13u, 13v, 13w Flip-flop circuit 14u, 14v, 14w Synchronous gate signal 15u, 15v, 15w Asynchronous gate signal 16u, 16v, 16w Gate signal 17u, 17v, 17w Multiplexer

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akihiko Ujiie No. 1 Toshiba-cho, Fuchu-shi, Tokyo Toshiba Corporation Fuchu factory

Claims (5)

[Claims] 1. When generating a gate signal for controlling a switching operation of a PWM inverter, a modulation method for comparing a modulated square wave and an inverted trapezoidal carrier wave in a synchronous mode in which the number of pulses in a half cycle is constant, or by this. Switching from 3 pulses to 1 pulse or from 1 pulse to 3 pulses by using a modulation method that generates a voltage pattern equivalent to the obtained signal by a voltage and frequency command individually for each U, V, W phase And a method of controlling the PWM inverter, which is performed at the timing when the maximum value or the minimum value of the fundamental wave component of each phase is reached. 2. A 3-pulse gate signal generation circuit, a 1-pulse gate signal generation circuit, and a gate signal from these gate signal generation circuits are fetched and a common command for 1-pulse / 3-pulse switching and U, V, W 1 pulse gate signal and 3 by AND logic with individual phase switching command pulse signal
U, V, which switch and output pulsed gate signals mutually
A PWM inverter control device comprising an output gate signal switching circuit for each W phase. 3. A PWM inverter control method for controlling a switching operation by switching a gate signal for controlling a switching operation of a PWM inverter between a synchronous mode and an asynchronous mode, which is common to U, V and W phases. After inputting the switching command between synchronous mode and asynchronous mode, U, V, W
A PW characterized in that the synchronous mode gate signal and the asynchronous mode gate signal are switched to each other at the timing when the maximum value or the minimum value of each fundamental wave component is reached for each phase.
Control method of M inverter. 4. The method for controlling a PWM inverter according to claim 3, wherein correction is performed by turning off an ON pulse of a minimum extinction period or less of the PWM inverter and turning on an off pulse of the minimum extinction period or less of the mode. A method for controlling a PWM inverter, characterized in that mode switching is executed at a timing when a modulation rate exceeding a predetermined value is reached near the switching point. 5. A synchronous mode / asynchronous mode switching signal is output by AND logic of a synchronous mode / asynchronous mode switching signal of a gate signal and a switching signal at a switching angle for each phase. A switching signal generation circuit and a synchronous gate signal and an asynchronous gate signal for each phase are input, and when a switching signal is input from the switching signal generation circuit for each phase, from the synchronous gate signal or the asynchronous gate signal up to that point A PWM inverter control device further comprising an output gate signal switching circuit for each phase of U, V, and W that newly outputs by switching to an asynchronous gate signal or a synchronous gate signal.