JP3239873B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory,
In particular, the present invention relates to a semiconductor memory device for selecting a sense amplifier connected to each bit line of a cell array.

[0002]

2. Description of the Related Art FIG. 5 is a diagram schematically showing a configuration of a semiconductor memory device of this kind. In the figure, reference numeral 504 denotes a cell, and 502-0 and 502-1 denote a cell array composed of a plurality of cells 504. Each cell 504 has a gate connected to a word line WL, and each word line WL selects a cell 504 in the row direction. On the other hand, cell array 1
The drain and source of each cell 504 in the column direction of No. 4 include:
Each bit line BL is connected, one cell is selected by the bit line BL and the word line WL, and the selected cell is precharged. Reading and writing of data from the selected cell are performed in the same manner.

[0003] Each bit line BL is connected to a corresponding sense amplifier SA1 to SA4. Here, in FIG. 5, the sense amplifier SA1 is connected to the bit lines BL1 and BL2, and the sense amplifier SA2 is connected to the next bit lines BL3 and BL4. A sense amplifier SA3 is connected to the bit lines BL5 and BL6, and a sense amplifier SA4 is connected to the next bit lines BL7 and BL8.

That is, the sense amplifiers SA are arranged in a so-called staggered manner, and half of the cells included in the cell array 502-0 are connected to the sense amplifiers SA1 and SA3 belonging to the sense amplifier row 506-0, and the rest are connected. Half are sense amplifiers SA belonging to sense amplifier row 506-1.
2, SA4.

FIG. 8 is a block diagram showing a specific configuration of the above-described semiconductor memory device. Each sense amplifier array 802 and cell array 804 are arranged alternately. Each sense amplifier column 802 is connected to a sense amplifier selection circuit 808 for selecting each sense amplifier SA included therein, and each cell array 804 selects a cell in a row direction by each word line WL. Decoder 806 is connected to each of them.

The sense amplifier selection circuit 808-1 includes NAND gates 808-00 and 808-01, and a NOR gate 81.
0-0, inverters 812-00, 812-01, P-type transistor 814-0, and N-type transistor 816-
It consists of 0. Other sense amplifier selection circuits have the same configuration. Here, in FIG. 8, when the block selection signal A1 is input to the NAND gate 808-00 of the sense amplifier selection circuit 808-1, an "L" level selection signal BSEL1 is output to the sense amplifier array 802-1.
Subsequently, when the sense signal SENS is input to the NOR gate 810-0, the drive signals SAP and S of the sense amplifier SA are driven.
AN is output to the sense amplifier array 802-1. Thereby, the sense amplifiers in the sense amplifier array 802-1 (the sense amplifiers corresponding to SA2 and SA4 in FIG.
1 and SA3).
Then, the bit line B connected to the selected sense amplifier
The cell in the cell array 804-0 is selected by L and the word line WL which the decoder 806-0 has already selected and output by the selection signal BSEL1 and a selection signal (not shown).

On the other hand, when the NAND gate 808-10 of the sense amplifier selection circuit 808-2 is selected by the block selection signal A2, similarly, the selection signal BSE at "L" level
L2 is output to the sense amplifier array 802-2. Subsequently, when the sense signal SENS is input to the NOR gate 810-1, the drive signals SAP and SA of the sense amplifier SA are driven.
N is output to the sense amplifier array 802-2. Thereby, the sense amplifiers in the sense amplifier row 802-2 (FIG. 5)
Are sense amplifiers corresponding to SA2 or SA4), and the bit line BL connected to the selected sense amplifier is connected to the decoder 13
2 selects a cell in the cell array 142 by the word line WL which has already been selected and output by the selection signal BSEL2 and a selection signal (not shown). Also, at this time, since the selection signal BSEL2 at the "L" level is output from the sense amplifier selection circuit 112 connected to the output of the NAND gate 21 of the sense amplifier selection circuit 113 to the sense amplifier row 122, (The sense amplifiers corresponding to SA2 and SA4 or the sense amplifiers corresponding to SA1 and SA3 in FIG. 5) are selected, and the bit line BL connected thereto and the decoder 806 are selected.
The cell in the cell array 804-1 is selected by the word line WL which has already been selected and output by the selection signal BSEL2 and a selection signal (not shown).

FIG. 9 is a circuit diagram showing an example of the sense amplifier 902 included in each sense amplifier array 802. The sense amplifier 902 arranged at the center of the figure includes P-type transistors 904-0 and 904-1 and an N-type transistor 906.
−0 and 906-1, and the bit lines BL1 and BL2 are connected to the connection points of the transistors 904-0 and 906-0 and the connection points of the transistors 904-1 and 906-1, respectively, which are the outputs of the sense amplifier 902. . Further, the sense amplifier drive signals SAP and SAN described above are applied to the source connection points of the P-type transistors 904-0 and 904-1 and the source connection points of the N-type transistors 906-0 and 906-1, respectively. I have. 912
-0 to 912-5 are N-type transistors. Also, B
SEL1a is a sense amplifier selection signal, and when "L", the sense amplifier SA is selected. Further, TG0 and TG1 shown in the figure are separation signals for separating the selected cells from the non-selected cells by separating the sense amplifiers SA.

FIG. 10 is a time chart showing the state of cell selection. The outline of the cell selection operation will be described with reference to this time chart.

After the selection signal BSEL becomes "L" at time t1 and the sense amplifier row is selected, the word line WL becomes "H" level by the decoder 806 at time t2, and the sense signal SENS at time t3. By the input, the sense amplifier drive signals SAP and SAN become “H” and “L”, respectively, as shown in FIG. Thus, each bit line BL connected to the sense amplifier SA (902)
1 and BL2 become "H" and "L", respectively, and at the time of the change of the bit line BL, the selected cell is precharged. Writing and reading of data to and from the selected cell are also performed at the same timing.

[0011]

As described above, in the conventional semiconductor memory device described above, since two bit line pairs share one sense amplifier, the bit line pair on the non-selected side is used. Transistors 914-0 to 914-3 are provided so as to be separated from the sense amplifier, and these transistors are controlled using separation signals TG0 and TG1. However, as described above, the isolation transistor is interposed between the bit line pair and the sense amplifier, and this is used as the isolation signal TG.
There is a problem that turning on and off using 0 and TG1 is a factor that hinders speeding up. For this reason, as shown in FIG.
In some cases, the structure 300 in which 914-3 and its separated signals TG0 and TG1 are deleted is used.

However, since the structure 300 shown in FIG. 3 has no isolation transistor, two corresponding bit line pairs are always connected to the sense amplifier 302. Therefore, as in the structure 900 shown in FIG. 9, the corresponding two bit line pairs cannot be independently selected using the block selection signals BSEL1a and BSEL0a,
Both bit line pairs are simultaneously selected or deselected by one block selection signal BSEL. Conversely, each sense amplifier needs to perform selection using the common block selection signal BSEL regardless of whether one adjacent memory cell array is selected or the other memory cell array.

This means that it is necessary to use the signal Z shown in FIG. 8 as the block selection signal BSEL supplied to each sense amplifier row.

However, generation of the signal Z (block selection signal BSEL) requires more time than generation of the block selection signals BSEL1 and BSEL2. That is,
As shown in FIG. 7A, the block selection signals BSEL1 and BSEL2 are generated when the block selection signals A1 and A2 input to the NAND gates 808-00 and the like of the sense amplifier selection circuit 808 are composed of addresses X5 to X0. BSE when X5 to X0 is "111111"
A specific block selection signal may be selected for a specific combination of addresses X5 to X0, such as outputting L0 and outputting BSEL1 when "111110". For this reason, as shown in FIG.
08-00 as it is, the block selection signal BSEL
1 or BSEL2, while the signal Z
To generate the (block selection signal BSEL), FIG.
As shown in (b), it is necessary to further AND the outputs of the two NAND gates.

As shown in FIG. 7C, X0 and X1
The logical product of X0T1T, the logical product of X0 and X1 (bar) is X0T1N, and the logical product of X0 (bar) and X1 is X0N1.
The logical product of T, X0 (bar) and X1 (bar) is X0N1N
And Also, the logical product of each combination of X2, X2 (bar) and X3, X3 (bar), and X4, X4
The logical product of each combination of (bar) and X5, X5 (bar) is the same as in the case of X0 and X1.

In this case, for example, the inverter 812 in the sense amplifier selection circuit 808-1 in FIG.
7B, when the signal Z is output as BSEL as shown in FIG. 7B, the input side of the NAND gate 808-00 in the sense amplifier selection circuit 808-1 is X0T1T, X2T3T and X4T5T are input. Further, as shown in FIG. 7B, X0N1T, X2T3T, and X4T5T are input to the input side of the NAND gate 808-10 in the sense amplifier selection circuit 808-2. Each sense amplifier selection circuit 808-
NAND gates 808-00, 808 within 1,808-2
-10, the sense amplifier selection circuit 808-
1 and a NAND gate 808-01 and an inverter 812
The selection signal BSEL is output via the signal -00, which is shown in FIG.
Are provided as the above-described selection signals BSEL.

As described above, as in the structure 300 shown in FIG. 3, even if the isolation transistor and the isolation signal TG are removed from each sense amplifier array 800 and the signal propagation from the cell array to the sense amplifier is accelerated, the block selection signal is not changed. BSE
The logic up to the output of L becomes complicated as shown in FIG. 7 (b), and a delay occurs here, so that the effect of increasing the speed has been offset.

Therefore, according to the present invention, the block selection signal B
It is an object of the present invention to simplify logic until SEL is output and realize high-speed reading.

[0019]

In order to solve the above-mentioned problems, the present invention provides a plurality of cell arrays, a plurality of decoders for selecting cells of each cell array in a row direction via word lines, and a plurality of cell arrays. A plurality of sense amplifier rows each having a sense amplifier arranged in a staggered manner via a bit line to a cell of each cell array in an adjacent column direction and a sense amplifier row based on a plurality of address bits; And a plurality of sense amplifier selection circuits outputting a selection signal for selecting a sense amplifier in the semiconductor memory device, the lower two address bits of the plurality of address bits input to the sense amplifier selection circuit are gray-coded. They are arranged in order.

Further, the sense amplifier selection circuit, the sense amplifier array, and the cell array are arranged in accordance with the arrangement order of the lower two address bits.

The sense amplifier selection circuit inputs one of the lower two bits of the plurality of address bits and a signal obtained by decoding the address bits excluding the lower two bits, and outputs a selection signal. is there.

The lower two bits are arranged in the order of first, second, third and fourth, and one of the lower two bits is input to a sense amplifier selection circuit corresponding to the second arrangement, In this configuration, the other of the lower two bits is input to the sense amplifier selection circuit corresponding to the array of No. 3.

Each of the sense amplifier selection circuits arranged corresponding to the first and fourth arrangements is configured to receive a signal obtained by decoding lower two bits.

Further, the word line selection of the decoder is performed based on the logical product output of the selection signal from the sense amplifier selection circuit adjacent to the decoder.

Also, the semiconductor memory device according to the present invention
In a semiconductor memory device in which a plurality of sense amplifier columns and a plurality of memory cell arrays are alternately arranged, the plurality of memory cell arrays are arranged in an order in which an address signal for selecting the plurality of memory cell arrays is a gray code. The amplifier row is selected based on a part of the address signal.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device 10 according to the present invention.
FIG. 3 is a block diagram showing a configuration of a 0. FIG. 2 is a diagram showing an arrangement state of each part of the semiconductor memory device.

In this semiconductor memory device, as shown in FIG. 2, the sense amplifier rows 102-0 to 102-3 and the cell arrays 104-0 to 104-3 are alternately arranged. Each of the sense amplifiers SA connected in a staggered manner to the cells of each cell array in the adjacent column direction via the bit line BL is provided in 102-0 to 102-3.
Is provided. Also, each sense amplifier row 102-0
102 to 102-3, a sense amplifier selection circuit 106 for selecting a sense amplifier SA in the sense amplifier row 102.
−0 to 106-3 are connected to each of them. Each of the cell arrays 104-0 to 104-3 has a decoder 108-0 to select a cell in the row direction by a word line WL.
8-3 are connected to each.

The sense amplifier selection circuit 106-1 is arranged as shown in FIG.
As shown in the figure, the NAND gate 110-0 and the NOR gate 11
2-0, inverter 114-0, P-type transistor 11
6-0 and an N-type transistor 118-0. Here, in FIG.
When the block selection signal is input to the NAND gate 110-0 of the 6-1, the output of the NAND gate 110-0 becomes “L”.
And this is output to the sense amplifier array 102-1 as the selection signal BSEL1. Subsequently, when the sense signal SENS is input to the NOR gate 112-0, the inverter 11
“H” via the P-type transistor 116-0
Level sense amplifier drive signal SAP is output to sense amplifier row 102-1 and N-type transistor 1
18-0 to "L" level sense amplifier drive signal SA
N is output. Thereby, the sense amplifier array 102-
2 are selected (sense amplifiers corresponding to SA1 to SA4 in FIG. 2). Then, the cells in the cell array 104-0 are selected by the bit line BL connected to the selected sense amplifier and the word line WL which the decoder 108 has already selected and output based on the selection signal BSEL1 and a selection signal (not shown). That is, the cells connected to the sense amplifiers SA2 and SA4 in the sense amplifier array 102-1 in FIG. 2 and the cells in the cell array 104-1 (that is, the sense amplifier SA in the sense amplifier array 102-1 in FIG. 2).
1, the cell connected to SA3) is selected.

When a block selection signal is input to the NAND gate 110-1 of the sense amplifier selection circuit 106-2, an "L" level selection signal BSEL2 is similarly output to the sense amplifier array 102-2. Subsequently, when the sense signal SENS is input to the NOR gate 112-1,
The “H” level drive signal SAP and the “L” level drive signal SAN are output to the sense amplifier array 102-2.
As a result, the sense amplifiers (sense amplifiers corresponding to SA1 to SA4 in FIG. 2) in the sense amplifier array 102-2 are selected, and the decoder 108 has already selected and output based on the selection signal BSEL2 and a selection signal (not shown). The connected word line WL and the bit line BL connected to the selected sense amplifier are connected to the cells in the cell array 104-1 (that is, the sense amplifiers SA2 and SA4 in the sense amplifier row 102-2 in FIG. 2). Cell) and cell array 10
4-2 (that is, the sense amplifier row 102-
2 connected to the sense amplifiers SA1 and SA3)
Is selected.

As described above, the sense amplifier selection circuit 106
The cells in the cell arrays 104-0 and 104-1 are selected by the output of the selection signal BSEL1 from -1. The output of the selection signal BSEL2 from the sense amplifier selection circuit 106-2 causes the cells in the cell arrays 104-1 and 104-2 to be selected. The cell is selected. When the selection signal BSEL0 is output from the sense amplifier selection circuit 106-0, the sense amplifiers SA1 and SA3 shown in FIG.
Is selected, and a cell in the cell array 104-0 connected thereto is selected. Further, the sense amplifier selection circuit 1
When the selection signal BSEL3 is output from 06-3, the sense amplifier SA shown in FIG.
1 to SA4 are selected, and the selected sense amplifiers SA2, SA
4 connected to the cell array 104-2 and the cell array 1 connected to the selected sense amplifiers SA1 and SA3
The cell in 04-3 is selected.

FIG. 3 is a circuit diagram showing a configuration of a sense amplifier having a configuration 300 in which the isolation transistor and isolation signal TG are deleted from the sense amplifier row circuit shown in FIG. The sense amplifier SA in FIG.
Transistors 304-0 and 304-1 and N-type transistors 306-0 and 306-1, and transistors 304-0 and 306-0 which are outputs of the sense amplifier SA.
And the connection points of the transistors 304-0 and 306-1 are connected to the bit lines BL1 and BL2, respectively.
Further, the above-described sense amplifier drive signals SAP and SAN
Are the source connection points of P-type transistors 304-0 and 304-1 and N-type transistors 306-0 and 306, respectively.
-1 is applied to the source connection point. Note that 308-0 to 308-2 in the drawing are N-type transistors. BSEL is a sense amplifier selection signal, and when "L", the sense amplifier SA is selected.

By the way, the signal input to the NAND gate 110-0 of the sense amplifier selection circuit 106-1 shown in FIG.
Of the bit input selection signals, two bits use the selection signal B obtained by decoding the block address, and the remaining one bit uses the predecode signal C before decoding the block address.

In this case, the block addresses X5 to X5
The block addresses are rearranged so that the relationship between X0 and the selection signal BSEL is as shown in FIG.

That is, if the block addresses X5 to X0 are "1"
11111 ", BSEL0 is output, and X5 to X0
Is "111110", BSEL1 is output, and when X5 to X0 are "111100", BSEL1 is output.
2 and outputs X when X5 to X0 are “111101”.
Rearrange to output SEL3. That is, the lower two bits X1, X2 in the gray code order in which the lower two bits of the block addresses X5 to X0 always change by one bit.
Rearrange X0. Then, the gray code is supplied as the predecode signal C of the NAND gate 110 of the sense amplifier selection circuit 106.

As described above, the block addresses X5 to X0
When the sense amplifier row is selected based on the data, the pre-decode signals (predecode signal C) of the block addresses X5 to X0 are supplied to the NAND gate 11 of the sense amplifier selection circuit 106.
It is configured to be given as an input of 0. As a result, there is no need for a logic gate disposed before the NAND gate 110 to decode the block addresses X5 to X0, and the circuit configuration is simplified. Further, the simplification of the circuit configuration eliminates the delay of the selection signal BSEL, thereby enabling high-speed access to the cell array.

FIG. 4B shows the sense amplifier selection circuit 10.
6 is a diagram showing an input state of each of the inputs a1 to a3 of the sixth NAND gate 110. FIG.

Here, the NAND gate 110 shown in FIG.
-9 to 110-2 are NAND gates 1 of the sense amplifier selection circuits 106-0 to 106-3 shown in FIGS.
10 respectively.

That is, the input a2 of each NAND gate 110 of each of the sense amplifier selection circuits 106-0 to 106-3 shown in FIG. 1 and FIG.
The logical product of X3 is input. The logical product of the block address bits X4 and X5 is input to the input a3 of each NAND gate 110 of each of the sense amplifier selection circuits 106-0 to 106-3.

The logical product of the block address bits X0 and X1 is input to the input a1 of the NAND gate 110-9 of the sense amplifier selection circuit 106-0, and the input of the NAND gate 110-0 of the sense amplifier selection circuit 106-1 is input. a1 includes, among the block address bits X0 and X1,
The undecoded bit X1 is input as it is, and the NAND gate 110-1 of the sense amplifier selection circuit 106-2 is input.
Of the block address bits X0 and X1, the inverted signal (X0
N) is input as it is and the sense amplifier selection circuit 106
The inverted signal (X1N) of the undecoded bit X1 of the block address bits X0 and X1 is input to the input a1 of the -3 NAND gate 110-2.

Then, for example, a circuit as shown in FIG.
When one block A is provided, the sense amplifier selection circuits 106-0 to 106-3 in the block A, the sense amplifier row 1
02-0 to 102-3, decoders 108-0 to 108
-3 and the cell arrays 104-0 to 104-3 are arranged in the order of the gray code, and the block A is first selected by the block address bits X5 to X2, and which of the sense amplifier selection circuits in the block A is selected in the lower order. The determination is made by the two bits X1 and X0 as described above.

In short, the sense amplifier arrays 102-0 to 102-1
02-3 are arranged in the order of the gray code, and the selected signals BSEL0 to BSEL3 based on the logic according to the gray code.
Therefore, for example, when all of the block addresses X5 to X1 are at the "H" level and one of the cell arrays 104-0 or 104-1 is selected, these cell arrays 104-0 and 104- are selected. 1 is selected by the selection signal BSEL1 irrespective of the logic of X0, and the necessary selection signal is obtained without taking the logical product of the two selection signals as in the related art. Is activated.

The block selection signal BS according to the present invention
In the EL, since the sense amplifier row is selected in a different form from the conventional block selection signal, the logic of the decoder is slightly complicated, and the selection of the word line is delayed as compared with the conventional one. However, as shown in FIG. 10, the selection of a word line is performed at a time later than the block selection, so that the access time to the memory cell is not affected.

FIG. 6 is a block diagram showing a main configuration of the decoder 13 for selecting a word line.

Here, FIG. 6A shows the decoder 10 of FIG.
8-0, the NOR gate 602 of the decoder 108-0 has a selection signal BSEL0 from the sense amplifier selection circuit 106-0 and a sense amplifier selection circuit 106
The select signal BSEL1 from −1 is input, the logical sum of them is obtained by the NOR gate 602, and the result is output to the NAND gate 604. In addition to the output from the NOR gate 602, other address signals for selecting the cell array 104-0 are input to the NAND gate 604. The NAND gate 604 calculates the logical product of these input signals, and outputs the logical product of the input signals via the inverter 606. The corresponding word line WL is selected by the logical product output.

The decoder shown in FIG. 6B is the decoder 806-0 of the conventional device shown in FIG.

Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 11 is a diagram showing an arrangement of sense amplifier rows 0 to 16 and memory cell arrays 0 to 15 in the semiconductor memory device according to the present embodiment, and both are arranged alternately as shown. In addition, each of the sense amplifier rows 0 to 1
6 are corresponding selection signals BSEL0 to BSEL, respectively.
For example, the sense amplifier row 0 is selected by the selection signal BSEL0, and the sense amplifier row 1 is selected by the selection signal BSEL1. Since the number of memory cell arrays is 16, four bits of addresses X0 to X3 are used to determine which memory cell array is to be selected.

FIG. 12 shows the relationship between the logic of these addresses X0 to X3 and the selected memory cell array. FIG.
As can be seen from FIG. 2, addresses X0 to X3 are "0000", "0001",
The memory cell array that is selected as it changes as "0010" does not simply change as "0", "1", or "2", but is selected according to the logic according to the gray code.

For example, when all of the addresses X1 to X3 are "1", the selected memory cell array is "0" or "1", and which of these is selected depends on the remaining address X0. When all of the addresses X1 to X3 are “0”, the selected memory cell array is “10” or “11”, and which of these is selected depends on the remaining address X0. Only decided. Also, addresses X0, X
When X2 and X3 are “0”, “1”, and “1”, respectively, the selected memory cell array is “1” or “2”.
Which of these is selected depends only on the remaining address X1. Similarly, address X1
When .about.X3 are "0", "1", and "1", respectively, the selected memory cell array is "2" or "3", and which of these is selected depends on the remaining address X0. Only depends on.

That is, the memory cell array 0 and the memory cell array 1 and the memory cell array 1 and the memory cell array 2
As described above, adjacent memory cell arrays always have a relationship in which only one certain bit is selected by a different address.

Recall that the sense amplifier rows and the memory cell arrays are alternately arranged. Each sense amplifier row (for example, sense amplifier row 1) has a memory cell array (memory cell array 0) adjacent to one side. Alternatively, the fact that the memory cell array (memory cell array 1) adjacent to the other side is selected is determined by the 4-bit addresses X0 to X
It will be understood that it can be known by the logical level (all 1) of the address (X1 to X3) of 3 bits out of 3. For this reason, each sense amplifier column monitors both the address of the memory cell array adjacent to one side and the address of the memory cell array adjacent to the other side as in the related art, and one of them is selected. Is no longer required to be activated in response to the request, but only by decoding a part of the address. That is, the time required to generate each selection signal BSEL can be reduced. This point is as described in the above embodiment.

Next, referring to FIG.
A circuit for generating SEL0 to BSEL16 will be described. As shown in FIG. 13, each selection signal BSEL0
To BSEL16 are generated by corresponding two-input NAND gates, and signals such as addresses X0D1T and X2N3T are supplied to these two-input NAND gates. Here, T indicates high active, N indicates low active, and D indicates don't care. For example, the address X0D1T is X
This signal is activated ("H" level) if X1 is at "H" level regardless of the logical level of 0, and X2N3
T is a signal that is activated (“H” level) when X2 is at “L” level and X3 is at “H” level. Here, it should be noted that a signal including "D (don't care)" is always applied to the inputs of the NAND gates that generate the selection signals BSEL1 to BSEL15.

The signals such as the addresses X0D1T and X2N3T are generated by the circuit shown in FIG. FIG.
As shown in the figure, these addresses X0D1T and X2N3T
Are generated from one NAND gate and one inverter. For example, X0T1T is generated by a NAND gate receiving addresses X0T and X1T and an inverter that inverts its output, and X2N3T is generated by a NAND gate receiving addresses X2N and X3T and an inverter that inverts its output. Also,
Address containing "D (don't care)", for example, X0T1
D is generated by a NAND gate receiving the address X0T and the power supply potential and an inverter for inverting the output of the NAND gate. Here, T indicates high active and N indicates low active. For example, the address X0T is a signal that is activated (“H” level) if X0 is at “H” level, and X2N is X2N If the signal is at "L" level, the signal is activated ("H" level). Here, "D
(For example, X0T1D) including "(don't care)"
Generates an input signal (X0T) and an output signal (X
Note that 0T1D) is the same signal.

That is, in generating an address (for example, X0T1D) including "D (don't care)", an address (for example, X0
T1T) has the same circuit configuration as that of the generation circuit, and its generation timing is made coincident with the generation timing of an address that does not include "D (don't care)".

Therefore, in the semiconductor memory device according to the present embodiment, all of the address signals X0T1D and X2N3T shown in FIG. 14 are substantially at the same timing regardless of whether or not "D (don't care)" is included. Since the transition occurs, each circuit shown in FIG. 13 receiving the transition does not generate an erroneous output, and thus has an effect that the operation margin in the actual circuit operation is greatly improved.

In this embodiment, as shown in FIG. 14, a circuit having the same circuit configuration is used for generating the addresses X0T1D and X2N3T, but this is the most preferable example and is not necessarily limited to this. Never. In other words, even if the circuit configurations are different from each other, any circuit configuration may be used as long as all the address signals X0T1D and X2N3T transition at substantially the same timing.

[0058]

As described above, according to the present invention, a plurality of cell arrays, a plurality of decoders for selecting cells in each cell array in a row direction via word lines, and a plurality of decoders are arranged between the cell arrays. In addition, a plurality of sense amplifier rows each having a sense amplifier connected in a staggered manner via a bit line to a cell of each cell array in an adjacent column direction, and a sense amplifier in the sense amplifier row based on a plurality of address bits. In a semiconductor memory device having a plurality of sense amplifier selection circuits for outputting a selection signal for selection, a plurality of address bits input to the sense amplifier selection circuit are arranged in gray code order, so that logic for decoding a block address is used. Since a gate is not required, the circuit configuration can be simplified, and a selection signal for selecting a sense amplifier row is provided. Delay no longer occurs in, the cell array can be selected and therefore at high speed.

Since the word line selection of the decoder is performed based on the logical product output of the selection signal from the sense amplifier selection circuit adjacent to the decoder, the word line selection conventionally provided in the decoder is performed. This has the effect of eliminating the need for the timing signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to the present invention.

FIG. 2 is a diagram showing an arrangement state of each unit of the semiconductor memory device.

FIG. 3 is a circuit diagram showing a configuration of a sense amplifier in the semiconductor memory device.

FIG. 4 is a diagram showing a relationship between a block address of a semiconductor memory device and a selection signal for selecting a sense amplifier row.

FIG. 5 is a diagram schematically showing a configuration of a semiconductor memory device.

FIG. 6 is a block diagram showing a main configuration of a decoder of the semiconductor memory device.

FIG. 7 is a diagram showing a relationship between a block address of a conventional semiconductor memory device and a selection signal for selecting a sense amplifier row.

FIG. 8 is a block diagram showing a configuration of a conventional device.

FIG. 9 is a circuit diagram showing a configuration of a conventional sense amplifier.

FIG. 10 is a time chart showing the operation timing of each unit in the semiconductor memory device.

FIG. 11 is a diagram showing an arrangement state of a sense amplifier array and a memory cell array in a semiconductor memory device according to a second embodiment of the present invention.

FIG. 12 is a table showing a relationship between logics of addresses X0 to X3 and a selected memory cell array.

FIG. 13 is a circuit diagram showing a circuit that generates selection signals BSEL0 to BSEL16.

FIG. 14 is a circuit diagram showing a circuit for generating an address X0T1D and the like.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 semiconductor memory device 102,506 sense amplifier array 104,502 memory cell array 106 sense amplifier selection circuit 108 decoder 110,604 NAND gate 112,602 NOR gate 114,606 inverter 116,304 p-type transistor 118,306,308 n-type transistor 504 memory Cell BSEL select signal SENS sense signal B select signal C predecode signal X address signal SA sense amplifier BL bit line

Claims (6)

(57) [Claims] A plurality of cell arrays; a plurality of decoders for selecting cells of each cell array in a row direction via word lines; and a plurality of decoders arranged between the cell arrays and adjacent to each other in a column direction. On the other hand, a plurality of sense amplifier rows each having a sense amplifier connected in a staggered manner via a bit line, and a plurality of sense amplifiers outputting a selection signal for selecting a sense amplifier in the sense amplifier row based on a plurality of address bits A plurality of address bits input to the sense amplifier selection circuit .
The plurality of address bits are arranged in gray code order, and the word line selection of the decoder is adjacent to the decoder.
Based on the logical product output of the selection signal from the sense amplifier selection circuit
The semiconductor memory device which comprises carrying out Hazuki. 2. The semiconductor memory device according to claim 1, wherein said sense amplifier selection circuit, sense amplifier row, and cell array are arranged in accordance with an arrangement order of lower two address bits. 3. The sense amplifier selecting circuit according to claim 1, wherein one of the lower two bits of the plurality of address bits and a signal obtained by decoding the address bits excluding the lower two bits are input. And outputting the selection signal. 4. The sense amplifier selection circuit according to claim 3, wherein said lower two bits are arranged in a first, second, third, and fourth order, and are arranged corresponding to said second arrangement. Receives one of the lower two bits,
2. The semiconductor memory device according to claim 1, wherein the other of the lower two bits is input to a sense amplifier selection circuit arranged corresponding to the third arrangement. 5. The sense according to claim 3, wherein the lower two bits are arranged in a first, second, third and fourth order, and are arranged corresponding to the first and fourth arrangements. A semiconductor memory device, wherein a signal obtained by decoding the lower two bits is input to an amplifier selection circuit. 6. In a semiconductor memory device in which a plurality of sense amplifier rows and a plurality of memory cell arrays are alternately arranged, the plurality of memory cell arrays are arranged in an order in which an address signal for selecting the array is a gray code.
In addition, the plurality of sense amplifier rows receive the address signal.
One of the lower two bits and the lower two bits
A semiconductor memory device which is selected by a signal obtained by decoding an address bit except for the address bit .