JP3239084B2 - Multicarrier transmission interleaving apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interleave apparatus and method for use in digital broadcasting by, for example, multicarrier transmission.

[0002]

2. Description of the Related Art In recent years, digital satellite television broadcasting systems have been realized and spread, but terrestrial broadcasting also has the same tendency. In terrestrial broadcasting, a multipath failure (ghost) due to reflection, a Rayleigh fading failure due to movement, etc., which do not occur in a satellite or the like, occur.
A method called DM (orthogonal frequency division multiplexing) is considered promising.

[0003] In digital transmission, error correction is indispensable from the viewpoint of changes in transmission paths and improvement of transmission characteristics. However, when a continuous error such as a burst error occurs, the correction capability is exceeded. Correction becomes impossible. For this reason, a data rearrangement operation called interleaving is performed to spread the burst error to the preceding and following blocks so as not to exceed the correction capability.

[0004] Some types of interleaving are classified according to a method of rearranging data. Among them, since block interleaving is also easy, it has been often used before. Others include convolutional interleaving ("Burst-Correcting Codes for the Classic"
Bursty Channel ", G, D, Forney, Jr.).

Convolutional interleaving is said to be effective against periodic burst errors caused by radar interference and the like (NASA, “SN users guide, A
ppendix J and K ”, STDN No, 101.2, Revison 6, 199
1.), is being used in various places.

[0006] The adverse effects of multipath are related to the phase.
As shown in FIG. 9, a sharp drop occurs at a specific frequency. Since data in this period is lost, a burst-like error occurs. In particular, in Rayleigh and Rice fading, as shown in FIG. 10, the signal is greatly attenuated in the time direction, and a very long burst-like error is likely to occur.

As described above, it is difficult to form an interleaved block having an arbitrary depth in interleaving in conventional multicarrier transmission, and the circuit scale becomes extremely enormous.

[0008]

As described above, in the conventional interleaving in multicarrier transmission,
It is difficult to configure an interleaved block having an arbitrary depth, and there is a problem that the circuit scale becomes extremely large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-carrier transmission interleave apparatus and method capable of solving the above-mentioned problems and facilitating the configuration of an interleave block having an arbitrary depth and reducing the circuit scale. I do.

[0010]

According to the present invention, there is provided a multicarrier transmission interleave apparatus and method for transmitting data using a plurality of carriers, the method comprising the steps of: A write address and a read address are generated in the row direction and the column direction, and the write address and the read address are sent to the memory circuit while controlling the output timing.
At this time, in a memory space having a row and column directions of the memory circuit constitutes a sub-block at a specific value, before
By configuring the writing direction with multiple sub-blocks,
Convolutional interleaving is performed for each sub-block.
U. In this case, in the memory circuit, the address in the row direction
To interleave in the frequency direction and add
Simultaneous interleaving in the time direction using
Can be.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a multi-carrier transmission interleave device according to the present invention. A write address generator (W-addr) 11 and a read address generator (R-addr) 12 have the same clock CK.
A write address and a read address are generated in accordance with. The addresses generated by the address generators 11 and 12 are all switched by the selector 13 between the read cycle and the write cycle in one clock.
It is sent to M14. If the RAM 14 has separate address lines for reading and writing,
Of course, you can use it. RAM 14
Input data IN is written during a write cycle, and data stored during a read cycle is read to obtain output data OUT.

The operation of the interleave device having the above configuration will be described below.

As described above, the nature of the error differs between the multipath in which data is lost in a symbol shown in FIG. 9 and the Rayleigh fading in which data is lost in a symbol unit shown in FIG. The present invention focuses on this,
Separating each unit for multipath and Rayleigh fading realizes more effective interleaving.

For this purpose, the interleaving in the carrier (frequency) direction f and the temporal (time) direction t is effective. However, since the interleaving is conventionally performed separately, an overhead due to a peripheral circuit for address generation and a plurality of RAMs are required. It is a problem. Therefore, in the present invention, each optimization is set as follows.

First, the interleaving in the time direction (column) t will be described.

Assuming multiplexed transmission, etc., frame synchronization can be made unnecessary by using convolutional interleaving in the time direction. However, when the number of data in the carrier direction is large, interleaving in the time direction is required. Too deep, increased interleaving delay,
There is a problem with increasing the capacity of the buffer. Therefore, a sub-block is formed by setting the value in the carrier direction to an integer multiple of a certain appropriate value Bz, and the interleave depth is repeated in sub-block units. FIG. 2 shows an outline of this processing.

FIG. 2 conceptually shows how the RAM 14 rearranges data. The vertical axis represents the carrier direction f and the horizontal axis represents the time direction t. , Interleave depth 4
Is shown. When this circuit is applied to OFDM having a different number of carriers, the same circuit is simply extended in the carrier direction by making an integer multiple of a certain value Bz in any case with a different number of carriers. realizable.

Next, the interleaving in the carrier direction (row) f will be described.

In the multipath, as shown in FIG.
Since data is lost in the symbol, the data is restored from adjacent surviving data. At this time, as shown in FIG. 2, the write row address is operated as a normal counter that increases by one. Also, the read row addresses are at equal intervals,
Alternatively, a quadratic function, or an M sequence (M sequence is an abbreviation of a maximum length sift register)
The stage is composed of two stages of feedback shift registers, and the period is 2 ⁿ
−1 bit, and 2 ⁿ⁻¹ “1s” in one cycle,
The feature is that a random signal containing 2 ⁿ -1 "0" is obtained. ) Or a specific function, RO
By referring to an M table or the like, a value is selected so that adjacent samples are appropriately separated. As a result, as shown in FIG. 9, it is possible to disperse the data error of the carrier part which has dropped sharply as a whole, and it is possible to suppress the error not to exceed the correction capability. Of course, the same operation may be performed at the write address.

In addition, when mobile reception is not taken into consideration only with multipath, time interleaving requiring a large-capacity memory area does not need to be used, so that interleaving in the carrier direction is set to block interleaving.
It is also possible to operate each independently. In either case, the configuration can be easily realized.

Further, the sharing of the circuit will be described.

For comparison, FIG. 3 shows a conceptual circuit configuration of convolutional interleaving conventionally considered. In the conventional configuration, for example, when the interleave depth is set to 12, one is set to through, and thereafter, 11 FIFO shift registers 21 to 21 expanded by one cell are used.
31 are prepared in parallel, and the input data IN
Are sequentially led to a through path and eleven shift paths, and the output of each path is sequentially extracted by a switch 33.

However, in the conventional configuration as described above, since there is a through path (the top path without delay), the paths before and after the register cannot be selected arbitrarily. On the other hand, according to the configuration of the above-described embodiment, as shown in FIG. 2, the through path can be eliminated and the selection order can be changed before and after the register, so that the interleaving in the frequency direction f can be replaced by the interleaving circuit in the time direction t. It becomes possible to incorporate.

Further, as shown in FIG. 4, even if the depth in the time direction is set to 1 in this structure, if the RAM address is reduced while maintaining the same circuit, interleaving only in the frequency direction f is realized. can do.

In general, as the number (points) of RAMs increases, overhead such as an address decoder for accessing the RAM cells and a wiring area becomes large. Can be reduced.

The number of OFDM carriers is 1 k, 2 k, 4
Although values such as k and 8k are used, for example, when operation at 8k, which is the maximum among these, is configured with interleaving / deinterleaving, the carrier direction is shortened in 1k transmission, so that the RAM usage rate is reduced to 1/8. Becomes

However, generally, the longer the interleave depth, the better the performance against worse fading. Therefore, when the number of carriers is different, for example, in the example of this embodiment, the interleaving depth at 1 k is made eight times, so that it can be realized only by changing the row address of the RAM 4 to a partial column address. It is. FIG. 5 shows a conceptual diagram when the interleaving depth is increased and the carrier direction is shortened.

Therefore, the multi-carrier transmission interleave device having the above configuration can easily configure an interleave block having an arbitrary depth, and furthermore, has a RA
Since it is realized by the write / read control of M14,
The circuit scale can be reduced as compared with the related art.

FIG. 6 shows an application example of the interleave device according to the present invention. Reference numeral 41 denotes a demultiplexer (DE-MPX) for decomposing input data in bit units.
Each bit output decomposed by the demultiplexer 41 is output to a block interleave processing unit (block length B
z) After being subjected to interleave processing in units of blocks in 42, they are combined in a multiplexer (MPX) 43. Further, the signal is input to the convolutional interleave circuit 44 for each sub-block shown in the first embodiment,
Interleaving in which sub-blocks are repeated every carrier number Bz is performed and output.

That is, when the convolutional interleave according to the first embodiment is combined with the bit interleave as described above, the bit interleave block size is set to an integral multiple of the value of the block interleave (of course, it may be equal). Therefore, the bit interleave falls within the symbol, and the consistency can be improved.

In the description of the above embodiment, the case of interleaving has been described, but this is of course applicable to deinterleaving. FIGS. 7 and 8 show conceptual configurations of deinterleaving corresponding to the conceptual configurations of interleaving shown in FIGS. 2 and 5, respectively.

According to the configuration of the above-described embodiment, the convolutional type interleave eliminates the need for synchronization detection and employs a frame structure with a combination of small blocks. Therefore, it is easy to configure an interleave block having an arbitrary depth. become. Further, by sharing the frequency-time interleave, the circuit scale can be reduced.

[0034]

As described above, according to the present invention, it is possible to provide a multicarrier transmission interleave apparatus and method which can easily configure an interleave block having an arbitrary depth and can reduce the circuit scale. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a multicarrier transmission interleave device according to the present invention.

FIG. 2 is a diagram showing a conceptual configuration for explaining the operation of the embodiment.

FIG. 3 is a block diagram showing a circuit configuration of a conventional convolutional interleave for comparison with the embodiment.

FIG. 4 is a block diagram showing a modification of the embodiment.

FIG. 5 is a block diagram showing a modification of the embodiment.

FIG. 6 is a block diagram showing an application example of the embodiment.

FIG. 7 is a block diagram illustrating a conceptual configuration of a deinterleave device corresponding to the configuration of FIG. 2;

FIG. 8 is a block diagram showing a conceptual configuration of a deinterleave device corresponding to the configuration of FIG. 5;

FIG. 9 is an operation diagram illustrating characteristics of a transmission path.

FIG. 10 is an operation diagram showing characteristics of a transmission path.

[Explanation of symbols]

 11 Write address generator 12 Read address generator 13 Selector 14 RAM 21-31 FIFO shift register 32, 33 Switch 41 Demultiplexer 42 Block interleave processing unit 43 Multiplexer 44 Convolutional interleave circuit

──────────────────────────────────────────────────の Continued on the front page (72) Inventor Keisuke Harada 5-2-2-8 Akasaka, Minato-ku, Tokyo Inside the Next Generation Digital Television Broadcasting System Research Laboratories (72) Inventor Hidenori Tsuboi Isogo, Yokohama-shi, Kanagawa 8 Shin-Sugita-cho, Ward Toshiba Multimedia Engineering Laboratory Co., Ltd. (56) References JP-A-8-265177 (JP, A) JP-A-7-254915 (JP, A) JP-A 8-32460 (JP, A) JP-A-8-32632 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 1/00-1/20 H04J 11/00 H03M 13/27

Claims (8)

(57) [Claims] 1. A multi-carrier transmission interleave apparatus for transmitting data using a plurality of carriers, wherein: a write address generating means for generating a write address in a row direction and a column direction based on a clock synchronized with the data; Address generating means for generating a read address in the row direction and the column direction on the basis of: a timing control means for selecting the output timing of the write address and the read address; and a write address and a read address controlled by the timing control means. based on provided with a memory circuit for reading outputs write data, in the memory space having a row and column directions of the memory circuit constitutes a sub-block at a specific value, the whereabouts
The direction is composed of a plurality of sub-blocks.
Multi-carrier transmission interleaving , wherein convolutional interleaving is performed on a block-by-block basis, and interleaving in the frequency direction using the address in the row direction and interleaving in the time direction using the address in the column direction are simultaneously performed in the memory circuit. apparatus. 2. The multicarrier transmission interleave apparatus according to claim 1, wherein said write address generation means and read address generation means use a function for generating said read / write address in said row direction. 3. The write address generating means and the read address generating means generate a read / write address in a row direction by adding integer values and obtaining a remainder with the number of effective data carriers. The multi-carrier transmission interleave device according to claim 1. 4. The method according to claim 1, wherein said write address generation means and read address generation means use an M series for said read / write address in said row direction.
A multi-carrier transmission interleaving device as described. 5. The multicarrier transmission interleave device according to claim 1, wherein said write address generation means and read address generation means use block interleaving for said row direction interleaving. 6. The multi-carrier transmission interleaving apparatus according to claim 1, wherein when the bit interleaving is performed in the preceding stage, the size of the sub-block is an integral multiple of the block length of the preceding bit interleaving. Item 2. The multicarrier transmission interleave device according to Item 1. 7. A multi-carrier system according to claim 1, wherein, when a data signal is input by a multi-carrier transmission system in which the number of carriers can be selected, the interleaving depth in the column direction is increased as the number of carriers decreases. Carrier transmission interleave device. 8. A multi-carrier transmission interleave method for transmitting data using a plurality of carriers, wherein a write address and a read address in a row direction and a column direction are generated based on a clock synchronized with the data, respectively. And the output of the read address is selected according to the interleave, and the memory circuit writes and reads out the data based on the selected write address and read address, and has a row direction and a column direction of the memory circuit . among the memory space, it constitutes a sub-block at a specific value, the whereabouts
The direction is composed of a plurality of sub-blocks.
Multi-carrier transmission interleaving , wherein convolutional interleaving is performed on a block-by-block basis, and interleaving in the frequency direction using the address in the row direction and interleaving in the time direction using the address in the column direction are simultaneously performed in the memory circuit. Method.