JP3238159B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for introducing impurities.

[0002]

2. Description of the Related Art In recent years, in semiconductor integrated circuits, elements have been miniaturized, and conductive layers have also been formed in areas smaller than 0.2 μm. Along with this, the diffusion of conductive impurities is required to be controlled more precisely than before.

Conventionally, diffusion control of conductive impurities such as phosphorus, arsenic, and boron in a silicon substrate has been performed by changing a heat treatment temperature and a heat treatment time. For example, in order to form a source region and a drain region in the manufacture of a MOS transistor, an impurity having a small diffusion coefficient is selected from impurities of the same conductivity type and introduced into a predetermined region by using a technique such as ion implantation. Thereafter, it has been proposed to perform a short-time impurity activation heat treatment at a low temperature to reduce the diffusion length of the impurity in the depth direction and the lateral direction. Further, in order to form a well region, a long-time heat treatment is performed at a high temperature to greatly increase the diffusion length of impurities.

It is known that the diffusion length of impurities in silicon in such a heat treatment step is generally proportional to the square root of Dt. Here, D is the diffusion coefficient of the impurity, and t is the heat treatment time. The value of the diffusion coefficient D is obtained for a case where the lattice defect concentration (vacancy concentration Cv · interstitial silicon atom concentration C1) in the silicon substrate is in a thermal equilibrium state (Cv · C1 = constant).

In the 1970's, it was reported that during oxidation of a silicon substrate, diffusion of impurities in the substrate proceeded much faster than in the case of thermal equilibrium.

[0006] This phenomenon is called oxidation enhanced diffusion (OED). The reason is that during the oxidation of the silicon substrate, a large amount of interstitial silicon atoms are generated at the interface between the oxide film and the silicon and diffuse into the substrate, thereby promoting the diffusion of impurities in the process.

On the other hand, it has been reported that diffusion of antimony is rather slowed down during oxidation of a silicon substrate. This phenomenon is called oxidation slowed diffusion (ORD) because the diffusion of vacancies is involved in the diffusion of antimony, and the interstitial silicon atoms generated during oxidation reduce the concentration of vacancies. It is to reduce by a binding reaction.

As described above, it is known that the impurity diffusion phenomenon depends on the type and concentration of the lattice defect, but the quantitative value is not known exactly. The focus was on minimizing the effect of lattice defects on GaN, and active utilization of lattice defects was not considered at all. Further, in the conventional technique, it is extremely difficult to control the lattice defect concentration in a wide concentration region.

For example, there are various problems in the diffusion technique for diffusing impurities. One of them is the depth of the impurity diffusion layer. That is, the depth of the impurity diffusion layer must be reduced when the element is miniaturized. However, it is extremely difficult to implant the impurity diffusion layer at a relatively high concentration and shallow, and there is a limit to reducing the impurity layer.

For example, in the case of a doped oxide method in which boron is diffused into a silicon substrate by using a glass layer (BSG) containing boron, which is generally used as a p-type impurity for a silicon substrate, as a diffusion source. Is that the diffusion coefficient in the glass layer is smaller than the diffusion coefficient in the silicon substrate by two digits or more. Therefore, the diffusion of such impurities is often limited by the diffusion of impurities in the glass layer.

Therefore, when boron impurities are to be introduced into the silicon substrate at a high concentration of, for example, 10 ²⁰ cm ⁻³ or more, BSG containing boron at a higher concentration than the above concentration is required.
Diffusion treatment must be performed in a relatively high temperature atmosphere of 1000 ° C. or higher using a film. In such a diffusion process, it is necessary to gradually carry the wafer into or out of the diffusion furnace in order to suppress stress on the wafer. For this reason, the impurities are diffused during this time, and the region into which the impurities are introduced is widened. Thus, it is extremely difficult to form a shallow impurity diffusion layer.

There is also a method of performing heat diffusion in a short time by using a lamp heating furnace. With this method, it is possible to make the impurity layer shallow, but on the other hand, the dispersion increases, making it difficult to obtain a desired impurity layer stably.
For this reason, there was a problem that the production yield was reduced.

[0013]

As described above, it is extremely difficult to control the impurity diffusion, and it is necessary to reduce the depth of the impurity diffusion layer when miniaturizing the element.
It is very difficult to implant a shallow impurity layer at a relatively high concentration, and there are various problems such as a limit in making the impurity layer shallow.

The present invention has been made in view of the above circumstances, and has as its object to provide a method of easily forming a diffusion layer with good controllability when diffusing an impurity into a semiconductor layer.

[0015]

According to a first aspect of the present invention, there is provided a defect source forming step of forming a defect source by introducing a first impurity into or on a semiconductor substrate;
Forming a diffusion source having an impurity at a position away from the defect source; and performing heat treatment to diffuse the first impurity from the defect source, thereby forming a lattice defect concentration higher than a concentration in a thermal equilibrium state. And a lattice defect generating step of generating a lattice defect having the following formula: wherein the second impurity is diffused from the diffusion source in the presence of the generated lattice defect.

Preferably, the lattice defect generating step is a step of forming a high-concentration phosphorus diffusion layer.

Desirably, the lattice defect generation step is a vacancy generation step of forming a vacancy by silicidation by forming a metal film such as a titanium layer or a nickel layer on the substrate surface.

According to the second aspect of the present invention, an interstitial atom is generated for an inverse type of defect which supports the diffusion speed of an impurity to be diffused, that is, a vacancy is generated for an interstitial atom. In addition, control is performed so as to reduce the concentration of lattice defects of the type that contribute to impurity diffusion by recombination.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, the diffusion source is formed on a back surface of the semiconductor substrate.

Desirably, the concentration of the lattice defect is controlled by adjusting the contact area between the defect source and the substrate to control the concentration of the lattice defect of the type contributing to impurity diffusion.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the first or second aspect, the diffusion source is locally formed on a back surface of the semiconductor substrate.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the first to fourth aspects, prior to the lattice defect generating step, an irregularity forming step of forming irregularities on the back surface of the semiconductor substrate is included.

[0023]

The present invention focuses on the fact that the diffusion phenomenon of impurities depends on the type and concentration of lattice defects, and controls the concentration of lattice defects in a wide concentration region to control impurity diffusion. is there.

According to the above arrangement, a lattice defect having a desired lattice defect concentration higher than the concentration in a thermal equilibrium state is generated, and the lattice defect assists or suppresses the diffusion in a thermal process for diffusion. Because
It is possible to obtain a desired diffusion length with extremely controllability.
Further, diffusion at a low temperature becomes possible, and it becomes possible to form a desired diffusion layer while preventing influence on the already formed layer.

As described above, the lattice defects for controlling the diffusion of impurities include vacancies and interstitial silicon atoms, as described above. One method is to directly generate vacancies or interstitial silicon atoms to control impurity diffusion, and the other is to use the opposite type, that is, interstitial atoms for vacancies and interstitial atoms for vacancies. In this method, vacancies are generated and the concentration of lattice defects of this type that contribute to impurity diffusion by recombination is reduced.

In any case, impurity diffusion can be controlled with high precision.

There are two general methods for generating such lattice defects.

The first is a method of diffusing phosphorus from a glass containing a high concentration of phosphorus into a silicon substrate, a method of ion-implanting a high concentration of phosphorus such as an ion beam irradiation step, and the like.
The introduction of a high concentration of phosphorus, which produces interstitial silicon atoms.

The second is a method in which a metal such as titanium or nickel is brought into contact with the surface of a silicon substrate to generate silicidation, thereby generating a vacancy at the interface.

The occurrence of such lattice defects is not limited to the surface of the substrate, but is generated on the surface of the substrate according to the situation near the surface of the silicon substrate, that is, the formation of other diffusion layers or various films. If this is not possible, it may be made to occur on the back of the substrate in the manner described above. In this case, it is necessary to set the distance from the back surface to the target impurity diffusion layer. In this case, local diffusion can be selectively supported by reducing the source of the lattice defect and reducing the distance to the diffusion source to such an extent that lateral diffusion can be ignored.

Further, the concentration of lattice defects can be controlled by the density of formation of defect sources. For example, it can be controlled by forming a defect source on a substrate through a mask having windows formed at a desired density. Further, the effective value of the defect concentration can be increased by forming irregularities on the surface of the silicon substrate and forming a defect source on the irregularities. That is, how much the lattice defect concentration is changed depends on
In generating a defect, the defect is adjusted by changing the defect introduction area. For example, when a chemical reaction between silicon and various metals is used as a method for introducing a defect, an area where the metal, which is a defect source area, is applied when the metal is attached to the silicon surface. Further, for example, the area of the high-concentration phosphorus diffusion layer is changed. Further, in order to increase the lattice defect concentration more remarkably, irregularities are formed on the back surface of the silicon substrate in order to increase the total amount of lattice defects. Thereby, the effective value of the defect generation area can be increased. As described above, according to the present invention, after the impurity is introduced into the semiconductor layer, prior to the thermal process for diffusion, a lattice defect having a desired lattice defect concentration higher than the concentration in the thermal equilibrium state is generated, and the lattice defect is generated. Thereby, diffusion of impurities can be suppressed or promoted, and the diffusion depth can be controlled with high precision.

Further, by forming a high-concentration phosphorus diffusion layer by ion implantation or diffusion from a glass layer containing high-concentration phosphorus, interstitial atoms are generated at the interface, thereby diffusing phosphorus and boron. Can be promoted.

In addition, the diffusion of antimony and arsenic can be promoted by forming a titanium layer or a nickel layer on the substrate surface and generating vacancies by silicidation.

According to the second aspect of the present invention, an interstitial atom is generated for an opposite type of defect which supports the diffusion speed of an impurity to be diffused, ie, a vacancy, and a vacancy is generated for an interstitial. By controlling the concentration of lattice defects of the type contributing to impurity diffusion by recombination to be reduced, diffusion can be suppressed and a shallow diffusion layer can be formed.

In order to control the defect concentration in the vicinity of the surface of the substrate, the concentration of the recombination center on the substrate surface is adjusted. This is done by controlling the amount of damage with good controllability by the etching time of reactive ion etching (RIE), or by injecting holes into the surface while nitriding the surface with NH ₃ gas and controlling the amount by the temperature and time. Or you can do it.

In the third aspect of the present invention, another layer is formed on the surface by generating lattice defects on the back surface side of the substrate and controlling the concentration of the lattice defects of the type contributing to impurity diffusion by diffusion of the defects. In this case, it can be easily controlled.

As described above, the diffusion of the conductive impurities in the silicon substrate at a low temperature is greatly affected by the amount of point defects. The greater the amount of point defects, the faster the diffusion of impurities. Moreover, the diffusion of point defects is several orders of magnitude faster than the diffusion of conductive impurities. FIG.
6 and 18 show the results of measuring the diffusion rate of interstitial silicon and the diffusion rates of boron and phosphorus in silicon. For example, interstitial silicon which is a point defect at 800 ° C. is 6 orders of magnitude faster than the diffusion rate of boron or phosphorus. Therefore, by controlling the amount of point defects, the diffusion of impurities can be controlled, and an arbitrary impurity distribution can be obtained by a heat treatment at 800 ° C. to 850 ° C., which is lower than in the prior art.

In particular, by promoting recombination of point defects on the substrate surface, the amount of point defects in the immediate vicinity of the substrate surface is reduced, and impurities are diffused deeply into the substrate by heat treatment while leaving only the impurities on the substrate surface. This allows a junction to be formed in a very shallow region of the substrate surface.

Further, when lattice defects were introduced into a silicon substrate, the extent to which the increase in the concentration of lattice defects accelerated the diffusion of conductive impurities was measured.

The results are shown in FIG.
A boron diffusion layer is formed in advance in the vicinity of the surface of a silicon substrate having a thickness of μm, a glass containing high concentration of phosphorus is attached to the back surface, and a profile of boron impurities when heat-treated at 850 ° C. is obtained by SIMS analysis or the like. The result of the calculation and the diffusion coefficient calculated from this is shown. FIG. 18 also shows the diffusion coefficient of boron when heat treatment was performed under the same conditions without attaching glass. According to FIG. 18, it can be seen that the diffusion coefficient of boron greatly increases due to lattice defects generated from the high-concentration phosphorus diffusion layer. At this time, the concentration Ci of the defect is controlled by the area of the glass to be attached to the silicon substrate, and the result is also shown. Ceq indicates the thermal equilibrium concentration. From these results, it can be seen that the diffusion coefficient of boron is approximately two orders of magnitude faster when the amount of interstitial silicon is increased by two orders of magnitude than the thermal equilibrium concentration condition. This is the same when phosphorus is used as an impurity. Also, it can be seen that the effect on the impurities increases as the temperature decreases. It can be seen that similar results are obtained when other methods for introducing lattice defects are used.

Further, in the case of the defect introduction method using PSG, it can be seen that the amount of defects to be introduced is controlled also by the phosphorus concentration in the glass. For example, as shown in FIG.
If the phosphorus concentration is 2 × 10 ²¹ atom / cm ³ at 00 ° C., it is possible to introduce defects whose quantity is two orders of magnitude higher than the equilibrium interstitial silicon atom concentration at 800 ° C. Therefore, the diffusion speed of boron can be increased by two orders of magnitude. This is 80
This means that diffusion comparable to diffusing boron at 1000C at 0 ° C can be performed. According to the fourth aspect of the present invention, if a lattice defect is locally generated on the rear surface side of the substrate and the concentration of the lattice defect of the type contributing to impurity diffusion is increased by local diffusion of the defect, the local It is possible to perform a deep diffusion.

The control of the diffusion speed can also be performed as follows.

When the total area of the lattice defect sources is different, in the vicinity of the lattice defect source, the isoconcentration lines of the lattice defect concentration are distributed almost concentrically around the source.
As one moves away from the source, the concentration becomes uniform by diffusion.
This uniformized concentration can be adjusted by changing the distribution density (total area) of the lattice defect sources. In other words, the lattice defect concentration at locations separated by the same distance increases as the distribution density increases (the total area increases). Therefore, the movement of the impurities becomes faster in the order of higher lattice defect concentration. By performing high-concentration phosphorus diffusion from the PSG film and changing the total amount of lattice defects generated from the high-concentration phosphorus diffusion layer by the distribution density (total area) of the diffusion window, the movement and distribution of boron are controlled. The square root of density has a clean linear relationship. Therefore, the movement of boron can be controlled using the distribution density as a parameter.

[0044]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Example 1 First, phosphorus (n) formed in a p-type silicon substrate 101 was formed.
(Type) Diffusion control from the buried layer 104S will be described.

In this method, as shown in FIG. 1A, a phosphorus (n-type) buried layer 1 is previously placed at a depth of 10 μm.
A glass layer 103 containing a high concentration of phosphorus is formed on the surface of the p-type silicon substrate 101 on which the 04S (region indicated by the broken line) is formed via a mask pattern 102 made of a silicon nitride layer. A high-concentration phosphorus diffusion layer 105 is selectively formed by introducing phosphorus, and interstitial silicon atoms 1 generated from the high-concentration phosphorus diffusion layer 105 are formed.
06 intends to support phosphorus diffusion from the buried layer. After the heat treatment at 900 ° C. for 1 hour, the diffusion length increases in the region opposed to the high-concentration phosphorus diffusion layer 105 as shown by the solid line, and the phosphorus (n-type) buried layer 104 is thicker but not opposed. There is almost no diffusion length extension in the region.

In this method, the interstitial silicon atoms generated in the high-concentration phosphorus diffusion layer 105 on the surface diffuse and reach the vicinity of the phosphorus (n-type) buried layer 104S as a diffusion source to support the diffusion of phosphorus. As a result, the diffusion length is increased, and a locally thick buried layer 104 is formed.

As a modification, as shown in FIG. 1B, the buried diffusion layer is an arsenic (n-type) buried layer 205S.
In this case, the titanium film 203 is replaced with the mask pattern 20 instead of the high-concentration phosphorus diffusion layer 105 formed on the surface.
2 and a titanium silicide layer 2 at the interface with silicon.
No. 04 is formed, thereby generating a vacancy, and the diffusion of the vacancy intends to support arsenic diffusion from the buried layer. After the heat treatment at 850 ° C. for 1 hour, the diffusion length increases in the region facing the titanium silicide layer 204 and the arsenic (n-type) buried layer 205 increases in the region facing the titanium silicide layer 204 as indicated by the solid line, whereas almost the region in the region not facing the titanium silicide layer 204 does No diffusion length spread is observed.

In this way, the diffusion length can be locally controlled by the interstitial atoms or vacancies. Further, in this method, the activation rate of impurities at a low temperature can be improved.

In this example, lattice defects are introduced into the substrate by diffusion. Therefore, it is necessary to set the distance (depth) to the target impurity diffusion layer in consideration of the diffusion coefficient of the lattice defect. The relationship between the lattice defect concentration and the depth after the heat treatment at 900 ° C. for 5 hours was measured. The result is shown in FIG. Incidentally, the diffusion coefficient of the lattice defect at 900 ° C. is 1 × 1 from FIG.
It was 0 ^-9 cm ² / s. From this figure, it can be seen that it is desirable to keep the distance from the defect source to 100 μm or less.

In this embodiment, a phosphorus (n-type) buried layer is formed as a buried layer. However, it is needless to say that the present invention can be applied to the formation of a p-type buried layer of boron or the like.

Embodiment 2 As a second embodiment of the present invention, the following experiment was conducted to quantitatively measure a change in diffusion rate due to lattice defects.

Although not shown here, a diffusion layer of boron as a p-type impurity is previously formed near the surface of an n-type silicon substrate having a thickness of about 10 μm, and the back surface contains high-concentration phosphorus as a defect source. Forming a glass layer, 850
FIG. 3 (a) shows the results of measuring the boron diffusion depths after 5 hours and 16 hours when the heat treatment was performed at ℃. For comparison, FIG. 3 (b) shows the results of measuring the boron diffusion depth after 5 hours and 16 hours when the glass layer containing high concentration phosphorus was not formed on the back surface. From these comparisons, it can be seen that the diffusion coefficient of boron becomes 50 times or more that of the case where no defect is introduced due to the introduction of the defect, and the diffusion is greatly promoted.

This is presumably because interstitial silicon atoms generated by the introduction of high-concentration phosphorus assisted boron diffusion and increased the diffusion length. In particular, in the case of phosphorus, the effect of the lattice defect becomes more remarkable as the diffusion temperature is lowered.

The thickness of the substrate was changed by 5 μm,
Similarly, a lattice defect is generated on the back surface, and the diffusion coefficient of boron is measured to be 9 × 10 ⁻¹⁵ cm ² / s for a 5 μm substrate, whereas it is 8 × 10 ⁻¹⁵ cm ² / s for a 10 μm thick substrate.
s. When the diffusion temperature is 50 μm or more at a diffusion temperature of 850 ° C., the effect of increasing the diffusion coefficient by introducing lattice defects from the back surface is not observed.

Embodiment 3 Next, as a third embodiment of the present invention, a method of controlling the lattice defect concentration by changing the area of the lattice defect source will be described.

In this method, as shown in FIG. 4A, a mask 302 made of a silicon nitride film is formed on the surface of a silicon substrate 301, and openings H are formed in the masks in regions A to C at three levels of density. Then, a glass layer containing high-concentration phosphorus is formed as an upper layer, and lattice defect sources 303 are formed in accordance with the density of the openings H.

At this time, the lattice defect density is equal to the density line 304.
It can be seen from the graph that CAB in the region where the concentration of the lattice defect source 303 increases becomes deeper in the order of CAB.

A similar diffusion source is formed to form boron (p
FIG. 4 shows a case where diffusion from the buried layer 305 is performed.
As shown in (b), the extension of the diffusion length depends on the lattice defect source 303.
It can be seen that CAB increases in the order of CAB in the region where the density of the GaN increases.

The openings H have a circular shape of about 1 μm and are regularly arranged. The lattice defect spreads concentrically from this opening H, but when the depth Z increases, XY
The concentration in the direction is made uniform by diffusion. This uniform concentration can be adjusted by changing the distribution density (total area) of the lattice defect sources as in the regions A and B.

The area of the lattice defect source is calculated as 1/4, 1/9, 1/16, 1 /
FIG. 5A shows the result of measuring the elongation of the boron diffusion layer when it was changed to 25, 1/36, and 1/49. FIG. 5B shows a similar measurement result when the thickness of the substrate is 5 μm. From these results, it is understood that the elongation of the diffusion length of boron and the square root of the diffusion source density have a linear relationship.
Therefore, it can be understood that the elongation of the diffusion length of boron can be controlled by controlling the distribution density.

The shape of this opening is not limited to a circle, but can be modified as shown in FIG.

As a modified example, conversely, as shown in FIG. 7, it is possible to increase the surface area by forming irregularities on the surface where lattice defects are generated.

In this case, as shown in FIG. 7, a glass layer 402 containing a high concentration of phosphorus is formed on the back surface of the silicon substrate 401 so that the density gradually changes, and a glass layer 402 containing a high concentration of phosphorus is formed. Is to be increased. As a result, as shown by the isoconcentration line 405 of the defect, it can be seen that the defect is diffused deeper as the formation density of the unevenness increases. Here, reference numeral 402 denotes a high-concentration phosphorus diffusion layer;
Reference numeral 3 denotes a low-concentration phosphorus diffusion layer. If the surface area is increased ten times, the defect concentration can be increased approximately ten times.

Embodiment 4 Hereinafter, an example of application to an actual device will be described.

FIGS. 8A to 8E show a manufacturing process in the case where an extremely thin p + type diffusion layer is formed as a source / drain region of a MOSFET by using the method of the embodiment of the present invention. It is a process sectional view.

First, as shown in FIG. 8A, an element isolation insulating film 2 is formed in an n-type silicon substrate 1 by a normal LOCOS method, and then a 10-nm-thick silicon oxide film is formed by a thermal oxidation method. A layer and a polycrystalline silicon film having a thickness of 300 nm are deposited and patterned by a photolithography method and a reactive ion etching method to form a gate insulating film 3g.
After forming the gate electrode 3, boron is ion-implanted into the source / drain region as a p-type impurity to form an ion-implanted layer 4.

Thereafter, prior to annealing for activating boron, the back surface of the silicon substrate 1 is shaved by etching or the like so as to have a thickness of 100 μm.
A silicon oxide film 5 is deposited on the back surface of the substrate by a CVD method. (Also, the thickness of the silicon substrate as a starting material may be set in advance so as to be 100 μm in this state.) Thereafter, as shown in the overall view in FIG. A square opening h of 1 μm × 1 μm is formed.

Then, as shown in FIG. 8C, a titanium film 6 is formed on the entire back surface of the substrate 1. Here, a nickel film may be used instead of the titanium film.

In this state, annealing is performed in a vacuum at 800 ° C. or in an inert gas atmosphere to convert titanium in the opening h on the back surface into titanium silicide 7 by an interface reaction. At this time, as shown in FIG. 8D, vacancies 8 are generated from the back surface of the substrate and diffuse toward the front surface. As a result, the vacancies recombine with interstitial silicon atoms near the substrate surface, and reduce interstitial silicon atoms near the substrate surface. Here, the ion-implanted layer 4 is implanted into the substrate surface.
Is an impurity whose diffusion is assisted by interstitial silicon atoms. Therefore, if the density of the openings h is set by the process shown in FIG. 8B so that the concentration of both lattice defects is reduced by recombination, the number of interstitial silicon atoms is reduced by the recombination. Lattice defects that support boron diffusion are reduced and the diffusion rate is reduced. As a result, a shallow diffusion layer 10 can be formed.

Then, as shown in FIG. 8 (d), the titanium 6 and the titanium silicide film 7 on the back surface are peeled off by washing with a treatment solution using an acid, and the surface is covered and protected with a silicon nitride film or the like. The silicon oxide film 5 on the back surface is peeled off with hydrofluoric acid or the like, and the protective film on the front surface is removed, so that a MOSFET having a shallow source / drain diffusion layer 10 can be obtained.

Thereafter, a barrier metal, a lead wiring, and the like are formed by a known method to complete the MOS transistor.

As described above, according to the method of the embodiment of the present invention, a shallower p + diffusion layer can be formed.

Embodiment 5 FIGS. 9 (a) to 9 (d) show a case where an extremely thin n + type diffusion layer is formed as a source / drain region of a MOSFET using the method of the embodiment of the present invention. It is a process sectional view showing a process.

First, as shown in FIG. 9A, an element isolation insulating film 12 is formed in a p-type silicon substrate 11 by a normal LOCOS method, and a film thickness of 10 nm is formed by a thermal oxidation method.
After depositing a silicon oxide layer having a thickness of 300 nm and a polycrystalline silicon film having a thickness of 300 nm and patterning them by a photolithography method and a reactive ion etching method, a gate insulating film 13g and a gate electrode 13 are formed. Antimony as a type impurity is ion-implanted into the source / drain regions to form an ion-implanted layer 14.

Thereafter, prior to annealing for activation of antimony, the back surface of the silicon substrate 11 is shaved by etching or the like so as to have a thickness of 100 μm. An Angstrom silicon nitride film 15 is deposited. (Also, the thickness of the silicon substrate as a starting material may be set in advance so as to be 100 μm in this state.) Thereafter, as shown in FIG.
A circular opening H of 1 μm × 1 μm is formed by photolithography.

Then, as shown in FIG. 9C, a glass layer 16 containing a high concentration of phosphorus and having a thickness of 2,000 Å is formed on the entire back surface of the substrate 11 by the CVD method, and the surface of the substrate 11 is formed by the sputtering method. A nickel film 19 is deposited.

In this state, annealing is performed in a vacuum at 850 ° C. or in an inert gas atmosphere, and nickel on the surface of the ion-implanted layer 14 in the region in contact with silicon, ie, in the source / drain region, is subjected to nickel by an interface reaction. Turns into silicon side 17. At the same time as vacancies are generated during the silicidation, interstitial silicon atoms 20 are generated from the high-concentration phosphorus-containing glass layer 16 on the back surface of the substrate and diffuse toward the surface. Since the interstitial silicon atoms 20 diffuse faster than the vacancies 18, they are good near the surface and both defects meet and recombine.

Therefore, also in this case, if the density of the openings H is set by the process shown in FIG. The reduction in the number of lattice defects that support the diffusion of antimony is reduced, and the diffusion speed is reduced. As a result, a shallow diffusion layer 21 can be formed.

Then, as shown in FIG. 9D, after the high-concentration phosphorus-containing glass layer 16 on the back surface is peeled off, the nickel 19 and the nickel silicide film 17 on the front surface are patterned to form wirings, and the surface is further formed. The silicon nitride film 15 on the back surface is peeled off with hydrofluoric acid or the like while being covered and protected by a silicon oxide film or the like, and the protective film on the front surface is removed, whereby a MOSFET having a shallow source / drain diffusion layer 21 can be obtained.

Thereafter, a barrier metal, a lead wiring, and the like are formed by a known method to complete a MOS transistor.

As described above, according to the method of the embodiment of the present invention, a shallower n + diffusion layer can be formed.

In this embodiment, the reduction of the diffusion rate has been described. However, if only the generation of vacancies due to the silicidation of the front surface and the diffusion of interstitial silicon atoms from the back surface are not performed, the diffusion speed is reduced. It goes without saying that the speed is increased and a deep diffusion layer is formed.

The impurity to be diffused is phosphorus or the like.
When diffusion is assisted by interstitial silicon atoms, silicidation is only performed at the surface, and the generation of vacancies due to silicidation causes interstitial silicon atoms present near the surface to be re-established. As a result, the concentration of interstitial silicon atoms is reduced, so that diffusion can be suppressed and shallow diffusion can be performed.

Embodiment 6 FIGS. 10 (a) and 10 (b) show that a p + diffusion layer connecting a buried collector contact layer of a bipolar transistor to a surface electrode by using the method of the present invention has directionality. FIG. 4 is a process cross-sectional view showing a manufacturing process when forming at a low temperature.

First, as shown in FIG. 10A, antimony is applied to the surface of the p-type silicon substrate 31 by n-type.
After forming an n @ + layer 32 serving as a buried collector contact layer containing a p-type impurity, a p-type silicon layer is deposited by an epitaxial growth method, and n-type diffusion as a collector is reached so as to reach the n @ + layer 32 from the surface. Layer 33
Are further formed in the n-type diffusion layer 33, and a p-type diffusion layer 34 as a base layer and an n @ + diffusion layer 3 as an emitter layer are formed.
5 is formed.

In this state, an n + diffusion layer 36 for contacting the buried collector contact layer is formed. Phosphorus ions are selectively implanted into a predetermined region of the surface, and thereafter, the activity of this phosphorus is reduced. Prior to annealing for the formation of silicon, the back surface of the silicon substrate 31 is shaved by etching or the like so as to have a thickness of 20 μm, and a silicon nitride film 37 having a thickness of 500 Å is deposited on the back surface of the substrate 31 by CVD. 1 μm × 1 μm having a tapered surface such that the opening narrows toward the substrate surface in a region facing the ion implantation region on the surface by photolithography
Is formed.

Then, in the same manner as in Example 5, a 10 μm-thick silicon layer 38 is formed on the entire back surface of the substrate 31, and irregularities are formed on the surface. The layer 39 is formed by a CVD method.

In this state, annealing is performed in a vacuum at 800 ° C. or in an inert gas atmosphere to selectively diffuse vertically from the phosphorus ion-implanted layer and to reach the n + contact layer 36 so as to reach the collector contact layer 32. To form

At this time, the interstitial silicon atoms 40 are generated from the high-concentration phosphorus-containing glass layer 39 on the back surface of the substrate. The taper gives directionality and can be diffused toward the surface,
The interstitial silicon atom concentration at a desired position can be increased several hundred to several thousand times.

Thus, the interstitial silicon atoms 40
Is rapidly diffused toward the surface even at low temperatures, supports the diffusion of phosphorus, and has a directional n + contact layer 3.
6 can be formed.

On the other hand, in the case of a buried collector contact layer containing antimony whose diffusion is assisted by vacancies, the vacancies recombine with interstitial silicon atoms diffused from the back surface, and as a result, the number of nearby vacancies decreases. And diffusion is suppressed.

In this method, deep diffusion can be selectively performed at a low temperature, so that a contact layer can be formed without affecting other diffusion layers.

As described above, according to the method of the embodiment of the present invention, it is possible to locally form a deep n + diffusion layer.

Embodiment 7 FIGS. 11 (a) to 11 (c) show a case where an extremely shallow n + type diffusion layer is formed as a source / drain region of a MOSFET using the method of the present invention. It is a process sectional view showing a process.

First, as shown in FIG. 11 (a), an element isolation insulating film 12 is formed in a p-type silicon substrate 11 by a normal LOCOS method, and boron is ion-implanted as a p-type impurity. An ion implantation layer 54 is formed.

Thereafter, as shown in FIG. 11 (b), before annealing for activating boron, a PSG film 55 is formed in the source / drain formation region on the surface of the silicon substrate 11, and this is formed. By patterning, the substrate surface in the channel region is exposed. And this PSG
A source / drain region 53 is formed by diffusion of phosphorus from the film 55. Here, the impurities are activated by heat treatment at 950 ° C. for 5 minutes, and then heat treatment at 800 ° C. for 30 minutes. At this time, a large amount of point defects (interstitial silicon atoms) are injected into the substrate along with the diffusion of phosphorus. The diffusion of the previously implanted boron is accelerated by the large number of point defects having a very high diffusion rate.

In this way, as shown in FIG. 11C, the region other than boron near the substrate surface in the region corresponding to the channel of the device diffuses deeply, and as a result, the channel region has a depth of 30%.
A p-type diffusion layer having a shallowness of nm could be formed. Here, in the vicinity of the surface corresponding to the channel, the amount of point defects that accelerates the diffusion of boron decreases due to recombination of point defects on the surface. Therefore, as described above, boron near the surface corresponding to the channel remained without being diffused.

Thereafter, a gate insulating film and a gate electrode are formed to complete the MOSFET. Thus, according to the method of the embodiment of the present invention, a shallower channel layer can be formed.

Conventionally, impurities such as phosphorus and boron are implanted into the source / drain region and the channel region, respectively, and heat treatment is performed. However, boron in the channel region diffuses deeply, and a shallow diffusion layer cannot be obtained. There was a problem.

It should be noted that phosphorus or arsenic is ion-implanted,
Even when boron ions are implanted from the BSG film using the BSG film, almost the same effect can be obtained.

Embodiment 8 FIGS. 12 (a) to 12 (c) show that the method of the present invention
FIG. 7 is a process cross-sectional view showing a manufacturing process when an extremely shallow p + type diffusion layer is formed as a channel region of an OSFET.

First, as shown in FIG. 12A, an element isolation insulating film 12 is formed on a p-type silicon substrate 11 by a normal LOCOS method, and then boron is ion-implanted as a p-type impurity to form a near-surface region. Next, an ion implantation layer 54 is formed. Then, a PSG film 55 is further formed and patterned, and the substrate surface in the channel region is exposed, and RIE is performed.
Causes damage D.

Thereafter, as shown in FIG.
When heat treatment is performed at 2 ° C. for 2 hours, point defects (interstitial silicon atoms) are implanted from the PSG, and the recombination of the implanted point defects particularly occurs on the damaged surface. The defect disappears more rapidly than in the case shown in FIG. Thus, especially by reducing the concentration of point defects at this surface, the diffusion of boron in only a few atomic layers of the surface was extremely slowed, and the diffusion in other regions was accelerated.

As a result, as shown in FIG. 12C, an extremely thin p layer having several atomic layers could be formed.

Thereafter, for example, by LPCVD, 40
A gate insulating film and a gate electrode are formed at 0 to 600 ° C. to complete a MOSFET.

As described above, according to the method of the present invention, a shallower channel layer can be formed.

FIG. 13 shows the relationship between the recombination speed on this surface and the logarithm of the point defect concentration (interstitial concentration). X (μ
m) is the depth from the substrate surface. 1 × 10 ¹⁷ atom / cm
^When the phosphorus concentration of the PSG film is adjusted so as to introduce the point defect of No. ³ , RIE damage is caused so that the surface recombination speed becomes 2.5 × 10 ⁻⁴ cm / h. The point defect density at a depth of 0.0 μm can be reduced by two orders of magnitude. The diffusion of the impurity was approximately proportional thereto, and the diffusion at the surface could be two orders of magnitude slower than the diffusion below.

Embodiment 9 FIGS. 14 (a) to 14 (c) show that M is obtained by using the method of the present invention.
FIG. 9 is a process cross-sectional view showing a manufacturing process when an extremely shallow i (intrinsic) layer is formed as a channel region of an OSFET.

First, as shown in FIG. 14A, after an element isolation insulating film 12 is formed in a p-type silicon substrate 11 by a normal LOCOS method, boron as a p-type impurity and boron as an n-type impurity are formed. An equivalent amount of phosphorus is ion-implanted, and the surface is selectively damaged by RIE. Then, a PSG film 55 is formed and patterned, and a window is opened on the substrate surface in the channel region at 850 ° C. for 2 hours. Heat treatment, and point defects (interstitial silicon atoms) from PSG
Inject.

At this time, as shown in FIG. 14 (b), on the surface without damage, the impurity is accelerated and diffused by the injection of the point defect. Due to the difference between the diffusion rates of phosphorus and boron at this time, a deep phosphorus diffusion layer (n − layer) 56 and a shallow boron diffusion layer (p − layer) 57 are formed. At this time, recombination of the implanted point defects occurs on the damaged surface, and the accelerated diffusion of impurities does not occur on the very surface of the substrate because the defects are largely lost. Thus, a shallow i-layer 58 is formed.

Thus, as shown in FIG. 14C, a channel region formed of a shallow i-layer 58 and a source / drain region formed of a shallow boron diffusion layer (p − layer) 57 are formed. Thereafter, a gate insulating film and a gate electrode are formed to complete the MOSFET. Thus, according to the method of the present embodiment, a shallower channel layer can be formed.

This method can be applied to the formation of a bipolar transistor.

Embodiment 10 FIGS. 15 (a) to 15 (c) show interstitial silicon atoms and lattice defects on a substrate surface by utilizing lattice defects caused by nitridation in an NH ₃ atmosphere instead of RIE damage. Are combined and eliminated.

First, as shown in FIG. 15A, after an element isolation insulating film 12 is formed in a p-type silicon substrate 11 by a normal LOCOS method, boron is ion-implanted as a p-type impurity, Next, an ion implantation layer 54 is formed. Then, a PSG film 55 is further formed and patterned to expose the substrate surface in the channel region.

Thereafter, as shown in FIG. 15B, a heat treatment is performed in an N ₂ atmosphere at 950 ° C. for 30 minutes to cover the entire surface with the silicon nitride film 60 and to directly contact the silicon nitride film. A damage (lattice defect) D is formed by nitriding. Thereafter, when heat treatment is performed at 850 ° C. for 2 hours, point defects (interstitial silicon atoms) are implanted from the PSG, and recombination between the lattice defects of the damage D and the implanted point defects is performed on the surface having the damage D. And defects disappear on the very surface of the substrate. In particular, by reducing the concentration of point defects at this surface, the diffusion of boron in only a few atomic layers of the surface was extremely slowed and the diffusion in other regions was accelerated. Therefore, as shown in FIG. 15 (c), an extremely thin p layer having several atomic layers could be formed.

Thereafter, a gate insulating film and a gate electrode are formed to complete the MOSFET. Thus, according to the method of the present invention, a shallower channel layer can be formed.

It should be noted that without being limited to the above-described embodiment,
The present invention is applicable to formation of various devices such as formation of a double diffusion layer, that is, a so-called HiC structure, or formation of a double diffusion layer with high precision on the surface of a groove in formation of a DRAM.

For example, a dynamic RAM (DRAM)
In the MOS capacitor which is a component of the method, a method of substantially increasing the capacitance without increasing the occupied area by forming a groove in the surface of the silicon substrate and forming the capacitor in the groove has been studied. I have. However, to improve the reliability of the time dependent breakdown of capacitors, 0V potential of the upper electrode, it is necessary to distinguish between the memory contents by a 5V, 10 × 10 ¹⁸ cm of the substrate opposite conductivity type on the silicon substrate surface A method of forming an impurity diffusion layer having a concentration of ^-3 or more has been adopted.

In the case of a DRAM, since a large number of cells are arranged, the problem that the isolation withstand voltage between the impurity diffusion layers of the capacitors formed in the trenches decreases as the distance between the trenches becomes shorter when the density is increased. There is.

In order to solve this problem, for example, when an n-type impurity diffusion layer is formed on the surface of a groove on a p-type substrate, a p-type impurity having a concentration slightly higher than the substrate concentration is formed below the impurity diffusion layer on the surface of the groove. Is formed to form a double diffusion layer, that is, a so-called HiC structure.
It has also been found that this HiC structure has a strong soft error resistance when the capacitance is reduced.

With the conventional method, it is extremely difficult to form a double diffusion layer on the surface of the groove with high precision. As a doping technique, the concentration of the bottom and side walls of the groove is reduced by a general ion implantation method. It is difficult to ensure uniformity, and in diffusion from a silicon oxide film containing impurities called doped glass, it is easy to ensure uniformity in the concentration of the bottom and side walls, but it is easy to ensure In each case, the film formation and the diffusion / separation steps must be repeated, and the number of steps is greatly increased. However, according to the present invention, lattice defects are controlled by introducing lattice defects from the back surface. This makes it possible to simultaneously diffuse a plurality of impurities into a desired profile with good controllability. Further, the formation of the diffusion layer inside the deep groove can be performed with extremely high controllability.

[0123]

According to the method of the present invention, a lattice defect having a desired lattice defect concentration higher than the concentration in a thermal equilibrium state is generated, and the lattice defect assists or suppresses diffusion in a thermal process for diffusion. Therefore, it is possible to obtain a desired diffusion length with extremely high controllability. Furthermore, diffusion at a low temperature is also possible, and it is possible to form a desired diffusion layer while preventing an effect on an already formed layer.

[Brief description of the drawings]

FIG. 1 is a view showing a method for introducing impurities according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a result of measuring a relationship between a lattice defect concentration and a depth after a heat treatment at 900 ° C. for 5 hours.

FIG. 3 is a diagram showing a relationship with the boron diffusion rate due to the presence of a phosphorus diffusion layer.

FIG. 4 is a diagram showing a relationship between diffusion source concentration and diffusion.

FIG. 5 is a diagram showing a relationship between a pattern density and a boron diffusion depth.

FIG. 6 is a diagram showing a modification of the pattern of the diffusion source.

FIG. 7 is a diagram showing a modification of the diffusion source.

FIG. 8 is a manufacturing process diagram of the MOSFET according to the fourth embodiment of the present invention.

FIG. 9 is a manufacturing process diagram of the MOSFET according to the fifth embodiment of the present invention.

FIG. 10 is a manufacturing process diagram of the bipolar transistor according to the sixth embodiment of the present invention.

FIG. 11 is a manufacturing process diagram of the MOSFET according to the seventh embodiment of the present invention.

FIG. 12 is a manufacturing process diagram of the MOSFET according to the eighth embodiment of the present invention.

FIG. 13 is a diagram showing the relationship between the recombination speed on the surface and the concentration of point defects in the eighth embodiment of the present invention.

FIG. 14 is a manufacturing process diagram of the MOSFET according to the ninth embodiment of the present invention.

FIG. 15 is a manufacturing process diagram of the MOSFET according to the tenth embodiment of the present invention.

FIG. 16 is a diagram showing the relationship between the diffusion rate of interstitial silicon atoms and temperature.

FIG. 17 is a diagram showing a relationship between equilibrium interstitial silicon atom concentration and temperature.

FIG. 18 is a diagram showing the relationship between the diffusion coefficient of interstitial atoms and temperature.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 silicon substrate 2 device isolation region 3 gate electrode 4 diffusion layer 5 silicon oxide film 6 titanium layer 7 titanium silicide layer 8 vacancy 9 interstitial silicon atom 10 source / drain region 12 device isolation region 54 ion implantation layer 55 PSG film 56 n layer 57 p-layer 58 i-layer

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-35720 (JP, A) JP-A-1-307215 (JP, A) JP-A-2-205016 (JP, A) JP-A-63- 313816 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/225

Claims (5)

(57) [Claims] 1. A defect source forming step of forming a defect source by introducing a first impurity into or on a surface of a semiconductor substrate, and separating a diffusion source having a second impurity from the defect source into the semiconductor substrate. Forming a diffusion source at a position; and performing a heat treatment to diffuse the first impurity from the defect source to generate a lattice defect having a lattice defect concentration higher than the concentration in a thermal equilibrium state. A method of manufacturing a semiconductor device, comprising: diffusing the second impurity from the diffusion source in the presence of the generated lattice defect. 2. A defect source forming step of forming a defect source by introducing a first impurity into or on a semiconductor substrate, and separating a diffusion source having a second impurity into the semiconductor substrate from the defect source. Forming a diffusion source at a position; diffusing, from the defect source, a lattice defect of a type opposite to the type of the lattice defect that promotes the diffusion rate of the second impurity by performing heat treatment; Reducing the concentration of lattice defects of a type that promotes speed, and suppressing the diffusion of the second impurity from the diffusion source. 3. The method according to claim 1, wherein the diffusion source is formed on a back surface of the semiconductor substrate. 4. The method according to claim 1, wherein the diffusion source is locally formed on a back surface of the semiconductor substrate. 5. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming irregularities on a back surface of said semiconductor substrate prior to said step of generating lattice defects.