JP3235153B2 - LSI manufacturing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the improvement of semiconductor production technology and reliability technology, and more particularly, to the conventional screening, in which an initial failure after forming a gate electrode can be assembled in a post-process. The present invention relates to a screening method and a screening apparatus for reducing the number of steps required to find a defective state and feed back to a step where a defect has occurred in order to take measures against the defect.

[0002]

2. Description of the Related Art FIG. 1 shows a manufacturing process including a screening process of the present invention, and FIG. 2 shows a manufacturing process including a conventional screening process. In FIG. 2, a screen after a previous process, a wafer inspection, a chip electrical inspection, and an assembling process is conventionally used.
Is being performed. This method is generally used to remove non-destructively latent defects by applying an electric field or current stress to a part of the gate, wiring, semiconductor junction, etc. inside the IC. . But,
Since a part of the gate inside the IC is subjected to stress only at a fixed rate determined by the input pulse, and is an assembled product, the screen is screened from the previous process as shown in FIG.
Until the gate electrode, wiring, semiconductor junction, etc. are broken, especially in the steps after the formation of the gate electrode, the wafer inspection, chip electrical inspection, and assembling steps must be performed before the gate electrode is formed. In order to clarify the cause of the defect, feedback is performed to the previous process, which causes an increase in man-hours and takes time. In addition, in the conventional method, since the product is an assembled product, a lot of time is required because a plurality of processes are required when the product is attached to and detached from a screening device as shown in FIG. And there is a problem that it is economically disadvantageous.

[0003]

According to the present invention, in order to develop a large variety of LSIs in a short period of time in response to an increase in demand for ASICs, burn-in board preparation, input pattern setting, individual IC Eliminates inefficient work such as setting, and all the gates that have become difficult due to the high integration of LSI
New screen that allows you to bias
The purpose of the present invention is to develop and manufacture an LSI by using a thinning method.

[0004]

After a gate electrode is formed in a process as shown in FIG. 1 of the present invention, the wafer is subjected to high-frequency baking in a vacuum or a predetermined diluted atmosphere while performing a high-temperature baking. And applying a high bias in a plasma atmosphere to perform screening. In the above-mentioned screening apparatus, the plasma generator is constituted by alternately combining a plus electrode and a minus electrode.

[0005]

As described above, a high frequency is applied in a vacuum or in a predetermined dilute atmosphere and a plasma atmosphere, and a high-temperature base is applied.
By applying a bias, all the gate oxide films on the wafer can be charged up, and a high bias and a high temperature stress can be applied to the wafer.
By performing the screening for the defect or the like in the previous process, the object of enabling the above-mentioned cause of the defect to be eliminated at an early stage is achieved.

In the above-described screening apparatus, a large number of wafers can be simultaneously screened by alternately combining a plus electrode and a minus electrode in the plasma generator, thereby achieving the above object. You can also.

[0007]

(Embodiment 1) FIG. 1 shows a flowchart of the manufacturing process of the present invention. Comparing FIG. 2 of the prior art with FIG. 1 of the present invention, in FIG. 2 of the prior art, screening is performed on a product after assembly in a post-process, whereas in FIG. 1 of the present invention, screening is performed on the pre-process. It is performed on wafers during the device formation process. By performing the screening in the pre-process as described above, it becomes possible to find and investigate the cause of the defect immediately after the occurrence of the defect, and the defect can be removed in-line, so that the feedback after the defect is found is performed. The man-hour is reduced and the production rate is improved. FIG. 3 shows a conventional screening apparatus in the screening in the post-process of the conventional example shown in FIG. FIG. 3A shows an outline of a currently used screening apparatus, and FIG. 3B shows an enlarged view of A in FIG. In (a), the assembled product is put in a high-temperature bath 2 and the temperature is adjusted to 1 by a temperature controller 3.
High temperature baking is performed at 25 ° C to 150 ° C, and IC
A high voltage Vcc is applied to the power supply pins of the IC by the power supply 1, and an appropriate input pulse is applied to the input pins to apply an electric field or current stress to each gate, wiring, semiconductor junction, etc. inside the IC. , Non-destructively removing initial defects such as gate destruction. Further, it is also possible to set the timer-4 to perform the screening as described above. In order to reduce the number of steps required for feedback, screening is performed in a pre-process, and a novel screening method for improving semiconductor production technology and reliability is described below. FIG. 4 shows a screening device according to the present invention.
First, a vacuum device 10 is used in a plasma generating device 5 to vacuum the inside of a screening device in a vacuum or a dilute atmosphere, for example, 1
0 ² to 10 ³ Pa. Further, in order to perform a high-temperature bake, the temperature in the apparatus is adjusted to 125 by using the temperature controller 3.
C. to 150 ° C., the wafer 8 is inserted between the positive electrode plate 7 and the negative electrode plate 9, and the high frequency power source 6
By applying a high frequency, a plasma is generated, and a high bias is applied to all the gate oxide films, wirings, semiconductor junctions and the like on the wafer 8 to charge up the above-mentioned parts and apply stress. Thereby, contamination and defects in each of the above sections can be found. By such a novel screening method, it is possible to remove defects in the preceding process after the formation of the gate electrode as shown in FIG. 1 of the present invention. Therefore, each of the electrode plates 7 and 9 must be larger than the wafer size. Screening can be performed as described above by setting the timer-4, and the plus electrode 7 and the minus electrode 9 can be reversed by changing the position of GND.
Further, as an example of the plasma generator, a parallel plate type plasma generator is used as an example, but the present invention is not limited to this. In particular, the electrodes of the plasma generator can be employed in various shapes. is there.

(Embodiment 2) FIG. 5 shows an example of a schematic cross-sectional structure of an apparatus in which some of the plus electrode plate 7, the minus electrode plate 9, and the wafer 8 are combined as one unit in the screening apparatus of FIG. . In this apparatus, a positive electrode plate 7 and a negative electrode plate 9 are alternately combined, a wafer 8 is inserted therebetween, and the wafer is screened in the same manner as described above. Since the processing can be performed in a larger amount than in the above case, it is possible to more efficiently remove defects in the previous process after the formation of the gate electrode. Screening can also be performed as described above by setting the timer-4, and the plus electrode 7 and the minus electrode 9 can be reversed by changing the position of GND.

[0009]

(1) Since screening is performed in the previous step, defects can be removed at an early stage, and the number of steps required by feeding back to the previous step can be reduced.

(2) All gates can be biased regardless of the high integration of the LSI.

(3) Since the aging work after the assembly is not required, the number of steps in the post-process can be reduced.

(4) Since gate breakdown can be removed by a stable and uniform plasma bias, high quality can be obtained.

[Brief description of the drawings]

FIG. 1 is a flowchart relating to screening in a pre-process of the present invention.

FIG. 2 is a flow chart of a conventional screening.
G.

FIG. 3 is a configuration diagram of a currently used screening device.

FIG. 4 is a configuration diagram of a screening apparatus of the present invention using plasma used for a wafer after forming a gate electrode.

FIG. 5 is a diagram schematically showing a cross section of a screening apparatus of the present invention capable of coping with screening of a large number of wafers.

[Explanation of symbols]

1 ··· Power source 2 ··· High temperature bath 3 ··· Temperature controller 4 ···
Timer, 5 Plasma generator, 6 High frequency power supply, 7 Plus electrode, 8 Wafer, 9 Negative electrode, 10 Vacuum device A, a part of the currently used screening device

Continuation of front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/66 G01R 31/26

Claims (2)

(57) [Claims] The method according to claim 1 a semiconductor wafer after Gate electrode forming step,
Plasma generator with plus and minus electrodes
And the semiconductor wafer is placed between the two electrodes.
In a vacuum or a predetermined lean atmosphere
A plasma is generated in an atmosphere, and the semiconductor is generated in the plasma.
Screening is performed by baking the body wafer.
A gate electrode forming step for the semiconductor wafer
Manufacturing of an LSI characterized by processing the following steps
Law . 2. The method according to claim 1, wherein said plus electrode and said minus electrode are combined alternately, and a semiconductor wafer is inserted between said electrodes to screen a plurality of semiconductor wafers.
2. The LSI according to claim 1, wherein
Manufacturing method .